Benefits of Code Coverage Analysis

AVMS-05

Agenda
™ Definition of Coverage Analysis

™ Statement/Branch Coverage

™ Expression Coverage

™ Toggle Coverage

™ Functional Coverage (PSL, OVA and SystemVerilog)

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Coverage Analysis

™ Coverage Analysis (in its Electronic Design flavor) measures

how well certain areas of your design are exercised.
™ Although it can be discussed on pure theoretical level,
coverage analysis can be executed practically, in either formal
or functional verification tools (we are concentrating mainly on
the functional aspects here).
™ Coverage analysis can be organized in different ways:
¾ Only source code of the design description is analyzed
(e.g. statement and branch coverage)
¾ Behavior of certain design objects is analyzed
(e.g. toggle coverage)
¾ Properties describing the design are analyzed
(functional coverage using assertions)

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Arguments for Coverage Analysis

™ Growing Complexity of designs

™ Testing Validity of HDL designs

™ Necessity to check numerous corner cases

™ Speed up in Time to Market

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Code Coverage

™ Kind of coverage analyzing frequency of execution of lines of

source code of your design
™ Originated in software development domain and migrated to
electronic design domain
™ Many definitions (frequently conflicting/overlapping) can be
found in the literature; we are presenting common versions
™ As mentioned earlier, we are concentrating on flavors of
coverage that can be verified functionally (e.g. in the process
of simulation)

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Code Coverage - Features

™ The simplest flavor – statement (or line) coverage – checks how

many times each executable statement is executed

™ Shows how effectively your code is exercised (raw count, percentage,

etc.)

™ Highlights the areas not exercised at all (dead code? poor testbench?)

™ More advanced flavor – branch coverage – preprocesses raw data to

provide detailed statistics on conditional statement execution

™ Specifies which branches of if or case statements were visited (and

how frequently)

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Where does it fit in ?
™ Code Coverage in Design Flow

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Key Functions

™ Code coverage data can be collected either on a per-unit or per-

instance basis
™ Default per-unit mode provides cumulative statistics for all instances of
a given unit; per-instance mode add separate entries for each
instance
™ Code coverage data can be turned off for any design region.
™ The code coverage data can be collected only for objects from the
current library or include objects from the external system libraries as
well.
™ Pragmas placed directly in the code can exclude certain areas from the
analysis
™ The Code Coverage viewer shows a synchronized display of the
design structure and the source code with the coverage data.

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Coverage Viewer

™ Statement Count
displays an
execution count
for each line of
the HDL code.

™ Branch Count(BC)
Displays Branch
Coverage data
for the IF or
CASE constructs.

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Coverage in Graphical Form

™ Source code and branch

code coverage can also
be displayed in the
graphical form

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Coverage Merge

™ Efficiency of your test suite can be verified using the Code

Coverage Merge feature.

™ To combine Code Coverage data obtained in two separate

simulation sessions, use the command
• cc merge -merge_branches UUT UUT -dir $DSN\coverage1 -dir
$DSN\coverage2 –dest $DSN\coverage_merged

™ The –merge_hierarchies switch will combine whole trees, if top-

level units have same name and structure
• cc merge -merge_hierarchies -dir $DSN\coverage1 -dir
$DSN\coverage2 –dest $DSN\coverage_merged

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Benefits to the designer

™ Can easily find sections of a model that have not been

exercised by a testbench

™ Helps in identifying sections of the model executed very

frequently

™ Helps in uncovering bugs in the design verification process

immediately during long regression tests

™ Integrated to the simulation kernel

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Expression Coverage

™ Expression coverage is a debugging tool that factorizes

logical expressions and monitors them during simulation
™ An expression is fully covered when all of the expression
cases are exercised
™ How the expression is exercised may depend on different
types of operators; e.g. shortcut operators (and, or) require
less cases than plain operators (xor)
™ Control mode of expression coverage works with one bit
arguments (vectors are reduced to bits using reduction or)
™ Vector mode deals with individual bits of vector arguments of
expressions

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Expression Coverage Report

™ Sample expression coverage report:

Expression Coverage report (version 1.0)

...
instance: UUT [ work.machine1(machine1) ] (EC : 2/3 - 66.67%
EC With Children : 2/3 - 66.67%)
process #ASSIGN#28_0

-----------------------------------------
C:\Riviera_Designs\COVERAGE_FSM\machine1.v (28)
(2/3 - 66.67%) expression: RESET1 || RESET2

<1> - RESET1
<2> - RESET2

cnt | <1> <2>

|| ---------------------
6 | 1 -
0 | 0 1
4 | 0 0

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Toggle Coverage

™ Toggle coverage describes design activity in terms of

changes in signal values (only regular high/low values are
counted)

™ Toggle coverage reports can identify a variety of issues in the

design and the testbench such as

• Identify signals which were not initialized

• Locate areas of the design which are not properly tested by the
testbench

• Measure power usage

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Toggle Coverage - Functions

™ Toggle Coverage creates a report
that informs:

• Whether monitored signals were

initialized
• Whether monitored signals experienced
rising and/or falling edges
• What’s the number of rising and falling
edges during the simulation session
• What’s the count of high and low pulses
on the selected signals

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Toggle Coverage-Modes
™ Full Mode
Signals are checked to detect if both rising and
falling edges occurred

™ Init Mode
Checks if selected signals were at least once set to
'0' or '1' value

™ Activity Mode
Provides information on how many rising and falling
edges happened on a signal while the signal was
monitored

™ Assign Mode
Provides information on how many pulses happened
on a signal while the signal was monitored

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Toggle Coverage - Summary

™ Pie Chart
Shows the percentage of signals
that toggled and did not toggle

™ Summary
Shows toggle coverage statistics

™ Parameters
Shows arguments for the toggle
command

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Functional Coverage

™ FC measures how well certain design features were exercised

™ At the abstract level, FC uses properties of the design described
either in plain English or in the specialized verification language
(e.g. PSL, SVA, OVA)
™ Properties specified in PSL or OVA can be injected into the
design code (if verification tool supports those languages)
™ Libraries of checkers (e.g. OVL) can be used with the design to
support functional coverage
™ Property checkers can be built manually (usually in the shape of
state machine)

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Functional Coverage

™ Functional coverage is the most selective of coverage

analysis flavors: you pick the properties you want to check
™ The desired result of Functional Coverage is ‘all properties
exercised’
™ 100% functional coverage means: ‘100% of properties you
have entered’, not ‘all functional aspects of the design’
™ Please refer to our OVL and Functional Coverage seminars
for more detailed info

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