Jawaban ini saya melihat dari milik Reyhan yang saya coba sendiri di EDA Playground .

5.1.2 SR latch dataflow

Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SR_latch is
Port(
r,s : in std_logic;
q,qbar : inout std_logic
);
end SR_latch;

architecture dataflow of SR_latch is

begin
q <= qbar nor r;
qbar <= q nor s;

end dataflow;

TestBench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SR_latch_tb is
end SR_latch_tb;

architecture dataflow of SR_latch_tb is

component SR_latch
Port(
r,s : in std_logic;
q,qbar : inout std_logic
);
end component;
signal s_val,r_val,q_out,qbar_out : std_logic := '0';
begin
wew : SR_latch port map(
r => r_val,
s => s_val,
q => q_out,
qbar => qbar_out
);
 process
begin
r_val <= '0';s_val <= '0';
wait for 10 ns;r_val <= '0';s_val <= '1';
wait for 10 ns;s_val <= '0';
wait for 10 ns;r_val <= '1';
wait for 10 ns;r_val <= '0';s_val <= '1';
wait for 10 ns;r_val <= '1';s_val <= '0';
wait for 10 ns;r_val <= '0';s_val <= '1';
wait for 10 ns;r_val <= '1';s_val <= '0';
-- wait for 10 ns;r_val <= '1';s_val <= '1';
wait for 20 ns;
end process;

end dataflow;
[2019-05-22 13:13:59 EDT] vlib work && vcom '-2008' '-o' design.vhd testbench.vhd &&
vsim -c -do "vsim testbench tugas3; vcd file dump.vcd; vcd add -r sim:/testbench/*vcd
add -r sim:/tugas3/*; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
Aldec, Inc. VHDL Compiler, build 2014.06.88
VLM Initialized with path: "/home/runner/library.cfg".
DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line
breakpoints and assertion debug will not be available."
COMP96 File: design.vhd
COMP96 Compile Entity "SR_latch"
COMP96 Compile Architecture "dataflow" of Entity "SR_latch"
COMP96 File: testbench.vhd
COMP96 Compile Entity "SR_latch_tb"
COMP96 Compile Architecture "dataflow" of Entity "SR_latch_tb"
COMP96 Top-level unit(s) detected:
COMP96 Entity => SR_latch_tb
COMP96 Compile success 0 Errors 0 Warnings Analysis time : 40.0 [ms]
# Aldec, Inc. Riviera-PRO version 2014.06.88.5387 built for Linux64 on June 25, 2014.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2014 Aldec, Inc. All rights reserved.
vsim testbench tugas3;
# VSIM: Error: Unknown library unit 'testbench' specified.
# VSIM: Error: Unknown library unit 'tugas3' specified.
# VSIM: Error: Simulation initialization failed.
Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd");
$dumpvars;'?
Done
5.2.1 D flip-flop behavioral

Program Utama

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_Flip_Flop is
Port(
 D,clk : in std_logic;
Q : out std_logic
);
end D_Flip_Flop;

architecture Behavioral of D_Flip_Flop is

begin
process (clk)
begin
if rising_edge (clk) then
Q <= D;
end if;
end process;
end Behavioral;

TestBench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_Flip_Flop_tb is
end D_Flip_Flop_tb;

architecture Behavioral of D_Flip_Flop_tb is

component d_flip_flop
Port(
D,clk : in std_logic;
Q : out std_logic
);
end component;
signal D_in,clk_in,Q_out : std_logic := '0';
begin
uvvuvwevve : d_flip_flop port map(
D => D_in,
clk => clk_in,
Q => Q_out
);
process
begin
wait for 10 ns;clk_in <= '1';d_in <= '0';
wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';d_in <= '1';
wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';
wait for 10 ns;clk_in <= '0';d_in <= '0';
wait for 10 ns;clk_in <= '1';
 wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';d_in <= '1';
wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';
wait for 10 ns;clk_in <= '0';d_in <= '0';
wait for 10 ns;clk_in <= '1';
wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';d_in <= '0';
wait for 10 ns;clk_in <= '0';
end process;
end Behavioral;

[2019-05-22 13:16:13 EDT] vlib work && vcom '-2008' '-o' design.vhd testbench.vhd &&
vsim -c -do "vsim testbench lab5; vcd file dump.vcd; vcd add -r sim:/testbench/*vcd
add -r sim:/lab5/*; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
Aldec, Inc. VHDL Compiler, build 2014.06.88
VLM Initialized with path: "/home/runner/library.cfg".
DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line
breakpoints and assertion debug will not be available."
COMP96 File: design.vhd
COMP96 Compile Entity "D_Flip_Flop"
COMP96 Compile Architecture "Behavioral" of Entity "D_Flip_Flop"
COMP96 File: testbench.vhd
COMP96 Compile Entity "D_Flip_Flop_tb"
COMP96 Compile Architecture "Behavioral" of Entity "D_Flip_Flop_tb"
COMP96 Top-level unit(s) detected:
COMP96 Entity => D_Flip_Flop_tb
COMP96 Compile success 0 Errors 0 Warnings Analysis time : 40.0 [ms]
# Aldec, Inc. Riviera-PRO version 2014.06.88.5387 built for Linux64 on June 25, 2014.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2014 Aldec, Inc. All rights reserved.
vsim testbench lab5;
# VSIM: Error: Unknown library unit 'testbench' specified.
# VSIM: Error: Unknown library unit 'lab5' specified.
# VSIM: Error: Simulation initialization failed.
Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd");
$dumpvars;'?
Done