P6 Notes

V Semester B.
Sc (CBCS) - Paper VI
MICROPROSSESOR & Electronic Instrumentation (EL-502T)
UNIT 1: Introduction to Microprocessor 9 hrs

Introduction, Applications, Basic block diagram, speed, word size, memory capacity,
classification of Microprocessors (mention different microprocessors being used)
Microprocessor 8085:Features, Architecture -Block diagram, Internal registers,
Register pairs, Flags, Stack pointer, Program counter, Types of Buses. Multiplexed
Address and Data bus, Generation of Control signals, Pin description of 8085.
8085 Instructions -Operation code, Operand & Mnemonics.
Instruction set of 8085-Instruction classification, Addressing modes, Instruction format.

Data transfer Instructions, Arithmetic instructions, Increment & Decrement
instructions, Logical instructions, Branch instructions and Machine control
instructions.
UNIT 2: Stack operations and Microprocessor Programming 9 hrs
Stack operations, Subroutine calls and return operations. Delay loops, use of counters,
Timing diagrams-Instruction cycle, Machine cycle, T- states, Time delay-Numerical
examples.
Programs for Data transfer and Memory operations (direct & indirect addressing),
Addition and Subtraction of two 8-bit & 16- bit numbers, Multiplication, Display of
smallest / largest number in a given array of numbers, Sorting of numbers in
descending / ascending order. Number of 1’s and 0’s in a given byte, Testing for zero
condition. 1’s and 2’s complements. Verification of truth tables of logic gates, Program
to add two n byte numbers, Program to generate Fibonacci series up to the limit,
program to find the factorial of a number, Program to find the GCD of two integer
numbers.
UNIT 3: I/O instructions and Interfacing 8 hrs
I/O instructions and, Interrupts in 8085.
Basic interfacing concepts, Compatible ICs of P 8085, Data transfer, Synchronous I/O
data transfer using interrupts.
Memory interfacing-Address decoding, Interfacing RAM and ROM.
Interfacings I/O devices—Input port, Output Port, IN & OUT instructions, Interfacing
input devices (interfacing matrix key board-block diagram), Interfacing output devices
(LED display interfacing-block diagram).
PPI IC 8255—Features, Pin diagram, Functional block diagram, Ports & their modes.
Introduction:
The word Microprocessor comes from the combination of micro and processor. Processor
means a device that processes whatever. In this context processor means a device that
processes numbers, specifically binary numbers, 0’s and 1’s. To process means to
manipulate. It is a general term that describes all manipulation. Again in this content, it
means to perform certain operations on the numbers that depend on the microprocessor’s
design.
In the late 1960’s, processors were built using discrete elements. These devices performed
the required operation, but were too large and too slow. In the early 1970’s the microchip was
invented. All of the components that made up the processor were now placed on a single
piece of silicon. The size became several thousand times smaller and the speed became
several hundred times faster. The “Micro” Processor was born.
Microprocessor based system:
Figure shows the block diagram of a microprocessor based system. It consists of Input,
Output, Memory and processor.
Definition of the Microprocessor: The microprocessor is a programmable device that takes

in numbers, performs on them arithmetic or logical operations according to the program
stored in memory and then produces other numbers as a result.
Programmable device: The microprocessor can perform different sets of operations on the
data it receives depending on the sequence of instructions supplied in the given program. By
changing the program, the microprocessor manipulates the data in different ways.
Instructions: Each microprocessor is designed to execute a specific group of operations.
This group of operations is called an instruction set. This instruction set defines what the
microprocessor can and cannot do.
Takes in: The data that the microprocessor manipulates must come from somewhere. It
comes from what is called “input devices”. These are devices that bring data into the system
from the outside world. These represent devices such as a keyboard, a mouse, switches, and
the like.
Numbers: The microprocessor has a very narrow view on life. It only understands binary
numbers.
A binary digit is called a bit (which comes from binary digit). The microprocessor recognizes
and processes a group of bits together. This group of bits is called a “word”. The number of
bits in a Microprocessor’s word, is a measure of its “abilities”. Words, Bytes, etc.
The earliest microprocessor (the Intel 8088 and Motorola’s 6800) recognized 8-bit words.
They processed information 8-bits at a time. That’s why they are called “8-bit processors”.
They can handle large numbers, but in order to process these numbers, they broke them into
8-bit pieces and processed each group of 8-bits separately. Later microprocessors (8086 and
68000) were designed with 16-bit words. A group of 8-bits were referred to as a “half-word”
or “byte”. A group of 4 bits is called a “nibble”. Also, 32 bit groups were given the name
“long word”.
Today, all processors manipulate at least 32 bits at a time and there exists microprocessors
that can process 64, 80, 128 bits.
Arithmetic and Logic Operations: Every microprocessor has arithmetic operations such as
add and subtract as part of its instruction set. Most microprocessors will have operations such
as multiply and divide. Some of the newer ones will have complex operations such as square
root. In addition, microprocessors have logic operations as well. Such as AND, OR, XOR,
shift left, shift right, etc. Again, the number and types of operations define the
microprocessor’s instruction set and depends on the specific microprocessor.
Stored in memory: First, what is memory? Memory is the location where information is
kept while not in current use. Memory is a collection of storage devices. Usually, each
storage device holds one bit. Also, in most kinds of memory, these storage devices are
grouped into groups of 8. These 8 storage locations can only be accessed together. So, one
can only read or write in terms of bytes to and from memory.
Memory is usually measured by the number of bytes it can hold. It is measured in Kilo, Mega
and lately Giga. A Kilo in computer language is 210 =1024. So, a KB (KiloByte) is 1024
bytes. Mega is 1024 Kilo and Giga is 1024 Mega.
Stored in memory: When a program is entered into a computer, it is stored in memory. Then
as the microprocessor starts to execute the instructions, it brings the instructions from
memory one at a time. Memory is also used to hold the data. The microprocessor reads
(brings in) the data from memory when it needs it and writes (stores) the results into memory
when it is done.
Produces: For the user to see the result of the execution of the program, the results must be
presented in a human readable form. The results must be presented on an output device.
This can be the monitor, a paper from the printer, a simple LED or many other forms.
Inside The Microprocessor: Internally, the microprocessor is made up of 3 main units. The
Arithmetic/Logic Unit (ALU), The Control Unit and an array of registers for holding data
while it is being manipulated.
Memory: Memory stores information such as instructions and data in binary format (0 and
1). It provides this information to the microprocessor whenever it is needed. Usually, there is
a memory “sub-system” in a microprocessor-based system.
This sub-system includes: The registers inside the microprocessor
 Read Only Memory (ROM) used to store information that does not change.
 Random Access Memory (RAM) (also known as Read/Write Memory) used to store
information supplied by the user. Such as programs and data.
Memory Map and Addresses: The memory map is a picture representation of the address
range and shows where the different memory chips are located within the address range.
To execute a program: the user enters its instructions in binary format into the memory. The
microprocessor then reads these instructions and whatever data is needed from memory,
executes the instructions and places the results either in memory or produces it on an output
device.
The three cycle instruction execution model
To execute a program, the microprocessor “reads” each instruction from memory,
“interprets” it, then “executes” it. The microprocessor fetches each instruction, decodes it,
Then executes it. This sequence is continued until all instructions are performed.
Machine Language
The number of bits that form the “word” of a microprocessor is fixed for that particular
processor. These bits define a maximum number of combinations. For example an 8-bit
microprocessor can have at most 28 = 256 different combinations. However, in most
microprocessors, not all of these combinations are used. Certain patterns are chosen and
assigned specific meanings. Each of these patterns forms an instruction for the
microprocessor. The complete set of patterns makes up the microprocessor’s machine
language.
The 8085 Machine Language
The 8085 (from Intel) is an 8-bit microprocessor. The 8085 uses a total of 246 bit patterns to
form its instruction set. These 246 patterns represent only 74 instructions. The reason for the
difference is that some (actually most) instructions have multiple different formats.
Because it is very difficult to enter the bit patterns correctly, they are usually entered in
hexadecimal instead of binary.
For example, the combination 0011 1100 which translates into “increment the number in the
register called the accumulator”, is usually entered as 3C.
Basic Concepts of Microprocessors
Microcomputer Microprocessor Microcontroller
A computer with a Silicon chip which includes Silicon chip which
microprocessor as its CPU, ALU, register circuits & includes microprocessor,
includes memory, I/O etc. control circuits memory & I/O in a single
package
Assembly Language: Entering the instructions using hexadecimal is quite easier than
entering the binary combinations. However, it still is difficult to understand what a program
written in hexadecimal does. So, each company defines a symbolic code for the instructions.
These codes are called “mnemonics”. The mnemonic for each instruction is usually a group
of letters that suggest the operation performed.
Using the previous example, 0011 1100 translates to 3C in hexadecimal (OPCODE). Its
mnemonic is: “INR A”. INR stands for “increment register” and A is short for accumulator.
Example: 1000 0000, Which translates to 80 in hexadecimal. Its mnemonic is “ADD B”.
“Add register B to the accumulator and keep the result in the accumulator”.
It is important to remember that a machine language and its associated assembly language are
completely machine dependent. In other words, they are not transferable from one
microprocessor to a different one.
For example, Motorola has an 8-bit microprocessor called the 6800.The 8085 machine
language is very different from that of the 6800. So is the assembly language. A program
written for the 8085 cannot be executed on the 6800 and vice versa.
“Assembling” the Program: How does assembly language get translated into machine
language? There are two ways: First one is “hand assembly”. The programmer translates
each assembly language instruction into its equivalent hexadecimal code (machine language).
Then the hexadecimal code is entered into memory.
In the other possibility is a program called an “assembler”, which does the translation
automatically.
8085 Microprocessor Architecture: 8085 is an 8-bit general purpose microprocessor
capable of addressing 65536 bytes (64 k) of memory, having 40 pins. It requires +5 v power
supply and can operate with 3 MHz clock. 8085 is upward compatible. Figure shows the pin
configuration of 8085A microprocessor.
Fig.1: Pin Diagram of 8085 Fig.2: Functional Diagram of 8085
8085 Microprocessor: Properties-Single + 5V Supply, 4 Vectored Interrupts (One is

Non Maskable), Serial In/Serial Out Ports, Decimal, Binary and Double Precision Arithmetic.
Direct Addressing Capability to 64K bytes of memory.
The Intel 8085A is a new generation, complete 8 bit parallel central processing unit (CPU).
The 8085A uses a multiplexed data bus. The address is split between the 8-bit address bus
and the 8bit data bus. Fig.1 shows the pin details of 8085 microprocessor.
Pin Description
The following describes the function of each pin:
A15 – A8 (Output tri State) Address Bus: The most significant 8 bits of the memory address
or the 8 bits of the I/0 address,3 stated during Hold and Halt modes.
AD0 –AD7 (Input /Output tri state) Multiplexed Address/Data Bus: Lower 8 bits of the
memory address (or I/0 address) appear on the bus during the first clock cycle of a machine
state. It then becomes the data bus during the second and third clock cycles. Tri stated during
Hold and Halt modes.
ALE (Output) Address Latch Enable: It occurs during the first clock cycle of a machine
state and enables the address to get latched into the on chip latch of peripherals. The falling
edge of ALE is set to guarantee setup and hold times for the address information. ALE can
also be used to strobe the status information. ALE is never 3stated.
SO, S1 (Output): Data Bus Status. Encoded status of the bus cycle: S1 can be used as an
advanced R/W status.
S1 S0 Machine Cycle
0 0 Halt
0 1 Write
1 0 Read
1 1 Fetch
RD (Output 3state): READ; indicates the selected memory or I/O device is to be read and
that the Data Bus is available for the data transfer.
WR (Output 3state): WRITE; indicates the data on the Data Bus is to be written into the
selected memory or I/O location. Data is set up at the trailing edge of WR.
READY (Input): If Ready is high during a read or write cycle, it indicates that the memory
or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to
go high before completing the read or write cycle.
HOLD (Input): HOLD; indicates that another Master is requesting the use of the Address
and Data Buses. The CPU, on receiving the Hold request, will relinquish the use of buses as
soon as the completion of the current machine cycle. Internal processing can continue. The
processor can regain the buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, and IO/M lines are Tri stated.
HLDA (Output): HOLD ACKNOWLEDGE- indicates that the CPU has received the Hold
request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the
Hold request is removed. The CPU takes the buses one half clock cycles after HLDA goes
low.
INTR (Input): INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled
only during the next to the last clock cycle of the instruction. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this
cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service
routine. The INTR is enabled and disabled by software. It is disabled by Reset and
immediately after an interrupt is accepted.
INTA (Output): INTERRUPT ACKNOWLEDGE; is used instead of (and has the same
timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to
activate the 8259 Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5
RESTART INTERRUPTS- These three inputs have the same timing as INTR except they
cause an internal RESTART to be automatically inserted.
RST 7.5 ~ ~ Highest Priority
RST 6.5
RST 5.5 Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a higher
priority than the INTR.
TRAP (Input): Trap interrupt is a non-maskable restart interrupt. It is recognized at the same
time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of
any interrupt.
RESET IN (Input): Reset sets the Program Counter to zero and resets the Interrupt Enable
and HLDA flip flops. None of the other flags or registers (except the instruction register) are
affected The CPU is held in the reset condition as long as Reset is applied.
RESET OUT (Output): Indicates CPlJ is being reset. Can be used as a system RESET. The
signal is synchronized to the processor clock.
X1, X2 (Input): Crystal or R/C network connections to set the internal clock generator X1
can also be an external clock input instead of a crystal. The input frequency is divided by 2 to
give the internal operating frequency.
CLK (Output): Clock Output for use as a system clock when a crystal or R/ C network is
used as an input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M (Output): IO/M indicates whether the Read/Write is to memory or l/O Tri stated
during Hold and Halt modes.
SID (Input): Serial input data line The data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.
SOD (output): Serial output data line. The output SOD is set or reset as specified by the SIM
instruction.
Vcc: +5 volt supply.
Vss : Ground Reference.
8085 Functional Description
The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt supply.
Its basic clock speed is 3 MHz thus improving on the present 8080's performance with higher
system speed. Also it is designed to fit into a minimum system of three IC's: The CPU, a
RAM/ IO, and a ROM or PROM/IO chip.
The 8085A uses a multiplexed Data Bus. The address is split between the higher 8-bit
Address Bus and the lower 8-bit Address/Data Bus. During the first cycle the address is sent
out. The lower 8-bits are latched into the peripherals by the Address Latch Enable (ALE).
During the rest of the machine cycle the Data Bus is used for memory or I/O data.
The 8085A provides RD, WR, and IO/Memory signals for bus control. An Interrupt
Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are
synchronized. The 8085A also provides serial input data (SID) and serial output data (SOD)
lines for simple serial interface.
In addition to these features, the 8085A has three maskable, restart interrupts and one non-
maskable trap interrupt.
Status Information
Status information is directly available from the 8085A. ALE serves as a status strobe. The
status is partially encoded, and provides the user with advanced timing of the type of bus
transfer being done. IO/M cycle status signal is provided directly also. Decoded S0 and S1
carries the following status information: HALT, WRITE, READ, FETCH as shown in the
table.1. S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of address
are multiplexed with the data instead of status. The ALE line is used as a strobe to enter the
lower half of the address into the memory or peripheral address latch. This also frees extra
pins for expanded interrupt capability.
Table.1: Machine cycles of 8085

Status Signals
Machine Cycle Signals IO/ M S1 S0 Control Signals
Op code Fetch 0 1 1 RD = 0
Memory Read 0 1 0 RD = 0
Memory Write 0 0 1 WR = 0
I/O Read 1 1 0 RD = 0
I/O Write 1 0 1 WR = 0
Interrupt Acknowledge 1 1 1 INTA = 0
Halt Z 0 0 RD = Z
Hold Z X X WR = Z
Reset Z X X INTA = 1
Interrupt and Serial I/O
The 8085A processor has Five interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP.
INTR is identical in function to the 8080 INT. Each of the three RESTART inputs 5.5, 6.5
and 7.5 has a programmable mask. TRAP is also a RESTART interrupt except it is non-
maskable. The three RESTART interrupts cause the internal execution of RST (saving the
program counter in the stack and branching to the RESTART address) if the interrupts are
enabled and if the interrupt mask is not set. The non-maskable TRAP causes the internal
execution of a RST independent of the state of the interrupt enable or masks.
The interrupts are arranged in a fixed priority that determines which interrupt is to be
recognized if more than one is pending as follows: TRAP highest priority, RST 7.5,
RST 6.5, RST 5.5, INTR lowest priority. This priority scheme does not take into account
the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt a
RST 7.5 routine if the interrupts were re-enabled before the end of the RST 7.5 routine. The
TRAP interrupt is useful for catastrophic errors such as power failure or bus error. The TRAP
input is recognized just as any other interrupt but has the highest priority. It is not affected by
any flag or mask. The TRAP input is both edge and level sensitive.
Basic System Timing
The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of
address on the Data Bus. During the I/O write and read cycle that the IO port address is
copied on both the upper and lower half of the address. Hold causes the CPU to relinquish the
bus when it is through with it by floating the Address and Data Buses.
System Interface
8085A family includes memory components, which are directly compatible to the 8085A
CPU. For example, a system consisting of the three chips, 8085A, 8156, and 8355 will have
the following features:
 2K Bytes ROM
 256 Bytes RAM
 1 Timer/Counter
 Four 8-bit I/O Ports
 One 6-bit I/O Port
 4 Interrupt Levels
 Serial In/Serial Out Ports
In addition to standard I/O, the memory mapped I/O offers an efficient l/O addressing
technique. With this technique, an area of memory address space is assigned for I/O address,
thereby, using the memory address for I/O manipulation. The 8085A CPU can also interface
with the standard memory that does not have the multiplexed address/data bus.
System Bus –wires connecting memory & I/O to microprocessor
Address Bus- Unidirectional-Identifying peripheral or memory location
Data Bus-Bidirectional-Transferring data
Control Bus-Synchronization signals-Timing signals and Control signals
Intel 8085 Microprocessor

Microprocessor consists of: Control unit: control microprocessor operations. ALU: performs
data processing function. Registers: provide storage internal to CPU. Interrupts, Internal
data bus.
ALU: In addition to the arithmetic & logic circuits, the ALU includes the accumulator, which
is part of every arithmetic & logic operation. Also, the ALU includes a temporary register
used for holding data temporarily during the execution of the operation. This temporary
register is not accessible by the programmer.
Registers General Purpose Registers: B, C, D, E, H & L are 8-bit general purpose registers
which can be used individually and accessed by the user. These registers can also be used as
16-bit register pairs as BC, DE and HL to hold 16-bit data. Registers H & L can be used as a
data pointer (holds memory address) for accessing data stored at memory location.
Fig.3: Architecture of Microprocessor 8085

Special Purpose Registers: Accumulator is an 8-bit register. It is the important register in
8085 as it is involved in all the arithmetic and logical operations carried out in the processor.
It is the destination register for all the operations. Stores 8-bit data during I/O transfer.
Fig.4: Register Array in 8085

Flag Register: It is an 8-bit register. Five bits of this register represents the status of the Flags
in the microprocessor before/after the execution of an instruction. The five status Flags used
in 8085 are S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity flag) & CY (carry
flag) respectively. In the figure 5, D5, D3 and D1 bits are not used in 8085.
Fig.5: Flag Register

Sign Flag (S): It is used for indicating the sign of the data in the accumulator, the sign flag is
set if negative (1 – negative) or else sign flag is reset if positive (0 –positive)
Zero Flag (Z): Is set if result obtained after an operation is 0. It is set following an increment
or decrement operation of that register.
10110011
+ 01001101
---------------
1 00000000
Carry Flag (CY): Is set if there is a carry or borrow from arithmetic operation
1011 0101 1011 0101

+ 0110 1100 -1100 1100
--------------- ---------------
Carry 1 0010 0001 Borrow 1 1110 1001
Auxillary Carry Flag (AC): This flag is set if there is a carry out of bit-3. Used in BCD
number operations.
Parity Flag (P): It is updated based on the number of one’s in a given byte of the data. If
even number of one’s then even parity else odd parity. Is set if parity is even (P=1) and is
cleared if parity is odd (P=0).
Program Counter (PC): This is a register that is used to control the sequencing of the
execution of instructions. This register always holds the address of the next instruction to be
fetched in the program. Since it holds an address, it is of 16-bit wide.
Stack Pointer (SP): The stack pointer is also a 16-bit register that is used to point into
memory. The memory this register points to is a special area called the stack. The stack is an
area of memory used to hold data that will be retrieved soon. The stack is usually accessed in
a Last In First out (LIFO) fashion.
Non Programmable Registers: Instruction Register (IR) & Decoder Instruction is stored in
IR after fetched by processor Decoder decodes instruction in IR.
Internal Clock generator: 8085 processor uses clock frequency of 3.125 MHz internally
and 6.25 MHz externally.
Address and Data Busses: The address bus has 8 signal lines A8 –A15which are
unidirectional. The other 8 address bits are multiplexed (time shared) with the 8 data bits. So,
the bits AD0 –AD7 are bi-directional and serve as A0 –A7 and D0 –D7at the same time. During
the execution of the instruction, these lines carry the address bits during the early part and
during the late parts of the execution they carry the 8-bit data. In order to separate the address
from the data, a latch is used to save the value of the data before the function of the bits
changes.
Demultiplexing AD7-AD0: From the above description, it becomes obvious that the AD7–AD0
lines are serving a dual purpose and that they need to be demultiplexed to get all the
information. The high order bits of the address remain on the bus for three clock periods.
However, the low order bits remain for only one clock period and they would be lost if they
are not saved externally. Also, notice that the low order bits of the address disappear when
they are needed most.
To make sure we have the entire address for the full three clock cycles, we will use an
external latch to save the value of AD7–AD0 when it is carrying the address bits. We use the
ALE signal to enable this latch.
Given that ALE operates as a pulse during T1, we will be able to latch the address. Then
when ALE goes low, the address is saved and the AD7–AD0 lines can be used for their purpose
as the bi-directional data lines. The high order address is placed on the address bus and hold
for 3 clock periods. The low order address is lost after the first clock period, this address
needs to be hold however we need to use latch. The address AD7 –AD0 is connected as inputs
to the latch 74LS373. The ALE signal is connected to the enable (G) pin of the latch and the
OC –Output control –of the latch is grounded.
8085 BUS Structure: There are three types of wire connections in the processor 8085 to
carry out various operations.
Address Bus: It is a 16-bit address lines A0-A15. This can have 0000H to FFFFH address
locations and can access 65536 bytes (64KB = 216) of memory. It is used to map I/O and uses
same instructions to accessing I/O devices and also memory.
Data Bus: It is an 8-bit data lines AD0-AD7. It is bi directional bus. The data bits are moved to
and from MPU to I/O and vice versa. The data range is from 00H to FFH (0 to 255)
Control Bus: It is usually a single bit line sending the generated control signals such as
read/write enable or flag bits from the processor to various peripherals. It is Unidirectional.
Address Bus: Consists of 16 address lines : A0 – A15. This can access 64KB ( = 216 =
65535) bytes of memory. Address locations is from 0000H to FFFFH. Use memory to map
I/O, same instructions used to access I/O devices and memory.
Data Bus: Consists of 8- data lines D0-D7. Operates in Bidirectional mode. The data bits are
sent from microprocessor unit to I/O and vice versa. Data ranges from 00H to FFH.
Control Bus: Consists of various lines carrying the control signals such as Read, Write,
Enable, Flag bits etc.
Bus Organisation in 8085
How Instruction is executed

All the instructions (of the program) are stored in memory. To run a program, the instructions
must be read from the memory in sequence and executed. This is achieved as:
a) PC is loaded with the 16-bit address of the instruction to be fetched.
b) CU generates the MEMR (memory read enable) control signal to access the memory.
c) The 8-bit Opcode of the instruction stored at the memory location is placed on the data
bus and is transferred to the IR (Instruction Decoder).
d) Instruction is then decoded and executed.
Addressing modes of 8085
The instructions MOV B,A or MVI C,65H are to copy data from a source into a destination.
In these instructions the source can be a register, an input port, or an 8-bit data. Similarly, a
destination can be a register or an output port. The sources and destination are operands. The
various formats for specifying operands are called the addressing modes. In 8085 processor
there are five types of addressing modes. They are:
1. Immediate Addressing mode
2. Register Addressing mode
3. Direct Addressing mode
4. Indirect Addressing mode
5. Implied or Implicit addressing mode.
In these modes following representations have a specific meaning.
Rs – Source Register Rd- Destination Register
R - General purpose register Rp- Register Pair
addr- 8-bit or 16-bit address Data – 8-bit or 16-bit data
M – Memory Register whose address is stored in HL register pair
1. Immediate Addressing mode: In this mode of addressing data is available in the

instruction itself. Byte 2 of the instruction represents 8-bit data. This data is loaded to
the destination register immediately after the execution of the instruction. It is an
example of two byte instruction. Example: MVI R, data MVI B, 86H
MVI L,00H etc.
2. Register Addressing: In this mode of addressing data is available in the Registers.
Data stored in Source register is loaded to the destination register after the execution
of the instruction. Source register contents are unaltered; however the destination
register contents are modified only. It is an example of one byte instruction. Example:
MOV Rd, Rs MOV B, C MOV L, E etc.
3. Direct Addressing: In this mode of addressing data is available in the memory
location or in Accumulator. It is used to load or accept the data from outside device to
accumulator. Byte 2 of the instruction represents 8-bit data. Byte-2 and byte-3 of the
instruction represents 16-bit data (address). Data stored in the specified location is
loaded to the accumulator after the execution of the instruction or Data stored in the
accumulator is stored to the specified location after the execution of the instruction. It
is an example of two byte or three byte instruction. Example: IN 00H OUT 01H
LDA 8050H STA 8070H LHLD 8100H etc.
4. Indirect Addressing: In this mode of addressing data is available in the memory
location. The effective address is calculated by the processor and the contents of the
address are used to form a second address. Data is available at the second address.
Byte-2 and byte-3 of the instruction represents 16-bit data (address). It is an example
of one byte or two byte or three byte instruction. Example: MOV M, B SUB M
LDAX B STAX D etc.
5. Implied or Implicit Addressing: In this mode of addressing one of the data is
available always in Accumulator (destination register). The contents of the other
register (source register) or 8-bit data in the instruction is operated on the contents of
accumulator and the result is stored in accumulator. Since only source is specified and
the destination (accumulator) is not mentioned (implied) for all arithmetic and logical
operations it is called Implied or implicit addressing mode. It is an example of one
byte or two byte instruction. Example: ADD C CMP L SBI B, 00H
RRC XCHG etc.
Timing Diagram of 8085: Representation of various control signals generated during

the execution of an instruction is the timing diagram representation. The Lower order
Address Bus, Higher order Address Bus, ALE signal, RD control, WR control and IO/M
control signals are shown with respect to the Internal Clock period. Various timing diagrams
are shown to know the sequence of actions (control signals generated) during the execution of
the instruction.
Timing Diagram of MOV A,B instruction
Timing Diagram of MVI A,45H instruction

Timing Diagram of LXI H, F045H instruction
Timing Diagram of MOV A,M instruction

Timing Diagram of MOV M,A instruction
Instruction Formats
An instruction is a command to the microprocessor to perform a given task on a specified
data. Each instruction has two parts: one is task to be performed, called operation code
(opcode), and the second is the data
One Byte Instructions: One byte instruction includes the opcode and operand in the same
byte. The operands are internal registers and are coded into the instruction. Example: MOV
Rd, Rs In this instruction Rd and Rs are two internal registers. Data which is available in Rs
register is loaded to Rd register. Only the Rd register content is modified.
Two byte Instructions:

Instruction set of 8085: An instruction is a binary pattern designed inside a
microprocessor to perform a specific function. The entire group of
instructions that a microprocessor supports is called Instruction Set. There
are 246 instructions in 8085 processor. Each instruction is represented by an
8-bit binary value. These 8-bits of binary value is called Op-Code or
Instruction Byte.
Classification of Instruction set: The 246 instructions of 8085 processor
are classified as
1. Data Transfer Instructions 2. Arithmetic Instructions
2. Logical Instructions 4. Branching Instructions
5. Control Instructions
Data Transfer Instructions

• These instructions move data between registers, or between memory and
registers.
• These instructions copy data from source to destination.
• While copying, the contents of source are not modified.
Op code Operand Description

MOV Rd, Rs Copy from source to destination.
M, Rs
Rd, M
This instruction copies the contents of the source register into the destination
register. The contents of the source register are not altered. If one of the
operands is a memory location, its location is specified by the contents of the
HL registers.
Example: MOV B, C or MOV B, M

MOV A,B MOV D,L
Before Execution of the Instruction Before Execution of the Instruction
A B D L
25 AB 4C 00
After Execution of the Instruction After Execution of the Instruction
A B D L
AB AB 00 00
MVI Rd, Data Move immediate 8-bit

M, Data
 The 8-bit data is stored in the destination register or memory.
 If the operand is a memory location, its location is specified by the
contents of the H-L registers.
 Example: MVI B, 57H or MVI M, 57H
LDA 16-bit address Load Accumulator

 The contents of a memory location, specified by a 16-bit address in the
operand, are copied to the accumulator.
 The contents of the source are not altered.
Example: LDA 2034H

LDAX B/D Register Pair Load accumulator indirect
 The contents of the designated register pair point to a memory location.
 This instruction copies the contents of that memory location into the
accumulator.
 The contents of either the register pair or the memory location are not
altered.
Example: LDAX B

LXI Reg. pair, 16-bit data Load register pair immediate
 This instruction loads 16-bit data in the register pair.
Example: LXI H, 2034 H
LHLD 16-bit address Load H-L registers direct

 This instruction copies the contents of memory location pointed out by
16-bit address into register L.
 It copies the contents of next memory location into register H.
Example: LHLD 2040 H
STA 16-bit address Store accumulator direct
 The contents of accumulator are copied into the memory location
specified by the operand.
Example: STA 2500 H
STAX Reg. pair Store accumulator indirect

 The contents of accumulator are copied into the memory location
specified by the contents of the register pair.
Example: STAX B
Opcode Operand Description
SHLD 16-bit address Store H-L registers direct
 The contents of register L are stored into memory location specified by
the 16-bit address.
 The contents of register H are stored into the next memory location.
Example: SHLD 2550 H

XCHG None Exchange H-L with D-E
 The contents of register H are exchanged with the contents of register D.

 The contents of register L are exchanged with the contents of register E.
Example: XCHG
SPHL None Copy H-L pair to the Stack Pointer (SP)
 This instruction loads the contents of H-L pair into SP.
Example: SPHL
XTHL None Exchange H–L with top of stack
 The contents of L register are exchanged with the location pointed out by
the contents of the SP.
 The contents of H register are exchanged with the next location (SP + 1).
Example: XTHL
PCHL None Load program counter with H-L contents
 The contents of registers H and L are copied into the program counter
(PC).
 The contents of H are placed as the high-order byte and the contents of L
as the low-order byte.
Example: PCHL
PUSH Reg. pair Push register pair onto stack
 The contents of register pair are copied onto stack.

 SP is decremented and the contents of high-order registers (B, D, H, A)
are copied into stack.
 SP is again decremented and the contents of low-order registers (C, E, L,
Flags) are copied into stack.
Example: PUSH B
POP Reg. pair Pop stack to register pair
 The contents of top of stack are copied into register pair.
 The contents of location pointed out by SP are copied to the low-order
register (C, E, L, Flags).
 SP is incremented and the contents of location are copied to the high-
order register (B, D, H, A).
Example: POP H
OUT 8-bit port address
Copy data from accumulator to a
port with 8-bit address
 The contents of accumulator are copied into the I/O port.
Example: OUT 78 H
IN 8-bit port address Copy data to accumulator from a
port with 8-bit address
 The contents of I/O port are copied into accumulator.
Example: IN 8C H
ARITHMETIC GROUP OF INSTRUCTIONS

These instructions perform the operations like:
 Addition, Subtraction, Increment and Decrement
ADDITION
• Any 8-bit number, or the contents of register, or the contents of memory
location can be added to the contents of accumulator.
• The result (sum) is stored in the accumulator.
• No two other 8-bit registers can be added directly.
Example: The contents of register B cannot be added directly to the
contents of register C.
SUBTRACTION
• Any 8-bit number, or the contents of register, or the contents of memory
location can be subtracted from the contents of accumulator.
• The result is stored in the accumulator.
• Subtraction is performed in 2’s complement form.
• If the result is negative, it is stored in 2’s complement form.
• No two other 8-bit registers can be subtracted directly.
INCREMENT / DECREMENT
• The 8-bit contents of a register or a memory location can be incremented
or decremented by 1.
• The 16-bit contents of a register pair can be incremented or decremented
by 1.
• Increment or decrement can be performed on any register or a memory
location.
ADD R Add register or memory to accumulator
M
 The contents of register or memory are added to the contents of
accumulator.
 The result is stored in accumulator.
 If the operand is memory location, its address is specified by H-L pair.
 All flags are modified to reflect the result of the addition.
Example: ADD B or ADD M
ADC R Add register or memory to accumulator
M with carry
 The contents of register or memory and Carry Flag (CY) are added to the
contents of accumulator.
Example: ADC B or ADC M
ADI 8-bit data Add immediate to accumulator
 The 8-bit data is added to the contents of accumulator.
 The result is stored in accumulator.
 All flags are modified to reflect the result of the addition.
Example: ADI 45 H
ACI 8-bit data Add immediate to accumulator with
carry
 The 8-bit data and the Carry Flag (CY) are added to the contents of
accumulator.
Example: ACI 45 H

DAD Reg. pair Add register pair to H-L pair
 The 16-bit contents of the register pair are added to the contents of H-L
pair.
 The result is stored in H-L pair.
 If the result is larger than 16 bits, then CY is set.
 No other flags are changed.
Example: DAD B
SUB R Subtract register or memory from
M accumulator
 The contents of the register or memory location are subtracted from the
contents of the accumulator.
 All flags are modified to reflect the result of subtraction.
Example: SUB B or SUB M
SBB R Subtract register or memory from
M accumulator with borrow
 The contents of the register or memory location and Borrow Flag (i.e.
CY) are subtracted from the contents of the accumulator.
Example: SBB B or SBB M
SUI 8-bit data Subtract immediate from accumulator
 The 8-bit data is subtracted from the contents of the accumulator.
Example: SUI 45 H

SBI 8-bit data Subtract immediate from accumulator
with borrow
 The 8-bit data and the Borrow Flag (i.e. CY) is subtracted from the
Example: SBI 45 H
INR R Increment register or memory by 1
M
 The contents of register or memory location are incremented by 1.

 The result is stored in the same place.
 If the operand is a memory location, its address is specified by the
contents of H-L pair.
Example: INR B or INR M
INX R Increment register pair by 1
 The contents of register pair are incremented by 1.
 The result is stored in the same place.
 Example: INX H
DCR R Decrement register or memory by 1
M
 The contents of register or memory location are decremented by 1.
 The result is stored in the same place.
Example: DCR B or DCR M
DCX R Decrement register pair by 1
 The contents of register pair are decremented by 1.
 The result is stored in the same place.
 Example: DCX H
Logical Instructions:
• These instructions perform logical operations on data stored in registers,
memory and status flags.
• The logical operations are:
– AND
– OR
– XOR
– Rotate
– Compare
– Complement
AND, OR, XOR:
• Any 8-bit data, or the contents of register, or memory location can
logically have
– AND operation
– OR operation
– XOR operation with the contents of accumulator.
• The result is stored in accumulator.
Rotate:
• Each bit in the accumulator can be shifted either left or right to the next
position.
Compare:
• Any 8-bit data, or the contents of register, or memory location can be
compares for:
– Equality
– Greater Than
– Less Than with the contents of accumulator.
• The result is reflected in status flags.
Complement:
• The contents of accumulator can be complemented.
• Each 0 is replaced by 1 and each 1 is replaced by 0.
CMP R Compare register or memory with accumulator
M
 The contents of the operand (register or memory) are compared with the
 Both contents are preserved .
 The result of the comparison is shown by setting the flags of the PSW as
follows:
 if (A) < (reg/mem): carry flag is set (CY=1)
 if (A) = (reg/mem): zero flag is set (Z=1)
 if (A) > (reg/mem): carry and zero flags are reset. (CY=Z=0)
Example: CMP B or CMP M
CPI 8-bit data Compare immediate with accumulator
 The 8-bit data is compared with the contents of accumulator.
 The values being compared remain unchanged.
 The result of the comparison is shown by setting the flags of the PSW as
follows:
 if (A) < data: carry flag is set (CY=1)
 if (A) = data: zero flag is set (Z=1)
 if (A) > data: carry and zero flags are reset (CY=Z-0)
Example: CPI 89H
ANA R Logical AND register or memory with
M accumulator
 The contents of the accumulator are logically ANDed with the contents of
register or memory.
 The result is placed in the accumulator.
 S, Z, P are modified to reflect the result of the operation.
 CY is reset and AC is set.
Example: ANA B or ANA M.
ANI 8-bit data Logical AND immediate with
accumulator
 The contents of the accumulator are logically ANDed with the 8-bit data.
 S, Z, P are modified to reflect the result.
 CY is reset, AC is set.
Example: ANI 86H.
XRA R Exclusive OR register or memory with
M accumulator
 The contents of the accumulator are XORed with the contents of the
register or memory.
 CY and AC are reset.
Example: XRA B or XRA M.
ORA R Logical OR register or memory
M with accumulator
 The contents of the accumulator are logically ORed with the contents of
the register or memory.
Example: ORA B or ORA M.
ORI 8-bit data Logical OR immediate with accumulator
 The contents of the accumulator are logically ORed with the 8-bit data.
Example: ORI 86H.
XRA R Logical XOR register or memory with
M accumulator
 The contents of the accumulator are XORed with the contents of the
register or memory.
Example: XRA B or XRA M.
XRI 8-bit data XOR immediate with accumulator
 The contents of the accumulator are XORed with the 8-bit data.
 The result is placed in the accumulator.
 S, Z, P are modified to reflect the result.
 CY and AC are reset.
Example: XRI 86H.
RLC None Rotate accumulator left
 Each binary bit of the accumulator is rotated left by one position.
 Bit D7 is placed in the position of D0 as well as in the Carry flag.
 CY is modified according to bit D7.
 S, Z, P, AC are not affected.
Example: RLC.
CY D7 D6 D5 D4 D3 D2 D1 D0
RRC None Rotate accumulator right

 Each binary bit of the accumulator is rotated right by one position.
 Bit D0 is placed in the position of D7 as well as in the Carry flag.
Example: RRC.
CY D7 D6 D5 D4 D3 D2 D1 D0

RAL None Rotate accumulator left through carry
 Each binary bit of the accumulator is rotated left by one position through
the Carry flag.
 Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least
significant position D0.
Example: RAL.
CY D7 D6 D5 D4 D3 D2 D1 D0

RAR None Rotate accumulator right through carry
 Each binary bit of the accumulator is rotated right by one position
through the Carry flag.
 Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most
significant position D7.
Example: RAR.
CY D7 D6 D5 D4 D3 D2 D1 D0

CMA None Complement accumulator
 The contents of the accumulator are complemented.
 No flags are affected.
Example: CMA.
CMC None Complement carry
 The Carry flag is complemented.
 No other flags are affected.
Example: CMC.
STC None Set carry
 The Carry flag is set to 1.
 No other flags are affected.
Example: STC.
Branching Instructions:
• The branching instruction alter the normal sequential flow.
• These instructions alter either unconditionally or conditionally.
JMP 16-bit Jump unconditionally
address
 The program sequence is transferred to the memory location specified by
the 16-bit address given in the operand.
Example: JMP 2034 H.
Jx 16-bit address Jump conditionally
the 16-bit address given in the operand based on the specified flag of the
PSW.
Example: JZ 2034 H.
Opcode Description Status Flags
JC Jump if Carry CY = 1
JNC Jump if No Carry CY = 0
JP Jump if Positive S=0
JM Jump if Minus S=1
JZ Jump if Zero Z=1
JNZ Jump if No Zero Z=0
JPE Jump if Parity Even P=1
JPO Jump if Parity Odd P=0

CALL 16-bit address Call unconditionally
the 16-bit address given in the operand.
 Before the transfer, the address of the next instruction after CALL (the
contents of the program counter) is pushed onto the stack.
Example: CALL 2034 H.
Cx 16-bit address Call conditionally
the 16-bit address given in the operand based on the specified flag of the
PSW.
 Before the transfer, the address of the next instruction after the call (the
contents of the program counter) is pushed onto the stack.
Example: CZ 2034 H.
CC Call if Carry CY = 1
CNC Call if No Carry CY = 0
CP Call if Positive S=0
CM Call if Minus S=1
CZ Call if Zero Z=1
CNZ Call if No Zero Z=0
CPE Call if Parity Even P=1
CPO Call if Parity Odd P=0

RET None Return unconditionally
 The program sequence is transferred from the subroutine to the calling
program.
 The two bytes from the top of the stack are copied into the program
counter, and program execution begins at the new address.
Example: RET.
Rx None Call conditionally
 The program sequence is transferred from the subroutine to the calling
program based on the specified flag of the PSW.
 The two bytes from the top of the stack are copied into the program
counter, and program execution begins at the new address.
Example: RZ.
RC Return if Carry CY = 1
RNC Return if No Carry CY = 0
RP Return if Positive S=0
RM Return if Minus S=1
RZ Return if Zero Z=1
RNZ Return if No Zero Z=0
RPE Return if Parity Even P=1
RPO Return if Parity Odd P=0

RST 0–7 Restart (Software Interrupts)
 The RST instruction jumps the control to one of eight memory locations
depending upon the number.
 These are used as software instructions in a program to transfer program
execution to one of the eight locations.
Example: RST 3.
Instructions Restart Address
RST 0 0000 H
RST 1 0008 H
RST 2 0010 H
RST 3 0018 H
RST 4 0020 H
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H
Control Instructions:
• The control instructions control the operation of microprocessor.
NOP None No operation
 No operation is performed.
 The instruction is fetched and decoded but no operation is executed.
Example: NOP
HLT None Halt

 The CPU finishes executing the current instruction and halts any further
execution.
 An interrupt or reset is necessary to exit from the halt state.
Example: HLT
DI None Disable interrupt
 The interrupt enable flip-flop is reset and all the interrupts except the
TRAP are disabled.
Example: DI
EI None Enable interrupt
 The interrupt enable flip-flop is set and all interrupts are enabled.
 This instruction is necessary to re-enable the interrupts (except TRAP).
Example: EI
RIM None Read Interrupt Mask
 This is a multipurpose instruction used to read the status of interrupts 7.5,
6.5, 5.5 and read serial data input bit.
 The instruction loads eight bits in the accumulator with the following
interpretations.
Example: RIM

SIM None Set Interrupt Mask
 This is a multipurpose instruction and used to implement the 8085
interrupts 7.5, 6.5, 5.5, and serial data output.
 The instruction interprets the accumulator contents as follows.
Example: SIM
Counters and Time Delays:

 A loop counter is set up by loading a register with a certain value
 Then using either DCR(decrement) or INR(increment) the contents of
the register are updated
 A loop is set up with a conditional jump instruction that loops back or not
depending on whether the count has reached the termination count.
Counter using register pair :
LXI B, 1000H
LOOP: DCX B
MOV A,C
ORA B
JNZ LOOP
Knowing the number of T states an instruction requires to execute, and the time
period of the clock signal Delay in the loop can be calculated as:
Delay = (Number of T states) X (Time period)
For example, MVI instruction needs 7T states. If the processor is running on
2MHz, then to execute MVI instruction processor needs 7x0.5microsecond =
3.5microsecond.
The following is an example of a delay loop:
MVI C, FF 7 T –States
Loop: DCR C 4 T-States
JNZ Loop 10 T-States
The first instruction initialises the loop counter and is executed only once
requiring only 7 T-States. The following two instructions form a loop that
requires 14 T-states to execute and is repeated 255 times until register C
becomes 0. In this program segment last iteration JNZ will fail an require only 7
T-states rather than 10 T-states. Hence, to find the total delay 3 T-states must be
deducted from the total delay to get an accurate delay calculation. Total delay is
given by the formula: Tdelay = TO +TL where, Tdelay – total delay, TO- delay
outside the loop and TL-delay of the loop.
TO= 7T-States is the delay of the MVI instruction
TL= (14T x 255)-3 = 3567 T-states
Similarly, delay loop can be set up using a register pair as loop counter.
LXI B,1000H 10 T-States
Loop: DCX B 6 T-States
MOV A,C 4 T-States
ORA B 4 T-States
JNZ Loop 10 T-States
TO = 10 T-States
TL = (24T x 4096)-3T=98301 T-States
Nested Loops: To increase the total delay nested loops can be setup in
assembly language by using two registers for the two loop counters and
updating the right register in the right loop. Figure shows the flowchart for the
nested loops.
For the given program segment the delay is :

TO1= 7T
TL1= (255 x 14)-3T = 3567 T and
TO2= 7T
TL2= (16 x (14+3574))-3T= 57405 T
Tdelay = 7+57405 = 57412T
T Total = 57412 x 0.5= 28.706 mS
The Stack
The stack is an area of memory identified by the programmer for
temporary storage of information.
The stack is a LIFO structure. Last In First Out. The stack normally
grows backwards into memory. In other words, the programmer defines the
bottom of the stack and the stack grows up into reducing address range.
Given that the stack grows backwards into memory, it is customary to place the
bottom of the stack at the end of memory to keep it as far away from user
programs as possible.
•In the 8085, the stack is defined by setting the SP (Stack Pointer) register.
LXI SP, FFFFH
This sets the Stack Pointer to location FFFFH (end of memory for the 8085).
Saving Information on the Stack

Information is saved on the stack by PUSHing it on. It is retrieved from
the stack by POPing it off. The 8085 provides two instructions: PUSH and POP
for storing information on the stack and retrieving it back. Both PUSH and POP
work with register pairs ONLY.
The PUSH Instruction

PUSH B - Decrement SP
Copy the contents of register B to the memory location pointed to by SP (SP-1)
Decrement SP (SP-2)
Copy the contents of register C to the memory location pointed to by SP (SP-2)
The POP Instruction

POP D - Copy the contents of the memory location pointed to by the SP to
register E
Increment SP (SP+1)
Copy the contents of the memory location pointed to by the SP (SP+1) to
register D
Increment SP (SP+2)
Operation of the Stack

During pushing, the stack operates in a “decrement then store” style. The stack
pointer is decremented first, then the information is placed on the stack.
During poping, the stack operates in a “use then increment” style. The
information is retrieved from the top of the stack and then the pointer is
incremented.
The SP pointer always points to “the top of the stack”.
The order of PUSHs and POPs must be opposite of each other in order to
retrieve information back into its original location.
PUSH B
PUSH D
...
POP D
POP B
The PSW Register Pair
The 8085 recognizes one additional register pair called the PSW
(Program Status Word).This register pair is made up of the Accumulator and the
Flags registers.
It is possible to push the PSW onto the stack, do whatever operations are
needed, then POP it off of the stack.The result is that the contents of the
Accumulator and the status of the Flags are returned to what they were before
the operations were executed.
Subroutines
Asubroutineisagroupofinstructionsthatwillbeusedrepeatedlyindifferentloc
ationsoftheprogram.Ratherthanrepeatthesameinstructionsseveraltimes,theycanbe
groupedintoasubroutinethatiscalledfromthedifferentlocations.
InAssemblylanguage,asubroutinecanexistanywhereinthecode.However,iti
scustomarytoplacesubroutinesseparatelyfromthemainprogram.
Subroutines
The 8085 has two instructions for dealing with subroutines.The CALL
instruction is used to redirect program execution to the subroutine.
The RTE insutruction is used to return the execution to the calling
routine.
The CALL Instruction

CALL 4000HPush the address of the instruction immediately following
the CALL onto the stack
Load the program counter with the 16-bit address supplied with the
CALL instruction.
The RTE Instruction

RTE
Retrieve the return address from the top of the stack
Load the program counter with the return address.
Cautions
The CALL instruction places the return address at the two memory
locations immediately before where the Stack Pointer is pointing.You must set
the SP correctly BEFORE using the CALL instruction.
The RTE instruction takes the contents of the two memory locations at
the top of the stack and uses these as the return address.Do not modify the stack
pointer in a subroutine. You will loose the return address.
Passing Data to a Subroutine

In Assembly Language data is passed to a subroutine through
registers.The data is stored in one of the registers by the calling program and the
subroutine uses the value from the register.
The other possibility is to use agreed upon memory locations.The calling

program stores the data in the memory location and the subroutine retrieves the
data from the location and uses it.
Call by Reference and Call by Value

If the subroutine performs operations on the contents of the registers, then
these modifications will be transferred back to the calling program upon
returning from a subroutine.Call by reference
If this is not desired, the subroutine should PUSH all the registers it needs
on the stack on entry and POP them on return.The original values are restored
before execution returns to the calling program.
Cautions with PUSH and POP

PUSH and POP should be used in opposite order.
There has to be as many POP’s as there are PUSH’s.If not, the RET
statement will pick up the wrong information from the top of the stack and the
program will fail.
It is not advisable to place PUSH or POP inside a loop.

Conditional CALL and RTE Instructions
The 8085 supports conditional CALL and conditional RTE
instructions.The same conditions used with conditional JUMP instructions can
be used.
CC, call subroutine if Carry flag is set.
CNC, call subroutine if Carry flag is not set
RC, return from subroutine if Carry flag is set
RNC, return from subroutine if Carry flag is not set
Etc.
A Proper Subroutine
According to Software Engineering practices, a proper subroutine:Is only
entered with a CALL and exited with an RTE
Has a single entry pointDo not use a CALL statement to jump into
different points of the same subroutine.
Has a single exit pointThere should be one return statement from any
subroutine.
Following these rules, there should not be any confusion with PUSH and
POP usage.
Interrupts
Interrupt is a process where an external device can get the attention of the
microprocessor.The process startsfrom the I/O device
The process is asynchronous.
Interrupts can be classified into two types:Maskable(can be delayed)

Non-Maskable(can not be delayed)
Interrupts can also be classified into:Vectored(the address of the service

routine is hard-wired)
Non-vectored(the address of the service routine needs to be supplied
externally)
An interrupt is considered to be an emergencysignal.The Microprocessor

should respond to it as soon as possible.
•When the Microprocessor receives an interrupt signal, it suspends the

currently executing program and jumps to an Interrupt Service Routine(ISR) to
respond to the incoming interrupt.Each interrupt will most probably have its
own ISR.
Responding to Interrupts
Responding to an interrupt may be immediateor delayeddepending on
whether the interrupt is maskable or non-maskable and whether interrupts are
being masked or not.
There are two ways of redirecting the execution to the ISR depending on
whether the interrupt is vectored or non-vectored.The vector is already knownto
the Microprocessor
The device will have to supplythe vector to the Microprocessor
The maskableinterrupt process in the 8085 is controlled by a single flip flop

inside the microprocessor. This Interrupt Enableflip flopis controlled using the
two instructions “EI” and “DI”.
•The 8085 has a single Non-Maskableinterrupt.The non-maskable
interrupt is notaffectedby the value of the Interrupt Enable flip flop.
The 8085 has 5 interrupt inputs.The INTR input.The INTR input is the
only non-vectoredinterrupt.
INTR is maskableusing the EI/DI instruction pair.
RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.RST 5.5, RST
6.5, and RST 7.5 are all maskable.
TRAP is the only non-maskableinterrupt in the 8085TRAP is also

automatically vectored
Interrupt Vectors and the Vector Table

An interrupt vectoris a pointer to where the ISR is stored in memory.
All interrupts (vectored or otherwise) are mapped onto a memory area
called the Interrupt Vector Table(IVT).The IVT is usually located in memory
page 00(0000H -00FFH).
The purpose of the IVT is to hold the vectors that redirect the
microprocessor to the right place when an interrupt arrives.
The IVT is divided into several blocks. Each block is used by one of the
interrupts to hold its “vector”
The 8085 Non-Vectored Interrupt Process:
1. The interrupt process should be enabledusing the EIinstruction.

2. The 8085 checks for an interrupt during the execution of everyinstruction.
3. If there is an interrupt, the microprocessor will complete the executing
instruction, and start a RESTARTsequence.
4. The RESTART sequence resets the interrupt flip flopand activates the
interrupt acknowledge signal(INTA).
5. Upon receiving the INTA signal, the interrupting deviceis expected to
return the op-codeof one of the 8 RST instructions.
1. When the microprocessor executes the RST instruction received from the
device, it saves the address of the next instructionon the stack and jumps to the
appropriate entry in the IVT.
2. The IVT entry must redirect the microprocessor to the actual service
routine.
3. The service routine must include the instruction EIto re-enable the
interrupt process.
4. At the end of the service routine, the RETinstruction returns the execution
to where the program was interrupted.
The 8085 recognizes 8 RESTART instructions: RST0 -RST7.each of

these would send the execution to a predetermined hard-wired memory location:
Restart Sequence
The restart sequence is made up of three machine cyclesIn the 1st
machine cycle:The microprocessor sends the INTA signal.
While INTA is active the microprocessor reads the data lines expecting to
receive, from the interrupting device, the opcode for the specific RST
instruction.
In the 2nd and 3rd machine cycles:the 16-bit address of the next
instruction is saved on the stack.
Then the microprocessor jumps to the address associated with the
specified RST instruction.
The location in the IVT associated with the RST instruction can not hold
the complete service routine.The routine is written somewhere else in memory.
Only a JUMP instruction to the ISR’s location is kept in the IVT block.
Hardware Generation of RST Opcode

How does the external device produce the opcode for the appropriate
RST instruction?The opcode is simply a collection of bits.
So, the device needs to set the bits of the data bus to the appropriate value
in response to an INTA signal.
Hardware Generation of RST The following is an example of generating RST 5:

RST 5’s opcode is EF =D D7654321011101111
During the interrupt acknowledge machine cycle, (the 1st machine cycle
of the RST operation):The Microprocessor activates the INTA signal.
This signal will enable the Tri-state buffers, which will place the value
EFH on the data bus.
Therefore, sending the Microprocessor the RST 5 instruction.
•The RST 5 instruction is exactly equivalent to CALL 0028H

Issues in Implementing INTR Interrupts
How long mustINTR remain high?The microprocessor checks the INTR
line one clock cycle before the last T-state of each instruction.
The interrupt process is Asynchronous.
The INTR must remain active long enough to allow for the longest
instruction.
The longest instruction for the 8085 is the conditional CALL instruction
which requires 18 T-states.
Therefore, the INTR must remain active for 17.5 T-states.

Issues in Implementing INTR Interrupts
How long canthe INTR remain high?The INTR line must be deactivated
before the EI is executed. Otherwise, the microprocessor will be interrupted
again.
The worst case situation is when EI is the first instruction in the ISR.
Once the microprocessor starts to respond to an INTR interrupt, INTA
becomes active (=0).
Therefore,INTR should be turned off as soon as the INTA signal is received.
Canthe microprocessor be interrupted again before the completion of the

ISR?As soon as the 1st interrupt arrives, all maskable interrupts are disabled.
They will only be enabled after the execution of the EI instruction.
Therefore, the answer is: “only if you allow it to”.

If the EI instruction is placed early in the ISR, other interrupt mayoccur before
the ISR is done.
Multiple Interrupts & Priorities
How do we allow multiple devices to interrupt using the INTR line?The
microprocessor can only respond to one signal on INTR at a time.
Therefore, we must allow the signal from only one of the devices to reach
the microprocessor.
We must assign some priority to the different devices and allow their
signals to reach the microprocessor according to the priority.
The Priority Encoder
The solution is to use a circuit called the priority encoder (74366).This
circuit has 8 inputs and 3 outputs.
The inputs are assigned increasing priorities according to the increasing
index of the input.Input 7 has highest priority and input 0 has the lowest.
The 3 outputs carry the index of the highest priority active input.
Figure 12.4 in the book shoes how this circuit can be used with a Tri-state
buffer to implement an interrupt priority scheme.The figure in the textbook does
not show the method for distributing the INTA signal back to the individual
devices.
Note that the opcodes for the different RST instructions follow a set
pattern.Bit D5, D4 and D3 of the opcodes change in a binary sequence from
RST 7 down to RST 0.
The other bits are always 1.
This allows the code generated by the 74366 to be used directly to choose
the appropriate RST instruction.
•The one draw back to this scheme is that the only way to change the
priority of the devices connected to the 74366 is to reconnect the hardware.
The 8085 Maskable/Vectored Interrupts
The 8085 has 4 Masked/Vectored interrupt inputs.RST 5.5, RST 6.5, RST
7.5They are all maskable.
They are automatically vectoredaccording to the following table:The
vectors for these interrupt fall in between the vectors for the RST instructions.
That’s why they have names like RST 5.5 (RST 5 and a half).
Masking RST 5.5, RST 6.5 and RST 7.5

These three interrupts are masked at two levels:Through the Interrupt
Enable flip flop and the EI/DI instructions.The Interrupt Enable flip flop
controls the whole maskable interrupt process.
Through individual mask flip flops that control the availability of the
individual interrupts.These flip flops control the interrupts individually.
The 8085 Maskable/Vectored Interrupt Process
1. The interrupt process should be enabledusing the EIinstruction.
2. The 8085 checks for an interrupt during the execution of everyinstruction.
3. If there is an interrupt, and if the interrupt is enabled using the interrupt
mask, the microprocessor will complete the executing instruction, and reset the
interrupt flip flop.
4. The microprocessor then executes a call instruction that sends the
execution to the appropriatelocation in the interrupt vector table.
When the microprocessor executes the call instruction, it saves the address of
the next instructionon the stack.
6.The microprocessor jumps to the specific service routine.
7.The service routine must include the instruction EIto re-enable the interrupt
process.
8.At the end of the service routine, the RETinstruction returns the execution to
where the program was interrupted.
The Interrupt Enable flip flop is manipulated using the EI/DI instructions.
•The individual masksfor RST 5.5, RST 6.5 and RST 7.5 are manipulated
using the SIMinstruction.This instruction takes the bit pattern in the
Accumulator and applies it to the interrupt mask enabling and disabling the
specific interrupts.
How SIM Interprets the Accumulator:
Bit 0 is the maskfor RST 5.5, bit 1 is the maskfor RST 6.5 and bit 2 is the
maskfor RST 7.5.If the mask bit is 0, the interrupt is available.
If the mask bit is 1, the interrupt is masked.
•Bit 3 (Mask Set Enable -MSE) is an enable for setting the mask.If it is
set to 0 the mask is ignoredand the old settings remain.
If it is set to 1, the new setting are applied.
The SIM instruction is used for multiple purposes and not only for setting
interrupt masks.It is also used to control functionality such as Serial Data
Transmission.
Therefore, bit 3 is necessary to tell the microprocessor whether or not
the interrupt masks should be modified
The RST 7.5 interrupt is the only8085 interrupt that has memory.If a
signal on RST7.5 arrives while it is masked, a flip flop will remember the
signal.
When RST7.5 is unmasked, the microprocessor will be interrupted even
if the device has removed the interrupt signal.
This flip flop will be automatically resetwhen the microprocessor
responds to an RST 7.5 interrupt.
•Bit 4 of the accumulator in the SIM instruction allows
explicitlyresettingthe RST 7.5 memory even if the microprocessor did not
respond to it.
The SIM instruction can also be used to perform serial data transmission
out of the 8085’s SOD pin.One bit at a time can be sent out serially over the
SOD pin.
•Bit 6 is used to tell the microprocessor whether or not to perform serial

data transmissionIf 0, then do not perform serial data transmission
If 1, then do.
•The value to be sent out on SOD has to be placed in bit 7 of the

accumulator.
•Bit 5 is not used by the SIM instruction
Using the SIM Instruction to Modify the Interrupt Masks
Example: Set the interrupt masks so that RST5.5 is enabled, RST6.5 is
masked, and RST7.5 is enabled.First, determine the contents of the accumulator
Triggering Levels
RST 7.5 is positive edge sensitive.When a positive edge appears on the
RST7.5 line, a logic 1 is storedin the flip-flop as a “pending” interrupt.
Since the value has been stored in the flip flop, the line does not have to
be highwhen the microprocessor checks for the interrupt to be recognized.
The line must go to zero and back to onebefore a new interrupt is
recognized.
RST 6.5 and RST 5.5 are level sensitive.The interrupting signal must
remain present until the microprocessor checks for interrupts.
Determining the Current Mask Settings

RIM instruction: Read Interrupt Mask Load the accumulatorwith an 8-bit
pattern showing the status of each interrupt pin and mask.
How RIM sets the Accumulator’s different bits:
The RIM Instruction and the Masks

Bits 0-2 show the current setting of the maskfor each of RST 7.5, RST
6.5 and RST 5.5They return the contents of the three mask flip flops.
They can be used by a program to read the mask settings in order to
modify only the right mask.
Bit 3 shows whether the maskable interrupt process is enabled or not.It

returns the contents of the Interrupt Enable Flip Flop.
It can be used by a program to determine whether or not interrupts are
enabled.
Bits 4-6 show whether or not there are pending interruptson RST 7.5,
RST 6.5, and RST 5.5Bits 4 and 5 return the current value of the RST5.5 and
RST6.5 pins.
Bit 6 returns the current value of the RST7.5 memory flip flop.
•Bit 7 is used for Serial Data Input.The RIM instruction reads the value of
the SID pinon the microprocessor and returns it in this bit.
Pending Interrupts
Since the 8085 has five interrupt lines, interrupts may occur during an
ISR and remain pending.Using the RIMinstruction, the programmer can read
the status of the interrupt lines and find if there are any pending interrupts.
The advantage is being able to find about interrupts on RST 7.5, RST 6.5,
and RST 5.5 without having to enable low level interrupts like INTR.
Using RIM and SIM to set IndividualMasks

Example: Set the mask to enable RST6.5 without modifying the masks
for RST5.5 and RST7.5.In order to do this correctly, we need to use the RIM
instruction to find the current settings of the RST5.5 and RST7.5 masks.
Then we can use the SIM instruction to set the masks using this
information.
Given that both RIM and SIM use the Accumulator, we can use some
logical operations to masks the un-needed values returned by RIM and turn
them into the values needed by SIM.
Assume the RST5.5 and RST7.5 are enabled and the interrupt process is
disabled.
TRAP
TRAP is the only non-maskableinterrupt.It does not need to be enabled
because it cannot be disabled.
It has the highest priorityamongst interrupts.

It is edge and level sensitive.It needs to be high and stay high to be
recognized.
Once it is recognized, it won’t be recognized again until it goes low, then
high again.
TRAP is usually used for power failure and emergency shutoff.

Internal Interrupt Priority
Internally, the 8085 implements an interrupt priority scheme.The
interrupts are ordered as follows:TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
However, TRAP has lower priority than the HLD signal used for DMA.
Memory and I/O Interfacing:
• Interface is a concept that refers to a point of interaction between
components, and is applicable at the level of both hardware and software.
• This allows a component, (such as a graphics card or an Internet
browser), to function independently while using interfaces to
communicate with other components via an input/output system and an
associated protocol.
• Address Bus
– Used to address memory & I/O devices
– 8085 has a 16-bit address bus
• Data Bus
– Used to transfer instructions and data
– 8085 has a 8-bit data bus
–
Higher Order Address Bus:
• The higher order address bus is a unidirectinal bus.
• It carries most significant 8-bits of a 16-bit address of memory or I/O
device.
• Address remains on lines as long operation is not completed.
Lower Order Address/Data Bus:
• This bus is bidirectional and works on time division multiplexing

between address and data.
• During first clock cycle, it serves as a least significant 8-bits of memory/
IO address.
• For second and third clock cycles it acts as data bus and carries data.
Demultiplexing Address/Data Lines:
• 8085 identifies a memory location with its 16 address lines, (AD0 to

AD7) & (A8 to A15)
• 8085 performs data transfer using its data lines, AD0 to AD7
• Lower order address bus & Data bus are multiplexed on same lines i.e.
AD0 to AD7.
• Demultiplexing refers to separating Address & Data signals for read/write
operations.
Generating Control Signals:
Memory interface:
• The memory is made up of semiconductor material used to store the
programs and data. The types of memory is,
– Primary or main memory

– Secondary memory
Primary Memory:
• RAM and ROM are examples of this type of memory.
• Microprocessor uses it in storing a program temporarily (commonly
called loading) and executing a program.
• Hence the speed of this type of memory should be fast.
Secondary Memory:
• These are used for bulk storage of data and information.
• The main examples include Floppy, Hard Disk, CD-ROM, Magnetic
Tape etc.
• Slower and Sequential Access Nature.
• non-volatile nature.
8085 interfacing with Memory chips:
Interface with two memory chips:
•
In case of multiple chips simple circuit like NOT gate will not work.
• In this case normally decoder circuits like 3-to-8 decoder circuit 74LS138
are used.
• These circuit are called address decoders.
Overall picture of memory interfacing:

Chip Selection
A15- A10 Circuit
8085
CS
A15-A8
ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip
WR RD IO/M D7- D0
RD WR
Types of address decoding:

• There are two types of address decoding techniques
– Exhaustive Decoding
– Partial Decoding
Exhaustive (Absolute) Decoding:
• In this type of scheme all the 16 bits of the 8085 address bus are used to
select a particular location in memory chip.
• Advantages:
– Complete Address Utilization
– Ease in Future Expansion
– No Bus Contention, as all addresses are unique.
• Disadvantages
– Increased hardware and cost.
– Speed is less due to increased delay.
Partial Decoding:
• In this scheme minimum number of address lines are used as required to
select a memory location in chip.
• Advantages:
– Simple, Cheap and Fast.
• Disadvantages:
– Unutilized space & fold back (multiple mapping).
– Bus Contention.
– Difficult future expansion.
Interfacing I/O Devices:
• Using I/O devices data can be transferred between the microprocessor
and the outside world.
• This can be done in groups of 8 bits using the entire data bus. This is
called parallel I/O.
• The other method is serial I/O where one bit is transferred at a time using
the SID and SOD pins on the Microprocessor.
Types of Parallel Interfacing:
• There are two ways to interface 8085 with I/O devices in parallel data
transfer mode:
– Memory Mapped IO
– IO Mapped IO (Peripheral mapped IO)
Memory Mapped IO:
• It considers them like any other memory location.
• They are assigned a 16-bit address within the address range of the
8085.
• The exchange of data with these devices follows the transfer of
data with memory.
• The user uses the same instructions used for memory.
IO Mapped IO:
• It treats them separately from memory.
– I/O devices are assigned a “port number” within the 8-bit address
range of 00H to FFH.
– The user in this case would access these devices using the IN and
OUT instructions only.
Comparison between IO mapped IO V/s Memory Mapped IO
Characteristics Memory mapped I/O Peripheral Mapped I/O
1. Device Address 16 bit 8 bit
2. Control signals for MEMR/MEMW IOR/IOW
I/O
3. Instructions Memory related instructions IN and OUT
available like STA, LDA, LDAX, ADD
M, ANA M etc
4. Data Transfer Between any register and I/O Only between I/O and
Accumulator
5. Maximum I/O Memory map (216=64k) is I/O map is independent
available shared between I/O and of mem. map, 28=256
system memory input and 256 outputs
can be connected
6. Execution speed 13T states (STA, LDA), 10T states
7T (MOV M,R)
7. Hardware required More hardware required to Less to decode 8 bit
decode 16 bit address address
8. Others Arithmetic and Logical Not available
operations can be directly
performed with I/O data
The interfacing of output devices:

• Output devices are usually slow.
• Also, the output is usually expected to continue appearing on the
output device for a long period of time.
• Given that the data will only be present on the data lines for a very
short period (microseconds), it has to be latched externally.
• To do this the external latch should be enabled when the port’s
address is present on the address bus, the IO/M signal is set high
and WR is set low.
• The resulting signal would be active when the output device is
being accessed by the microprocessor.
• Decoding the address bus (for memory-mapped devices)
follows the same techniques discussed in interfacing memory.
Interfacing of Input Devices:

• The basic concepts are similar to interfacing of output devices.
• The address lines are decoded to generate a signal that is active when the
particular port is being accessed.
• An IORD signal is generated by combining the IO/M and the RD signals
from the microprocessor.
• A tri-state buffer is used to connect the input device to the data bus.
• The control (Enable) for these buffers is connected to the result of
combining the address signal and the signal IORD.
Key board and Display Interface:
USART (Universal Synchronous Asynchronous Receiver Transmitter) : 8251A
Programmable Communication Interface:
 8251A is a USART (Universal Synchronous Asynchronous Receiver
Transmitter) for serial data communication.
 Programmable peripheral designed for synchronous /asynchronous serial
data communication, packaged in a 28-pin DIP.
 Receives parallel data from the CPU & transmits serial data after
conversion.
 Also receives serial data from the outside & transmits parallel data to the
CPU after conversion.
Pin configuration of 8251:
Block Diagram of 8251:

Figure shows the various stages of 8251 as
 Data Bus buffer

 Read/Write Control Logic
 Modem Control
 Transmitter
 Receiver
1. Data Bus Buffer:
 D0-D7 : 8-bit data bus used to read or write status, command word or
data from or to the 8251A
2. Read/Write Control logic:
• Includes a control logic, six input signals & three buffer registers: Data
register, control register & status register.
• Control logic : Interfaces the chip with MPU, determines the functions of
the chip according to the control word in the control register & monitors
the data flow.
Input signals:
 CS – Chip Select : When signal goes low, the 8251A is selected by the
MPU for communication.
 C/D – Control/Data : When signal is high, the control or status register is
addressed; when it is low, data buffer is addressed. (Control register &
status register are differentiated by WR and RD signals)
 WR : When signal is low, the MPU either writes in the control register or
sends output to the data buffer.
 RD : When signal goes low, the MPU either reads a status from the status
register or accepts data from data buffer.
 RESET : A high on this signal reset 8252A & forces it into the idle mode.
 CLK : Clock input, usually connected to the system clock for
communication with the microprocessor.
Control Register:
 16-bit register for a control word consist of two independent bytes
namely mode word & command word.
 Mode word : Specifies the general characteristics of operation such as
baud, parity, number of bits etc.
 Command word : Enables the data transmission and reception.
 Register can be accessed as an output port when the Control/Data pin is
high.
Status Register:
• Checks the ready status of the peripheral.
• Status word in the status register provides the information concerning
register status and transmission errors.
Data Register:
 Used as an input and output port when the C/D is low
CS C/D WR RD Operation
0 0 1 0 MPU reads data from data buffer

0 0 0 1 MPU writes data from data buffer
0 1 0 1 MPU writes a word to control register
0 1 1 0 MPU reads a word from status register
1 × × × Chip is not selected for any operation
3. Modem Control:
 DSR - Data Set Ready : Checks if the Data Set is ready when
communicating with a modem.
 DTR - Data Terminal Ready : Indicates that the device is ready to accept
data when the 8251 is communicating with a modem.
 CTS - Clear to Send : If its low, the 8251A is enabled to transmit the
serial data provided the enable bit in the command byte is set to ‘1’.
 RTS - Request to Send Data : Low signal indicates the modem that the
receiver is ready to receive a data byte from the modem.
4. Transmitter Section:
 Accepts parallel data from MPU & converts them into serial data.
 Has two registers:
– Buffer register : To hold eight bits
– Output register : To convert eight bits into a stream of serial bits.
 The MPU writes a byte in the buffer register.

 Whenever the output register is empty; the contents of buffer register are
transferred to output register.
 Transmitter section consists of three output & one input signals
 TxD - Transmitted Data Output : Output signal to transmit the
data to peripherals
 TxC - Transmitter Clock Input : Input signal, controls the rate of
transmission.
 TxRDY - Transmitter Ready : Output signal, indicates the buffer
register is empty and the USART is ready to accept the next data
byte.
 TxE - Transmitter Empty : Output signal to indicate the output
register is empty and the USART is ready to accept the next data
byte.
5. Receiver Section:
Accepts serial data on the RxD pin and converts them to parallel data.
Has two registers :
a. Receiver input register
b. Buffer register
 When RxD goes low, the control logic assumes it is a start bit, waits for
half bit time, and samples the line again. If the line is still low, the input
register accepts the following data, and loads it into buffer register at the
rate determined by the receiver clock.
 RxRDY - Receiver Ready Output: Output signal, goes high when the
USART has a character in the buffer register & is ready to transfer it to
the MPU.
 RxD - Receive Data Input : Bits are received serially on this line &
converted into a parallel byte in the receiver input register.
 RxC - Receiver Clock Input : Clock signal that controls the rate at
which bits are received by the USART.
PROGRAMMABLE PERIPHERAL INTERFACE - 8255

Features:
• It is a programmable device.
• It has 24 I/O programmable pins like PA,PB,PC (3-8 pins).
 T T L compatible.
 Improved dc driving capability
Pin diagram:
• Data bus(D0-D7):These are 8-bit bi-directional buses, connected to 8085

data bus for transferring data.
• CS: This is Active Low signal. When it is low, then data is transfer from
8085.
• Read: This is Active Low signal, when it is Low read operation will be
start.
• Write: This is Active Low signal, when it is Low Write operation will be
start.
• Address (A0-A1):This is used to select the ports. like this
A1 A0 Select
0 0 PA
0 1 PB
1 0 PC
1 1 Control reg.
• RESET: This is used to reset the device. That means clear control
registers.
• PA0-PA7:It is the 8-bit bi-directional I/O pins used to send the data to
peripheral or to receive the data from peripheral.
• PB0-PB7:Similar to PA
• PC0-PC7:This is also 8-bit bidirectional I/O pins. These lines are divided
into two groups.
1. PC0 to PC3(Lower Groups)
2. PC4 to PC7 (Higher groups)
These two groups working in separately using 4 data’s.
Block Diagram of 8255:
Data Bus Buffer:

• It is a 8-bit bidirectional Data bus.
• Used to interface between 8255 data bus with system bus.
• The internal data bus and Outer pins D0-D7 pins are connected in
internally.
• The direction of data buffer is decided by Read/Control Logic.
Read/Write Control Logic:
• This is getting the input signals from control bus and Address bus
• Control signal are RD and WR.
• Address signals are A0,A1,and CS.
• 8255 operation is enabled or disabled by CS.
Group A and Group B control:
• Group A and B get the Control
Signal from CPU and send the command to the individual control blocks.
• Group A send the control signal to port A and Port C (Upper) PC7-PC4.
• Group B send the control signal to port B and Port C (Lower) PC3-PC0.
• PORT A:
• This is a 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1, mode 2 .
PORT B:
• This is a 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode 1.
• PORT C:
• This is a 8-bit Unlatched buffer Input and an Output latch.
• It is splitted into two parts.
It can be programmed by bit set/reset operation
Operation modes:
BIT SET/RESET MODE:
• The PORT C can be Set or Reset by sending OUT instruction to the
CONTROL registers.
I/O MODES:
MODE 0(Simple input / Output):
• In this mode , port A, port B and port C is used as individually (Simply).
• Features:
• Outputs are latched , Inputs are buffered not latched.
• Ports do not have Handshake or interrupt capability.
MODE 1 :(Input/output with Hand shake)
• In this mode, input or output is transferred by hand shaking Signals.
• Handshaking signals is used to transfer data between whose data transfer
is not same.
Example:
• The computer send the data to the printer large speed compared to the
printer.
• When computer send the data according to the printer speed at the time
only, printer can accept.
• If printer is not ready to accept the data then after sending the data bus ,
computer uses another handshaking signal to tell printer that valid data is
available on the data bus.
• Each port uses three lines from port C as handshake signals
MODE 2: Bi-directional I/O data transfer:

• This mode allows bidirectional data transfer over a single 8-bit data bus
using handshake signals.
• This feature is possible only Group A
• Port A is working as 8-biy bidirectional.
• PC3-PC7 is used for handshaking purpose.
• The data is sent by CPU through this port , when the peripheral request it.
CONTROL WORD FORMATS:
• In the INPUT mode , When RESET is High all 24 pins (3-ports) be a
input mode.
• i.e all flip flops are cleared and the interrupts are rest.
• This condition is maintained even after RESET goes low.
• This can be avoid by writing single control word to the control registers ,
when required.
FOR BIT SET/RESET MODE:
• This is bit set/reset control word format.
• PC0-PC7 is set or reset as per the status of D0.
• A BSR word is written for each bit
• Example:
• PC3 is Set then control register will be 0XXX0111.
• PC4 is Reset then control register will be 0XXX01000.
• X is a don’t care.
X X X
Don’t Care
• The control word for both mode is same.

• Bit D7 is used for specifying whether word loaded in to Bit set/reset
mode or Mode definition word.
• D7=1=Mode definition mode.
• D7=0=Bit set/Reset mode.
DATA TRANSFER INSTRUCTIONS

Copy from source to destination
MOV Rd, Rs This instruction copies the contents of
M, Rs the source register into the
Rd, M destination register; the contents of
the source register are not altered. If
one of the operands is a memory
Example: MOV B, C or location, its location is specified by
MOV B, M the contents of the HL registers.
Move immediate 8-bit
MVI Rd, data The 8-bit data is stored in the
M, data destination register or memory. If the
operand is a memory location, its
Example: MVI B, 57 or location is specified by the contents of
MVI M, 57 the HL registers.
Load accumulator
LDA 16-bit address The contents of a memory location,

specified by a 16-bit address in the
operand, are copied to the
Example: LDA 2034 or accumulator.
LDA XYZ The contents of the source are not
altered.
Load accumulator indirect
LDAX B/D Reg. pair The contents of the designated
register pair point to a memory
location. This instruction copies the
contents of that memory location into
Example: LDAX B the accumulator. The contents of
either the register pair or the memory
location are not altered.
Load register pair immediate
LXI Reg. pair, 16-bit data The instruction loads 16-bit data in
Example: LXI H, 2034 the register pair designated in the
operand.
Load H and L registers direct
LHLD 16-bit address The instruction copies the contents of
the memory location pointed out by
the 16-bit address into register L and
Example: LHLD 2040 copies the contents of the next
memory location into register H. The
contents of source memory locations
are not altered.
Store accumulator direct
STA 16-bit address The contents of the accumulator are

copied into the memory location
specified by the operand. This is a 3-
Example: STA 4350 or byte instruction, the second byte
STA XYZ specifies the low-order address and
the third byte specifies the high-order
address.
Store accumulator indirect

STAX Reg. pair The contents of the accumulator are
copied into the memory location
specified by the contents of the
Example: STAX B operand (register
pair). The contents of the accumulator
are not altered.
Store H and L registers direct
SHLD 16-bit address The contents of register L are stored
into the memory location specified by
the 16-bit address in the operand and
the contents of H register are stored
into the next memory location by
incrementing the operand. The
Example: SHLD 2470 contents of registers HL are
not altered. This is a 3-byte
instruction, the second byte specifies
the low-order address and the third
byte specifies the
high-order address.
Exchange H and L with D and E
XCHG None The contents of register H are
exchanged with the contents of
Example: XCHG register D, and the contents of
register L are exchanged with
the contents of register E.
Copy H and L registers to the stack pointer
SPHL None The instruction loads the contents of
the H and L registers into the stack
pointer register, the contents of the H
register
provide the high-order address and
Example: SPHL the contents of the L register provide
the low-order address. The contents
of the H
and L registers are not altered.
Exchange H and L with top of stack
XTHL None The contents of the L register are

exchanged with the stack location
pointed out by the contents of the
stack pointer
register. The contents of the H
Example: XTHL register are exchanged with the next
stack location (SP+1); however, the
contents of the stack pointer register
are not altered.
Push register pair onto stack
PUSH Reg. pair The contents of the register pair
designated in the operand are copied
onto the stack in the following
sequence. The stack pointer register
is decremented and the contents of
the high order register (B, D, H, A) are
Example: PUSH B or copied into that location. The
PUSH A stack pointer register is decremented
again and the contents of the low-
order register (C, E, L, flags) are
copied to that
location.
Pop off stack to register pair
POP Reg. pair The contents of the memory location
pointed out by the stack pointer
register are copied to the low-order
register (C, E, L, status flags) of the
operand. The stack pointer is
incremented by 1 and the contents of
that memory location are copied to
Example: POP H or the high-order register (B, D, H, A) of
POP A the operand. The stack pointer
register is again incremented by 1.
Output data from accumulator to a port with 8-bit address
OUT 8-bit port address The contents of the accumulator are
copied into the I/O port specified by
Example: OUT 87 the operand.
Input data to accumulator from a port with 8-bit address
IN 8-bit port address The contents of the input port

designated in the operand are read
Example: IN 82 and loaded into the accumulator.
ARITHMETIC INSTRUCTIONS
Add register or memory to accumulator
ADD R The contents of the operand (register
or memory) are M added to the
contents of the accumulator and the
result is stored in the accumulator. If
Example: ADD B or the operand is a memory location, its
ADD M location is specified by the contents of
the HL registers. All flags are modified
to reflect the result of the addition.
Add register to accumulator with carry
ADC R The contents of the operand (register
or memory) and M the Carry flag are
added to the contents of the
accumulator and the result is stored in
the accumulator. If the operand is a
Example: ADC B or memory location, its location is
ADC M specified by the contents of
to reflect the result of the addition
Add immediate to accumulator

ADI 8-bit data The 8-bit data (operand) is added to
the contents of the accumulator and
the result is stored in the accumulator.
Example: ADI 45 All flags are modified to reflect the
result of the addition.
Add immediate to accumulator with carry

ACI 8-bit data The 8-bit data (operand) and the
Carry flag are added to the contents
of the accumulator and the result is
Example: ACI 45 stored in the accumulator. All flags
are modified to reflect the result of the
addition.
Add register pair to H and L registers
DAD Reg. pair The 16-bit contents of the specified
register pair are added to the contents
of the HL register and the sum is
stored in the HL register. The
Example: DAD H contents of the source register pair
are not altered. If the result is larger
than 16 bits, the CY flag is set. No
other flags are affected.
Subtract register or memory from accumulator
SUB R The contents of the operand (register
or memory ) are M subtracted from
the contents of the accumulator, and
the result is stored in the accumulator.
If the operand is a memory location,
Example: SUB B or its location is specified by the
SUB M contents of
to reflect the result of the subtraction.
Subtract source and borrow from accumulator
SBB R The contents of the operand (register
or memory ) and M the Borrow flag
are subtracted from the contents of
the
accumulator and the result is placed
in the accumulator. If the operand is a
Example: SBB B or memory location, its location is
SBB M specified by the contents of the HL
registers. All flags are modified to
reflect the result of the subtraction.
Subtract immediate from accumulator
SUI 8-bit data The 8-bit data (operand) is subtracted
from the contents of the accumulator
and the result is stored in the
Example: SUI 45 accumulator. All flags are modified to
reflect the result of the subtraction.
Subtract immediate from accumulator with borrow

SBI 8-bit data The 8-bit data (operand) and the
Borrow flag are subtracted from the
contents of the accumulator and the
Example: SBI 45 result is stored
in the accumulator. All flags are
modified to reflect the result of the
subtracion.
Increment register or memory by 1
INR R The contents of the designated
register or memory) are M
incremented by 1 and the result is
stored in the same place. If
Example: INR B or INR the operand is a memory location, its
M location is specified by the contents of
the HL registers.
Increment register pair by 1
INX R The contents of the designated
register pair are incremented by 1 and
Example: INX H the result is stored in the same place.
Decrement register or memory by 1
DCR R The contents of the designated
register or memory are M
decremented by 1 and the result is
stored in the same place. If
Example: DCR B or the operand is a memory location, its
DCR M location is specified by the contents of
the HL registers.
Decrement register pair by 1
DCX R The contents of the designated

register pair are decremented by 1
Example: DCX H and the result is stored in the same
place.
Decimal adjust accumulator
DAA none The contents of the accumulator are
changed from a binary value to two 4-
bit binary coded decimal (BCD) digits.
This is the only instruction that uses
the auxiliary flag to perform the binary
to BCD conversion, and the
conversion procedure is described
below. S, Z, AC, P, CY flags are
altered to reflect the results of the
operation.
If the value of the low-order 4-bits in
the accumulator is greater than 9 or if
Example: DAA AC flag is set, the instruction adds 6
to the
low-order four bits.
If the value of the high-order 4-bits in
the accumulator is greater than 9 or if
the Carry flag is set, the instruction
adds 6
to the high-order four bits.
LOGICAL INSTRUCTIONS
Compare register or memory with accumulator
CMP R The contents of the operand (register
or memory) are M compared with the
contents of the accumulator. Both
contents are preserved . The result of
the comparison is shown by setting
the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is
Example: CMP B or set,CY=1
CMP M if (A) = (reg/mem): zero flag is set,
Z=1
if (A) > (reg/mem): carry and zero
flags are reset, CY=Z=0
Compare immediate with accumulator
CPI 8-bit data The second byte (8-bit data) is
compared with the contents of the
accumulator. The values being
compared remain unchanged. The
result of the comparison is shown by
setting
the flags of the PSW as follows:
if (A) < data: carry flag is set, CY=1
Example: CPI 89 if (A) = data: zero flag is set, Z=1
if (A) > data: carry and zero flags are
reset, CY=Z=0
Logical AND register or memory with accumulator
ANA R The contents of the accumulator are
logically ANDed with M the contents
of the operand (register or memory),
and the result is placed in the
accumulator. If the operand is a
memory location, its address is
Example: ANA B or specified by the contents of
ANA M HL registers. S, Z, P are modified to
reflect the result of the operation. CY
is reset. AC is set.
Logical AND immediate with accumulator
ANI 8-bit data The contents of the accumulator are
logically ANDed with the 8-bit data
(operand) and the result is placed in
the
Example: ANI 86 accumulator. S, Z, P are modified to
is reset. AC is set.
Exclusive OR register or memory with accumulator

XRA R The contents of the accumulator are
Exclusive ORed with M the contents
of the operand (register or memory),
and the result is placed in the
accumulator. If the operand is a
memory location, its address is
Example: XRA B or specified by the contents of
XRA M HL registers. S, Z, P are modified to
and AC are reset.
Exclusive OR immediate with accumulator
XRI 8-bit data The contents of the accumulator are
Exclusive ORed with the 8-bit data
the
Example: XRI 86 accumulator. S, Z, P are modified to
and AC are reset.
Logical OR register or memory with accumulator
ORA R The contents of the accumulator are
logically ORed with M the contents of
the operand (register or memory), and
the
result is placed in the accumulator. If
the operand is a memory location, its
Example: ORA B or address is specified by the contents
ORA M of
HL registers. S, Z, P are modified to
and AC are reset.
Logical OR immediate with accumulator
ORI 8-bit data The contents of the accumulator are
logically ORed with the 8-bit data
the
Example: ORI 86 accumulator. S, Z, P are modified to
and AC are reset.
Rotate accumulator left
RLC None Each binary bit of the accumulator is
rotated left by one position. Bit D7 is
placed in the position of D0 as well as
Example: RLC in
the Carry flag. CY is modified
according to bit D7. S, Z, P, AC are
not affected.
CY D7 D6 D5 D4 D3 D2 D1 D0
Rotate accumulator right

RRC None Each binary bit of the accumulator is
rotated right by one position. Bit D0 is
placed in the position of D7 as well as
in
Example: RRC the Carry flag. CY is modified
according to bit D0. S, Z, P, AC are
not affected.
CY D7 D6 D5 D4 D3 D2 D1 D0
Rotate accumulator left through carry

RAL None Each binary bit of the accumulator is
rotated left by one position through
the Carry flag. Bit D7 is placed in the
Carry
flag, and the Carry flag is placed in
Example: RAL the least significant position D0. CY is
modified according to bit D7. S, Z, P,
AC
are not affected.
CY D7 D6 D5 D4 D3 D2 D1 D0
Rotate accumulator right through carry

RAR None Each binary bit of the accumulator is
rotated right by one position through
the Carry flag. Bit D0 is placed in the
Carry
flag, and the Carry flag is placed in
Example: RAR the most significant position D7. CY is
modified according to bit D0. S, Z, P,
AC
are not affected.
CY D7 D6 D5 D4 D3 D2 D1 D0
Complement accumulator
CMA none The contents of the accumulator are
Example: CMA complemented. No flags are affected.
Complement carry
CMC none The Carry flag is complemented. No
Example: CMC other flags are affected.
Set Carry
STC none The Carry flag is set to 1. No other
Example: STC flags are affected.
CONTROL INSTRUCTIONS
No operation
NOP none No operation is performed. The
instruction is fetched and
Example: NOP decoded. However no operation is
executed.
Halt and enter wait state
HLT none The CPU finishes executing the
current instruction and halts
Example: HLT any further execution. An interrupt or
reset is necessary to
exit from the halt state.
Disable interrupts
DI none The interrupt enable flip-flop is reset
and all the interrupts
Example: DI except the TRAP are disabled. No
flags are affected.
Enable interrupts
EI none The interrupt enable flip-flop is set
and all interrupts are
enabled. No flags are affected. After a
Example: EI system reset or the
acknowledgement of an interrupt, the
interrupt enable flipflop
is reset, thus disabling the interrupts.
This instruction is
necessary to reenable the interrupts
(except TRAP).
Read interrupt mask
RIM none This is a multipurpose instruction
used to read the status of
interrupts 7.5, 6.5, 5.5 and read serial
Example : RIM data input bit. The
instruction loads eight bits in the
accumulator with the
following interpretations.
Set interrupt mask
SIM none This is a multipurpose instruction and
used to implement the
Example: SIM 8085 interrupts 7.5, 6.5, 5.5, and
serial data output. The
instruction interprets the accumulator
contents as follows.

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V Semester B.

UNIT 1: Introduction to Microprocessor 9 hrs

8085 Instructions -Operation code, Operand & Mnemonics.

Instruction set of 8085-Instruction classification, Addressing modes, Instruction format.

Definition of the Microprocessor: The microprocessor is a programmable device that takes

Fig.1: Pin Diagram of 8085 Fig.2: Functional Diagram of 8085

8085 Microprocessor: Properties-Single + 5V Supply, 4 Vectored Interrupts (One is

Table.1: Machine cycles of 8085

Intel 8085 Microprocessor

Fig.3: Architecture of Microprocessor 8085

Fig.4: Register Array in 8085

Fig.5: Flag Register

1011 0101 1011 0101

Bus Organisation in 8085

How Instruction is executed

1. Immediate Addressing mode: In this mode of addressing data is available in the

Timing Diagram of 8085: Representation of various control signals generated during

Timing Diagram of MVI A,45H instruction

Timing Diagram of MOV A,M instruction

Two byte Instructions:

Data Transfer Instructions

Op code Operand Description

Example: MOV B, C or MOV B, M

Op code Operand Description

MVI Rd, Data Move immediate 8-bit

LDA 16-bit address Load Accumulator

Op code Operand Description

Op code Operand Description

LHLD 16-bit address Load H-L registers direct

STAX Reg. pair Store accumulator indirect

Opcode Operand Description

 The contents of register H are exchanged with the contents of register D.

 The contents of register pair are copied onto stack.

ARITHMETIC GROUP OF INSTRUCTIONS

Opcode Operand Description

Opcode Operand Description

 The contents of register or memory location are incremented by 1.

Opcode Operand Description

RRC None Rotate accumulator right

Opcode Operand Description

Opcode Operand Description

Opcode Operand Description

Opcode Operand Description

Opcode Operand Description

Opcode Operand Description

HLT None Halt

Opcode Operand Description

Counters and Time Delays:

For the given program segment the delay is :

Saving Information on the Stack

The PUSH Instruction

The POP Instruction

Operation of the Stack

The CALL Instruction

The RTE Instruction

Passing Data to a Subroutine

The other possibility is to use agreed upon memory locations.The calling

Call by Reference and Call by Value

Cautions with PUSH and POP

It is not advisable to place PUSH or POP inside a loop.

Interrupts can be classified into two types:Maskable(can be delayed)

Interrupts can also be classified into:Vectored(the address of the service

An interrupt is considered to be an emergencysignal.The Microprocessor