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Named after John von Neumann who wrote First Draft of a report on the
EDVAC (Electronic Discrete Variable Automatic Computer), 1952
address
200
PC
memory data
CPU
200 ADD r5,r1,r3 ADD IR
r5,r1,r3
address
data memory
data PC
CPU
address
Processor
TOS
Mem
+ +
Register renaming:
ADD r10, r0, r1 r4 r2
ADD r11, r2, r3 r0
ADD r12, r4, r10 +
r6
Out-of-order:
Instructions are eligible for issue/execution once source
operands become available
Machine will change order of instructions to keep dispatching.
Substantially faster but also more complex.
a b e f a b e
c g f c nop
d d g nop
expressions instructions
20 Processor Architecure and ARM
Limits in VLIW
VLIW (at least the original forms) has several short-
comings that precluded it from becoming mainstream:
VLIW instruction sets are not backward compatible between
implementations. As wider implementations (more execution
units) are built, the instruction set for the wider machines is
not backward compatible with older, narrower
implementations.
128 bits
0x00..10
Big Endian Little Endian
0x00..13
3 2 1 0 3 2 1 0
0xffffffff
register register
31 Processor Architecure and ARM
ARM Programming Model
r0 r8
r1 r9 0
31
r2 r10
r3 r11 CPSR
r4 r12
r5 r13
r6 r14 NZCV
r7 r15 (PC)
N Z CV I F T Mode
Flag
Cond
CF Destination 0
Assembler:
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
MOV r0,r0,LSL 2 ; perform shift
ADR r4,b ; get address for b
LDR r1,[r4] ; get value of b
AND r1,r1,#15 ; perform AND
ORR r1,r0,r1 ; perform OR
ADR r4,z ; get address for z
STR r1,[r4] ; store value for z
Assembler:
; compute and test condition
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
ADR r4,b ; get address for b
LDR r1,[r4] ; get value for b
CMP r0,r1 ; compare a < b
BGE fblock ; if a >= b, branch to false block
Assembler:
ADR r2,test ; get address for test
LDR r0,[r2] ; load value for test
ADR r1,switchtab ; load address for switch table
LDR r1,[r1,r0,LSL #2] ; index switch table
Assembler
; loop initiation code
MOV r0,#0 ; use r0 for I
MOV r8,#0 ; use separate index for arrays
ADR r2,N ; get address for N
LDR r1,[r2] ; get value of N
MOV r2,#0 ; use r2 for f
ADR r3,c ; load r3 with base of c
ADR r5,x ; load r5 with base of x