IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO.
5, MAY 2007
A Carrier-Based Approach for Compact Modeling
of the Long-Channel Undoped Symmetric
Double-Gate MOSFETs
Jin He, Member, IEEE, Feng Liu, Jian Zhang, Jie Feng, Jinhua Hu, Shengqi Yang,
and Mansun Chan, Senior Member, IEEE
Abstract—This paper presents a carrier-based approach to
develop a compact model for long-channel undoped symmetric
double-gate MOSFETs. The formulation starts from a solution
of the Poisson’s equation that is coupled to the Pao–Sah current
formulation to obtain an analytic drain–current model in terms
of the carrier concentration. The model provides an analytical
expression to describe the dependence of the surface potential,
silicon-film centric potential, inversion charge, and the current on
the silicon-body thickness and the gate-oxide thickness. The model
calculation is verified by comparing results to the 2-D numerical
simulations, and good agreement is observed.
Index Terms—Compact modeling, device physics, double-gate
(DG) MOSFETs, non-charge-sheet approximation, nonclassical
devices.
I. INTRODUCTION
A S CMOS technologies are scaling to the 45-nm regime
and beyond, undoped (or lightly doped) double-gate (DG)
MOSFETs have become the most promising candidates for
extending the device-scaling roadmap because of a number
of advantages such as ideal 60-mV/decade subthreshold
slope, free-dopant-associated fluctuation effects, excellent
short-channel-effect (SCE) immunity, and unique mobility
enhancement [1]–[5]. To allow large-scale evaluation of the
performance of DG-MOSFETs, a compact model is needed.
Modeling of DG-MOSFETs requires a different approach
compared with conventional bulk CMOS due to several
unique physical effects of the DG-MOSFETs, such as the
two conducting-interface coupling, volume inversion, and the
carrier energy-level quantization [6]–[15]. Recently, extensive
Manuscript received June 15, 2006; revised February 1, 2007. This work
was supported in part by the Scientific Research Foundation for the Returned
Oversea Chinese Scholars, by the State Education Ministry (SRF for ROCS,
SEM), by the National Natural Science Foundation of China (90607017), by
the competitive Earmarked Grant HKUST6289/04E from the Research Grant
Council of Hong Kong SAR, and by the International Joint Research Program
(NEDO Grant) from Japan under the Project Code NEDOO5/06.EG01. The
review of this paper was arranged by Editor M.-C. Chang.
J. He, F. Liu, J. Zhang, J. Feng, J. Hu, and S. Yang are with the Multi-Project-
Wafer Center, Institute of Microelectronics, School of Electronic Engineering
and Computer Science, Peking University, Beijing 100871, China (e-mail:
jinhe@ime.pku.edu.cn).
M. Chan is with the Department of Electronic and Computer Engineering,
Hong Kong University of Science and Technology, Clearwater Bay, Kowloon,
Hong Kong.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2007.893812
0018-9383/$25.00 © 2007 IEEE
1203
study of DG-MOSFET device physics and transport mechanism
has been performed [6]–[10] and some preliminary core models
have also been proposed [11]–[21]. For example, two research
groups solved the 1-D Poisson equation to derive analytical
solutions for the potential, charge, and current–voltage char-
acteristics [9]–[18]. Other groups used the charge-based ap-
proach and focus on analytical charge and current expressions
[19]–[21].
A fundamental complication of DG-MOSFETs is the ex-
istence of multiple interfaces that couple to each other. As
a result, the drain–current of DG-MOSFETs cannot be fully
described by an equation with respect to the source and drain
surface potentials but also require the potential at the center
of the silicon film at the source and drain ends [13]. For the
asymmetric and independent gate DG-MOSFETs, the drain–
current calculation would involve the calculation of six channel
potentials and the corresponding coupling factors at the source
and drain ends [14]–[18]. Calculation of these potentials and
their coupling factors in asymmetric and independent DG-
MOSFETs has been found to be difficult and computation
extensive [15]–[17]. On the other hand, charge-based models
provide a simplification in deriving the I–V characteristics, but
they always requires special assumptions and approximations
that compromise the physical detail in describing the device
behavior [19]–[21].
Our recent work on the nonclassical CMOS modeling with
a carrier-based approach has been found to be very useful in
developing an analytic yet continuous compact model for the
ultrathin-body silicon-on-insulator MOSFETs and cylindrical
surrounding-gate devices [22], [23]. This method avoids the
difficulties in calculating the surface and silicon-film centric
potentials as long as the carrier concentrations at the boundaries
are known. The calculation of carrier concentrations is obtained
directly from the Poisson’s equation solution and, thus, requires
minimal approximation. In this paper, a complete carrier-based
analytic core model for long-channel undoped symmetric DG-
MOSFETs is developed using the carrier-based approach. The
model is formulated from the solution of the Poisson equation
and Pao–Sah current expression and covers all operation re-
gions. The model results have been verified by 2-D numerical
simulations and demonstrated to be accurate over a wide range
of operation regions. In the current discussion, some second-
order physics effects such as the SCE, drain-induced barrier
lowering (DIBL), and the quantum–mechanical effects (QMEs)
1204 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 5, MAY 2007

According to Boltzmann statistics, the mobile-electron con-

centration is expressed by the potential


q(φ − φfn )
n = ni exp (2a)
kT
and


q(φ0 − φfn )
n0 = ni exp (2b)
kT
where ni and n0 are the intrinsic carrier concentration and
the induced carrier concentration, respectively, at the reference
point in the x-direction, φo and φfn are the reference point elec-
trostatic potential and the quasi-Fermi potential with respect to
the source end, respectively, and kT /q is the thermal voltage.
The spatial derivative of the electron concentration from (2a)
is written as
dφ kT dn
= (3)
dx qn dx

2
d2 φ kT d2 n kT dn
2
= 2
− 2 . (4)
dx qn dx qn dx
Substituting (4) into (1) gives an equation for the electron
Fig. 1. (a) Diagrams of the undoped symmetric DG n-MOSFET coordinate concentration
and (b) energy-band distribution for the inversion case, where y is the channel
2
direction with the source as the origin and channel length L. x is the vertical d2 n 1 dn q 2 n2
direction of the silicon film with the origin at the silicon-film center and 2
= + . (5)
thickness of Tsi . Since the sourer end is referred to as ground point, the gate dx n dx εsi kT
voltage and the drain voltage are defined as Vgs and Vds , as shown in the figure.
E and ψ are the corresponding energy-band levels. Efn and Efp are electron There is a geometry symmetric point in the silicon-film cen-
and hole quasi-Fermi energy. ter due to the characteristic of the symmetric DG-MOSFETs,
where the electric field is zero. If this geometry symmetric point
is referred as the origin, a solution of the normal differential
are ignored for the sake of simplicity. This exclusion, however,
equation (5) is a trigonometric function from the device physics
should not affect the general validity of the conclusions, and it is
is reasonable
possible to incorporate them later. The effects of second-order
effects are also discussed. c
n(x) =  0   (6)
1/2
2 q 2 c0
cos 2ε kT x
si

II. MODEL DEVELOPMENT

where c0 is the integration constant.
Fig. 1 shows the coordinate system and energy levels of For consistency with the common treatment, the choice of the
an n-channel undoped long-channel symmetric DG-MOSFET. n(x) = no , as the reference at x = 0, further simplifies (6) to
The same voltage is applied to the two gates with the same
work function. Since there is no contact to the silicon body, the n0
n(x) =  1/2  . (7)
energy levels are referred to the electron quasi-Fermi level of q 2 n0
cos2 2εsi kT x
the source. Assume that the quasi-Fermi level is constant across
the silicon-film direction (x-direction) so that the device current
flows only along the channel (y-direction). Under the gradual Substituting (7) into (2a) gives the corresponding
channel approximation, one can write the Poisson’s equation electrostatic-potential distributions in the silicon film
for a silicon region with only mobile electron as
 
1/2 
kT n0 kT −2 q 2 n0
φ(x) = φfn + ln + ln cos x .
d2 φ qn q ni q 2εsi kT
2
= (1) (8)
dx εsi

where n and φ are the mobile-electron concentration and the The electric-field distribution is then obtained by differenti-
spatial electrostatics, respectively, εsi is the permittivity of ating (8)
silicon materials, and the other symbols have the common  1/2 
1/2 
physics meanings. In n-channel DG-MOSFETs, transport due 2n0 kT q 2 n0
E(x) = tan x . (9)
to holes is minimal and can be ignored in the derivation. εsi 2εsi kT
HE et al.: CARRIER-BASED APPROACH FOR COMPACT MODELING 1205

These results are mathematically equivalent to the solutions
presented in the study in [9]–[12]. Our results, however, are
based on a different theoretical path. More compact surface-
potential, field, and total inversion charge expressions can be
obtained in terms of carrier functions, as demonstrated in the
following.
The symmetry of the boundary condition of the DG-
Following Pao–Sah current formulation [24], which as-
sumes that the drift-diffusion transport is valid for the long-
channel DG-MOSFETs, the drain current is obtained by
integrating Ids dy from the source to the drain, expressed
as (dφfn /dn0 )(dn0 /dy)

VDS
0D
n
MOSFETs allows the surface potential and the surface electric W W dφfn
Ids =µ Qi (φfn )dφfn = µ Qi (n0 ) dn0
field to be calculated with (8) and (9), respectively L L dn0
0 n0S
 
1/2  (15)
kT n0 q 2 n0 Tsi
φs = φfn + ln cos−2 (10)
q ni 2εsi kT 2 where n0s and n0d are the solutions of (14) corresponding to
 1/2 
2 1/2  φfn = 0 and φfn = Vds , respectively, µ is the effective mobility
2n0 kT q n0 Tsi (assumed constant here), and W and L are the DG-MOSFET
Es = tan . (11) channel width and length, respectively.
εsi 2εsi kT 2
Note that dφfn /dy can also be expressed as a function of n0
T /2 by differentiating (14). Substituting these factors into (15) and
Defining Qin = q 0 si n(x)dx, half of the total inversion integrating, yield
charge is obtained by performing the integration


2
1/2 W εsi 2kT
2
q n0 Tsi Ids =2 • µ
Qin = [2εsi n0 kT ]1/2 tan . (12) L q
2εsi kT 2


1/2 
1/2 
The surface potential, field, and carrier concentration also  q 2 n0 q 2 n0 Tsi q 2 n0 Tsi
need to obey Gauss’s law with an applied gate voltage. Thus, × tan −
2εsi kT 2εsi kT 2 8εsi kT
we need

 1/2  
Vgs − φm = φs + Qin /Cox (13) 
2
q n0 tox tan 2 q 2 n0 Tsi 
2εsi kT 2  n0s
+ 
where φm is the work-function difference between the gate and 4εox kT  n0d . (16)

the channel and Cox is the gate oxide capacitance with the oxide 
thickens of tox .
Substituting the surface-potential and the inversion-charge
As the charge formulation only accounts for half of the
expressions into (13) gives
total channel, the final current of a symmetric DG-MOSFET
 
1/2  is doubled in (16). The analytical output conductance and the
2
kT n0 q n T transconductance can be derived directly from (16). We would
cos−2
0 si
Vgs − φm − φfn = ln
q ni 2εkT 2 like to point out that (16) is equivalent to the drain–current

1/2  formulation in the study in [11] and [13] if appropriate variable
tox 1/2 q 2 n0 Tsi transformation is performed.
+ [2n0 εsi kT ] tan . (14)
εox 2εkT 2

III. RESULT AND DISCUSSION

Equation (14) gives an exact closed-form expression of
carrier (electron) concentration at the silicon-film center as a
function of gate voltage, channel voltage, silicon film, and gate
oxide thickness. The electron, field, and potential distribution
at the center and interface can then be calculated precisely in
terms of n0 . Comparing with the work in [9]–[12], this equation
comes more directly from the Poisson’s equation without need
of the intermediate variables and auxiliary functions.
For a given Vgs , no is first solved using (14) as a function of
φfn . Along the channel direction, the quasi-Fermi potential φfn
(and, thus, no ) varies from φfn = 0 at the source to φfn = Vds
at the drain. The functional dependence of no (y) and φfn (y)
is determined by the current-continuity principle that requires
the current to be constant and independent of the quasi-Fermi
potential φfn or the channel position y.
The DG-MOSFET characteristics of all regions: From the
linear to the saturation and from the subthreshold to the strong
inversion region can be predicted from the derived model. The
2-D semiconductor-device simulator ISE-TCAD 8.0 has been
used to verify the presented model [25]. A set of the refined
and optimized grid specification was generated for numerical
simulation accuracy and computation efficiency following the
method proposed in [26], which assured that the numerical
result is not highly sensitive to the grid refining and is also
robust for the analyzed test-device structure. The simulation
assumes a constant mobility, (300 cm2 /V-s), and a metal gate
structure without QME. The simulated DG-MOSFET has a
channel length of 2 µm, channel width of 10 µm, and gate oxide
thickness of tox = 2 nm.
1206
Fig. 2. Electrostatic potential and mobile-carrier (electron) distribution in
the silicon film as a function of the gate voltage in the studied long-channel
symmetric undoped MOSFET with a channel length of 2 µm, channel width
of 10 µm, Tsi = 16 nm, gate oxide thickness of tox = 2 nm, and a con-
stant mobility (300 cm2 /V-s) and metal gate structure, obtained from the
presented model.
Fig. 2 illustrates the electron concentration and electrostatic
potential in a silicon film of 16-nm thickness calculated with
the analytic model. It is observed that in the low gate voltage
or the subthreshold region, the electron distribution is almost
constant along the vertical direction of the silicon body. In this
case, an assumption that the inversion-charge density is pro-
portional to the silicon-film thickness is a good approximation
for compact-modeling development, as described in the study
in [19]. With the increase of the effective gate voltage, the
device enters the strong inversion region where the surface-
electron concentration becomes several orders of magnitude
higher than that at center of the silicon body. In this case,
device behaves like a surface-channel bulk MOSFET, and the
surface-electron concentration dominate the inversion-charge
density.
Fig. 3 shows potential at the surface and the center of the
channel versus the applied gate voltage, as calculated using (10)
and the Boltzmann statistics. There are two distinct operation
regions in the undoped symmetric DG-MOSFETs (i.e., the sub-
threshold and the strong inversion region) as in a conventional
bulk MOSFET. It is also observed that the surface-potential
bending gradually saturates as in bulk MOSFETs. The potential
in the center of the film always has a pinch-off voltage value
when the gate voltage is increased. This pinch-off value of
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 5, MAY 2007
Fig. 3. Plot of the surface and centric potentials versus gate voltage for
different quasi-Fermi potential in the studied long-channel symmetric DG-
MOSFET with a channel length of 2 µm, channel width of 10 µm, the
silicon-film thickness of 10 nm, gate oxide thickness of tox = 2 nm, and a
constant mobility (300 cm2 /V-s) and metal gate structure, obtained from the
presented model.
Fig. 4. Inversion-charge characteristics obtained from the analytic model for
two different values of Tsi and Vds = 0.0 V in the long-channel DG-MOSFETs
with a channel length of 2 µm, channel width of 10 µm, gate oxide thickness of
tox = 2 nm, and a constant mobility (300 cm2 /V-s) and metal gate structure.
the centric potential can be predicted from (2b) and (10) with
the augment in a trigonometric function must be less or equal
(π/2), thus
 
kT 2εsi kT π 2
φ0 ≤ φfn + ln . (17)
q q 2 ni Tsi2
This result was also obtained in the study in [10] and [12];
derived independently with a different approach.
Fig. 4 shows the dependence of the channel inversion charge
as a function of the silicon-body thickness illustrating the so-
called “volume inversion effect,” which cannot be described
by any charge-sheet approximation [27]. It is observed that the
silicon-film thickness only changes the amount of subthreshold
inversion charge but has no effect on the strong inversion-
charge density. This verifies the existence of the volume inver-
sion and illustrates that the “volume inversions effect” can be
used to control the subthreshold current in nano nonclassical
CMOS application.
HE et al.: CARRIER-BASED APPROACH FOR COMPACT MODELING
Fig. 5. Ids –Vgs curves for the different silicon-film thickness in the long-
channel DG-MOSFETs with a channel length of 2 µm, channel width of 10 µm,
gate oxide thickness of tox = 2 nm, and a constant mobility (300 cm2 /V-s)
and metal gate structure, calculated from the analytic model (solid curves),
compared with the 2-D numerical simulation results (points). The same currents
are plotted on both logarithmic (left) and linear (right) scales.
Fig. 5 shows the comparison of Ids versus Vgs character-
istics obtained from the analytic model (curves) and the 2-D
simulation (points). The error between the model prediction
and the 2-D numerical device simulator is only about 2%–3%.
This error may be due to numerical uncertainties in the ISE-
TCAD simulation caused by, for instance, a relatively low grid
point density in silicon-body region where a little inversion
charge is induced [26]. Taking this error source into account,
we may conclude that the developed model is physically valid,
and it gives an accurate description of how the charges vary
with gate voltage.
Fig. 5 also shows the “volume inversion” as predicted by both
the model and 2-D device simulation. To optimize the device
performance, the silicon-film thickness should be kept minimal
to suppress the off current. In the subthreshold region, the first
term of the right-hand side in both (14) and (16) dominates, thus
W in nanoscale DG-MOSFETs, such as SCEs, DIBL effect, and
Ids ≈ µ kT Tsi [nos −n0d ]
L QMEs are ignored in this paper for simplicity in the develop-
  
8εsi kT
W q Vg −φm − kT
q ln qn2 T 2
=µ kT ni Tsi e i SI (1−e−qVds /kT ).
L cially at very thin silicon-film thickness. In addition, the SCEs
(18)
It is explicitly predicted from (18) that the subthreshold current
of DG-MOSFE is proportional to the silicon-film thickness but
independent of the gate oxide thickness.
Fig. 6 shows the Ids –Vds curves calculated from the analytic
model (curves) and 2-D numerical simulation results (points),
indicating very good agreement. The analytical model indicates
that the inversion charge and the channel current are dominated
by the last terms of (14) and (16) in the linear region above the
threshold, therefore
W  
Ids ≈ µCox (Vg − ∆φm )2 − (Vg − ∆φm − Vds )2
L
W symmetric undoped DG-MOSFETs has been presented using
= 2µCox (Vg − φm − Vds /2)Vds . (19)
L
From (19), the drain current can be shown to follow a clas-
sical square law up to the saturation region. In the saturation
1207
Fig. 6. Ids –Vds curve of the long-channel DG-MOSFET with a channel
length of 2 µm, channel width of 10 µm, the silicon-film thickness of 10 nm,
gate oxide thickness of tox = 2 nm, and a constant mobility (300 cm2 /V-s)
and metal gate structure, calculated from the analytic model (solid curves),
compared with the 2-D numerical simulation results (points).
region, both the inversion charge and the channel current at the
source are dominated by the last term of (14) and (16), but
are dominated by the first term of (14) and (16) at the drain.
The combination results in

W
Ids =µ Cox (Vg − φm )2
L
    
q Vg −∆φm −ln
8εsi kT
−Vds /kT
qn2 T 2
− kT ni Tsi e i SI . (20)
The expression indicates that the drain–current approaches a
saturation value due to a term that exponentially decreases
increasing Vds .
Finally, we would like to point out that some physical effects
ment of DG-MOSFET core model. The QMEs would increase
the threshold voltage and degrade the subthreshold slope espe-
also lead to the threshold voltage decrease and subthreshold-
slope degradation with the reduction of channel length. It is
difficult to include all these effects in a single study. A more
feasible model-development process is to separately develop
the second-order effect as modules and then integrate them into
the core model. This approach has been applied by many model
developers [2], [6]–[8] and the most famous is BSIM3/BSIM4
[28]. Therefore, the same approach will be used to develop the
complete DG-MOSFET model.
IV. CONCLUSION
In this paper, a carrier-based analytic model for long-channel
a carrier-based approach. The model is derived by solving the
Poisson–Boltzmann equation and the Pao–Sah current formula-
tion. The drain current is described by a single explicit equation
with respect to the carrier concentration at the boundaries that
1208
is valid for all regions of operation. In particular, the volume
inversion that cannot be captured by using the classical charge-
sheet approximation is well accounted for and demonstrated
by the presented model. It is also shown that the predicted
I–V curves agree well with the results obtained with the
2-D numerical simulation, which verified the validity of the
presented model.
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http://www.eecs.berkeley.edu/device/bsim3
Jin He (M’04) received the B.S. degree from Tianjin
University, Tianjin, China, in 1988 and the M.S.
and Ph.D. degrees from the University of Electron
Science and Technology of China, Chengdu, China
in 1993 and 1999, respectively.
From 1999 to 2001, he worked as a Postdoctoral
and Associate Professor at the Institute of Micro-
electronics, Peking University, China. From 2001 to
2005, he worked as a Visiting Scholar and Research
Engineer at the Department of Electrical Engineering
and Computer Sciences, University of California,
Berkeley. He independently developed the core model for BSIM5, the next gen-
eration BSIM MOSFET compact model for mixed-signal application, including
the Hydro-Dynamic and Quasi-Ballistic Transport mechanisms. In August 25,
2005, he came back to the Institute of Microelectronics, School of Electronic
Engineering and Computer Science, Peking University, Beijing, China, as a Full
Professor, starting up the Nano-scale and Tera-Hz Device and Circuit Group,
focusing on new-generation surface-potential-based compact MOSFET model
for 65–32-nm-technology very large-scale integrated circuit simulation and
multigate-device physics research. He has published more than 130 technical
papers in international journals and conferences and coauthored three books.
Feng Liu received the B.S. degree in microelec-
tronics from Nankai University, Tianjin, China, in
2006. He is currently working toward the M.S. de-
gree in the Multi-Project-Wafer Center, Institute of
Microelectronics, School of Electronic Engineering
and Computer Science, Peking University, Beijing,
China.
His research interests include nonclassical device
modeling and circuit performance.
Jian Zhang is currently working toward the B.S. de-
gree in the Department of Microelectronics, Peking
University, Beijing, China.
He is currently with the Group of Nano- & Tera-
Devices and Circuits, under the supervision of Prof.
Jin He. His research interests include device model-
ing of SOI and double gate.
HE et al.: CARRIER-BASED APPROACH FOR COMPACT MODELING
Jie Feng was born in China in 1985. She received
the B.S. degree from Peking University, Beijing,
China. She is currently working toward the M.S.
degree in the Multi-Project-Wafer Center, Institute of
Microelectronics, School of Electronic Engineering
and Computer Science, Peking University.
Her research interests include quantum transport
and spin device modeling.
Jinhua Hu was born in 1984. She received the B.S.
degree from Huazhong University of Science and
Technology, Wuhan, China. She is currently working
toward the M.S. degree in the Multi-Project-Wafer
Center, Institute of Microelectronics, School of Elec-
tronic Engineering and Computer Science, Peking
University, Beijing, China.
Her current research interests include terahertz
wave in solid-state electronics and its device
modeling.
Shengqi Yang received the B.S. degree, the Eco-
nomic Double Major degree, in 2000, and the M.S.
degree, in 2002, from Peking University, Beijing,
China, and the Ph.D. degree from Princeton Univer-
sity, Princeton, NJ, in 2006.
He joined Intel in March 2006, where he was
responsible for video postprocessing algorithm and
architecture design. Currently, he is a Researcher in
the Multi-Project-Wafer Center, Institute of Micro-
electronics, School of Electronic Engineering and
Computer Science, Peking University. His research
interests include low-power and reliable ICs design, multimedia system design,
cryptographic system design, power modeling and optimization, and CMOS
compact modeling.
1209
Mansun Chan (S’92–M’95–SM’01) received the
B.S. degree (highest honors) in electrical engineering
and the B.S. degree (highest honors) in computer
science from the University of California, San Diego,
La Jolla, in 1990 and 1991, respectively, and the M.S.
and Ph.D. degrees from the University of California
at Berkeley, in 1994 and 1995, respectively.
During his undergraduate study, he was with
Rockwell International Laboratory, working on
heterojunction bipolar transistor (HBT) modeling,
where he developed the self-heating SPICE model
for HBT. His research at Berkeley covered a broad area in silicon devices
ranging from process development to device design, characterization, and
modeling. A major part of his work was on the development of record-
breaking silicon-on-insulator (SOI) technologies. He has also maintained a
strong interest in device modeling and circuit simulation. He is one of the
major contributors to the unified BSIM model for SPICE, which has been
accepted by most U.S. companies and the Compact Model Council (CMC)
as the first industrial standard MOSFET model. In January 1996, he joined
the Electrical and Electronic Engineering Faculty at the Hong Kong University
of Science and Technology. Between July 2001 and December 2002, he was a
Visiting Professor at the University of California at Berkeley and the Codirector
of the BSIM program. He is currently consulting on the development of
next-generation compact models. His research interests include nanodevice
technologies, image sensors, SOI technologies, high performance IC, 3-D
circuit technology, device modeling, and Nano BIOMEMS technology.
Dr. Chan was the recipient of the UC Regents Fellowship, Golden Keys
Scholarship for Academic Excellence, SRC Inventor Recognition Award,
Rockwell Research Fellowship, R&D 100 Award (for the BSIM3v3 project),
Teaching Excellence Appreciation Award (1999), and Distinguished Teaching
Award (2004), among others.