Building hierarchical designs in Verilog

Arhitectura Calculatoarelor/Computer Architecture

September 18, 2018

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Verilog hierarchies

Objectives:
I Learn how to instantiate a module
I Construct a design hierarchy

Hierarchical design
- Facilitates design of complex architectures
- Promote design reuse
Instance: a module used as a component in a larger module.
An instances has:
• A module: provides the definition of the instance.
• A container: the module in which the instance is created.
Creating a new instance is referred to as instantiation.

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Instantiation

An instance is constructed by providing the following:

• the name of the module to be instantiated, followed by
• an instance name (to differentiate from other instances of the
same module), followed by
• a list of port connections
List of port connections specifies to which signals from container
are instance’s ports linked.
A port connection is specified like:
.<module_port>(<container_signal>), in which
• module port is a port of the instantiated module
• container signal is an internal signal or a port from container

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4-to-1 multiplexer
Exercise: Build a 4-to-1 multiplexer out of 2-to-1 multiplexers.
Solution: The architecture of the 4-to-1 multiplexer using three
2-to-1 multiplexer modules is depicted bellow. Data input, d, is on
4 lines and the 2-bit selection line, s, propagates one bit of d to the
output, o. For example, if s = (1, 0), input line d[2] is propagated
to o.

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4-to-1 multiplexer (contd.)
The Verilog code implementing the 4-to-1 multiplexer’s
architecture is presented bellow:

1 module m u x 2 s 1 b (
2 input [ 3 : 0 ] d , 17 m u x 1 s 1 b mux2 (
3 input [ 1 : 0 ] s , 18 . d0 ( d [ 2 ] ) ,
4 output o 19 . d1 ( d [ 3 ] ) ,
5 ); 20 . s(s [0]) ,
21 . o(g)
7 wire f ; 22 );
8 wire g ;
24 m u x 1 s 1 b mux3 (
10 m u x 1 s 1 b mux1 ( 25 . d0 ( f ) ,
11 . d0 ( d [ 0 ] ) , 26 . d1 ( g ) ,
12 . d1 ( d [ 1 ] ) , 27 . s(s [1]) ,
13 . s(s [0]) , 28 . o(o)
14 . o( f ) 29 );
15 ); 30 endmodule

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4-to-1 multiplexer (contd.)
The first instance created in the 4-to-1 multiplexer code above has
the following components:
• the module to be instantiated is mux 1s 1b (it must be the
name of an existing Verilog module)
• the instance name is mux1 (it must be a valid Verilog ID)
• the list of port connections, within round parentheses (more
details in the following slide)

10 mux 1s 1b mux1 (
11 .d0(d[0]),
12 .d1(d[1]),
13 .s(s[0]),
14 .o(f)
15 ) ;

c 2018 Opriţoiu Flavius. All Rights Reserved.
4-to-1 multiplexer (contd.)
Detail of the mux_2s_1 emphasizing the mux1 instance and its
connections:

10 m u x 1 s 1 b mux1
11 . d0 ( d[0] ) ,
12 . d1 ( d [ 1 ] ) ,
13 . s(s [0]) ,
14 . o( f )
15 );

Elements of the first port connection:

• d0 - port of the mux_1s_1 module for the connection in line
of code 11 is constructed
• d[0] - signal inside the mux_2s_1 container ( d[0] is a
container’s port, thus a signal in the container ) to which port
d0 is connected

c 2018 Opriţoiu Flavius. All Rights Reserved.
4-to-1 multiplexer (contd.)
Internal wires link internal instances
• connect one instance’s output to another instance’s input
• must be declared inside the container module as wires

Internal wire declaration for the mux_2s_1b architecture:

7 wire f ;
8 wire g ;

c 2018 Opriţoiu Flavius. All Rights Reserved.
 4-to-1 multiplexer (contd.)

Verilog code bellow

• connects mux1’s output, o, to wire f (left)
• connects mux3’s input, d0, to wire f (right)

10 m u x 1 s 1 b mux1 ( 24 m u x 1 s 1 b mux3 (
11 . d0 ( d [ 0 ] ) , 25 .d0(f),
12 . d1 ( d [ 1 ] ) , 26 . d1 ( g ) ,
13 . s(s [0]) , 27 . s(s [1]) ,
14 .o(f) 28 . o(o)
15 ); 29 );

c 2018 Opriţoiu Flavius. All Rights Reserved.
4-to-1 multiplexer (contd.)

Important: When connecting a wire to a port, their widths (in

bits) must match!
If two ports of different widths need to be connected, choose for
the width of the connecting wire the width of one of them. For
connecting the wire to the port of different width:
• if the wire has fewer lines and the other port is an output,
some of the output lines will remain unconnected
• if the wire has fewer lines and the other port to which it
connects is an input, use concatenation to provide the needed
extra input lines (eg. .x({4’d0, data}),)
• if the wire has more lines, regardless of the port being aninput
or an output, use part-select to provide only the needed bits
(eg. .s(addr[15:14]),)

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Three-to-eight-lines decoder with enable input
Exercise: Build a decoder device with three selection lines, an
enable input and active low outputs using decoder components
with two selection lines, enable input and active low outputs.
Solution: The architecture of the three-to-eight-lines decoder,
dec_3x8, is depicted bellow.

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Three-to-eight-lines decoder with enable input (contd.)

Justification: Since the three-to-eight-lines decoder has 8 output

lines it follows that 2 two-to-four-lines decoder components,
dec_2x4 are needed for providing the required number of outputs.
Input lines s[1 : 0] are used as selection lines for the 2 dec_2x4
instances so that the instances’ 4 output lines to be addressed by
consecutive configurations. Selection line s[2] activates only one of
the two dec_2x4 instances assuring proper sequencing of the two’s
outputs. The dedicated enable line activates selection of one of the
two dec_2x4 instances.
The three-to-eight-lines decoder architecture uses:
• 2 two-to-four-lines decoders, dec_2x4
• 2 AND gates and,
• an inverter

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Three-to-eight-lines decoder with enable input (contd.)
Verilog code for the three-to-eight-lines decoder
1 module d e c 3 x 8 (
2 input e ,
3 input [ 2 : 0 ] s ,
4 output [ 7 : 0 ] y
5 );

7 dec 2x4 i1 (
8 . s(s [1:0]) ,
9 . e(e & s [2]) ,
10 . y(y [7:4])
11 );

13 dec 2x4 i2 (
14 . s(s [1:0]) ,
15 . e ( e & (˜ s [ 2 ] ) ) ,
16 . y(y [3:0])
17 );
18 endmodule

c 2018 Opriţoiu Flavius. All Rights Reserved.