NCP1560

Full Featured Voltage Mode

PWM Controller
The NCP1560 PWM controller contains all the features and
flexibility needed to implement voltage−mode control in high
performance single ended DC−DC converters. This device cost
effectively reduces system part count with the inclusion of a high http://onsemi.com
voltage startup regulator that operates over a wide input range of
21.5 V to 150 V. The NCP1560 provides two control outputs, OUT1 MARKING DIAGRAM
which controls the main PWM switch and OUT2 with adjustable 16
16
overlap delay, which can control a synchronous rectifier switch or an
1 NCP1560
active clamp/reset switch. Other distinctive features include: two AWLYWW
mode over current protection, line under/overvoltage lockout, fast line SO−16
feedforward, soft−start and a maximum duty cycle limit. D SUFFIX
1
Features CASE 751B
• Minimum Operating Voltage of 21.5 V NCP1560 = Device Code
A = Assembly Location
• Internal High Voltage Startup Regulator WL = Wafer Lot
• Dual Control Outputs with Adjustable Overlap Delay Y = Year
WW = Work Week
• Single Resistor Oscillator Frequency Setting
• Fast Line Feedforward PIN CONNECTIONS
• Line Under/Overvoltage Lockout 1 16
Vin VAUX
• Dual Mode Overcurrent Protection UV/OV OUT1
• Programmable Maximum Duty Cycle Control NC GND
FF OUT2
• Maximum Duty Cycle Proportional to Line Voltage CS tD
• Programmable Soft−Start CSKIP VREF
RT VEA
• Precision 5.0 V Reference
DCMAX SS
• Pb−Free Package is Available*
Typical Applications ORDERING INFORMATION
• Telecommunication Power Converters Device Package Shipping†
• Industrial Power Converters NCP1560HDR2 SO−16 2500/Tape & Reel
• High Voltage Power Modules
NCP1560HDR2G SO−16 2500/Tape & Reel
• +42 V Automotive Systems (Pb−Free)
• Control Driven Synchronous Rectifier Power Converters †For information on tape and reel specifications,
*For additional information on our Pb−Free strategy and soldering details, please including part orientation and tape sizes, please
download the ON Semiconductor Soldering and Mounting Techniques refer to our Tape and Reel Packaging Specifications
Reference Manual, SOLDERRM/D. Brochure, BRD8011/D.
TX Lout

+ Startup +
SR
Vin Drive Cout Vout
− Feedforward −

Vin FF
M1 Cclamp
NCP1560
UV/OV OUT1
Driver
OUT2 Mclamp
tD
Overlap
Delay Error
Opto
Amplifier

Figure 1. Active−Clamp Forward Converter

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number

July, 2006 − Rev. 7 NCP1560/D
 NCP1560

High Voltage VAUX

Vin Startup
Regulator
5.0 V
VREF
Reference

UV/OV UV OUT1
Fault Delay Output
Modulator
Detection Logic Drivers
CS OUT2

CSKIP tD

RT
Oscillator VEA
FF
SS
GND
DCMAX

Figure 1. Simplified Block Diagram

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 NCP1560

1
Vin
ISTART Disable VAUX

16
VREF
VAUX One Shot 5.0 V Reference
CAUX Pulse DIS 11
(250 ns)
+
14 VAUX(on)/AUX(off) Disable_VREF
−
GND
S Q
Disable_VREF Monotonic
Start RD
Vin + Latch
+
1.52 V − (Reset
− Dominant)
2 R

STOP Disable_ss
UV/OV +
−
+ 12
3.61 V
− tD
VREF
12.3 A DIS 15
Disable − OUT1
S Q
CSKIP + Clock Output
Latch Delay VAUX
6 − (Reset Logic
CCSKIP + Dominant) DIS 13
+ R OUT2
One Shot 2V
−
Pulse VAUX
(600 ns)
+
5 −
+
CS 0.57 V
−
+
Soft Start PWM
−
+ − + Comparator Comparator
0.5 V
VREF − + −
10
VEA
6 A CURRENT MIRROR 2 k
Disable_ss Oscillator Ramp
I1 20 k
9 I1
2 2V
SS
CSS STOP Max DC
10 pF + + − Comparator
−
7 +
+ 2V
RT + * Trimmed during 2V −
RT 1.3 V* manufacturing to obtain −
− 1.3 V with RT = 101 k 2V
One Shot
Clock
Vin Pulse VREF
40 k
I+ V
125 k RMDP
RFF FF Ramp +
4 5.3 k 32 k
+ (Adjustable)
8
FF + VDC(inv) DCMAX
IFF
6.7 k V −
− 27 k RP
−
10 pF CFF

Figure 2. NCP1560 Functional Block Diagram

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 NCP1560

PIN DESCRIPTION
Pin Name Application Information

1 Vin This pin is connected to the bulk DC input voltage supply. A constant current source supplies current from
this pin to the capacitor connected on the VAUX pin. The charge current is typically 13.8 mA. Input voltage
range is 21.5 V to 150 V.

2 UV/OV Input supply voltage is scaled down and sampled by means of a resistor divider. The supply voltage must
be scaled down between 1.52 V and 3.61 V within the specified input voltage range.

3 NC Not Connected.

4 FF An external resistor between Vin and this pin adjusts the amplitude of the FF Ramp in proportion to Vin. By
varying the feedforward ramp amplitude in proportion to the input voltage, changes in loop bandwidth are
eliminated.

5 CS Over current sense input. If the CS voltage exceeds 0.48 V or 0.57 V, the converter enters the
Cycle−by−Cycle or Cycle Skip current limit mode, respectively.

6 CSKIP The capacitor connected between this pin and ground sets the Cycle Skip period. A soft−start sequence
follows at the conclusion of the fault period.

7 RT A single external resistor between this pin and GND sets the oscillator fixed frequency.

8 DCMAX An external resistor between this pin and GND sets the voltage on the Max DC Comparator inverting
input. The duty cycle is limited by comparing the voltage on the Max DC Comparator inverting input to the
Feedforward Ramp.

9 SS An internal 6.2 A current source charges the external capacitor connected to this pin. The duty cycle is
limited during startup by comparing the voltage on this pin to the Oscillator Ramp.

10 VEA The error signal from an external error amplifier is fed into this input and compared to the Feedforward
Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM
Comparator inverting input.

11 VREF Precision 5.0 V reference output. Maximum output current is 6.0 mA.

12 tD An external resistor between VREF and this pin sets the overlap delay between OUT1 and OUT2
transitions.

13 OUT2 Output of the PWM controller with leading and trailing edge overlap delay. OUT2 can be used to drive a
synchronous rectifier topology, an active clamp/reset switch, or both.

14 GND Control circuit ground.

15 OUT1 Main output of the PWM controller.

16 VAUX Positive input supply voltage. This pin is connected to an external capacitor for energy storage. An
internal current supplies current from Vin to this pin. Once the voltage on VAUX reaches 11 V, the current
source turns OFF. It turns ON again once VAUX falls to 7.0 V. During normal operation, power is supplied
to the IC via this pin, by means of an auxiliary winding.

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 NCP1560

MAXIMUM RATINGS
Symbol Rating Value Unit

Vin Input Line Voltage −0.3 to 150 V

VAUX Auxiliary Supply Voltage −0.3 to 16 V

IAUX Auxiliary Supply Input Current 35 mA

VOUT OUT1 and OUT2 Voltage −0.3 to (VAUX + 0.3 V) V

IOUT OUT1 and OUT2 Output Current 10 mA

VREF 5.0 V Reference Voltage −0.3 to 6.0 V

IREF 5.0 V Reference Output Current 6.0 mA

VIO All Other Inputs/Outputs Voltage −0.3 to VREF V

IIO All Other Inputs/Outputs Current 10 mA

TJ Operating Junction Temperature −40 to 125 °C

Tstg Storage Temperature Range −55 to 150 °C

PD Power Dissipation at TA = 25°C 0.77 W

RJA Thermal Resistance, Junction−to−Ambient 130 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1 is the HV startup of the device and is rated to the max rating of the part, or 150 V.
Machine Model Method 150 V.
Pins 2−16: Human Body Model 4000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.

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 NCP1560

ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 k, CCSKIP = 6800 pF,
RD = 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = −40°C to 125°C, unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

STARTUP CONTROL AND VAUX REGULATOR

VAUX Regulation V
Startup Threshold/VAUX Regulation Peak (VAUX increasing) VAUX(on) 10.5 11.0 11.5
Minimum Operating VAUX Valley Voltage After Turn−On VAUX(off) 6.6 7.0 7.4
Hysteresis VH − 4.0 −

Minimum Startup Voltage (Pin 1) VSTART(min) V

ISTART = 1.0 mA, VAUX = VAUX(on) − 0.2 V − 19.3 21.5

Startup Circuit Output Current ISTART mA

VAUX = 0 V
TJ = 25°C 13 17.5 21
TJ = −40°C to 125°C 10 − 25
VAUX = VAUX(on) − 0.2 V
TJ = 25°C 10 13.8 17
TJ = −40°C to 125°C 8 − 19

Startup Circuit Off−State Leakage Current (Vin = 150 V) ISTART(off) A

TJ = 25°C − 23 50
TJ = −40°C to 125°C − − 100

Startup Circuit Breakdown Voltage (Note 2) V(BR)DS 150 − − V

ISTART(off) = 50A, TJ = 25°C

Auxiliary Supply Current After VAUX Turn−On mA

Outputs Disabled
VEA = 0 V IAUX1 − 2.7 5.0
VUV/OV = 0.7 V IAUX2 − 1.3 2.5
Outputs Enabled IAUX3 − 4.6 6.5

LINE UNDER/OVERVOLTAGE DETECTOR

Undervoltage Threshold (Vin Increasing) VUV 1.40 1.52 1.64 V

Undervoltage Hysteresis VUV(H) 0.080 0.098 0.120 V

Overvoltage Threshold (Vin Increasing) VOV 3.47 3.61 3.75 V

Overvoltage Hysteresis VOV(H) − 0.145 − V

Undervoltage Propagation Delay to Output tUV − 250 − ns

Overvoltage Propagation Delay to Output tOV − 160 − ns

CURRENT LIMIT

Cycle−by−Cycle Threshold Voltage ILIM1 0.44 0.48 0.52 V

Propagation Delay to Output (VEA = 2.0 V) tILIM − 90 150 ns

VCS = ILIM1 to 2.0 V, measured when VOUT reaches 0.5 VOH

Cycle Skip Threshold Voltage ILIM2 0.54 0.57 0.62 V

Cycle Skip Charge Current (VCSKIP = 0 V) ICSKIP 8.0 12.3 15 A

2. Guaranteed by design only.

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 NCP1560

ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 k, CCSKIP = 6800 pF,
RD = 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = −40°C to 125°C, unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OSCILLATOR

Frequency (RT = 101 k, Vin = 36 V) fOSC1 kHz

TJ = 25°C 285 300 315
TJ = −40°C to 125°C 280 − 320

Frequency (RT = 59 k, Vin = 36 V, VEA = 1 V) fOSC2 kHz

TJ = 25°C 456 480 504
TJ = −40°C to 125°C 444 − 516

MAXIMUM DUTY CYCLE COMPARATOR

Maximum Duty Cycle (Vin = 36 V, VEA = 3 V, TJ = 25°C) DCMAX %

RP = 0 , RMDP = open 57 62 66
RP = open, RMDP = open 75 80 85

Open Circuit Voltage VDCMAX 0.40 0.47 0.60 V

SOFT−START

Charge Current (VSS = 1.0 V) ISS(C) 5.0 6.2 7.4 A

Discharge Current (VSS = 5.0 V, VUV/OV = 3.7 V) ISS(D) 20 52.5 − mA

PWM COMPARATOR

Input Resistance (V1 = 1.25 V, V2 = 1.50 V) RIN(VEA) 8.0 22 60 k

RIN(VEA) = (V2 − V1)/(I2 − I1)

Lower Input Threshold VEA(L) 0.3 0.7 0.9 V

Delay to Output (from VOH to 0.5 VOH) tPWM − 200 − ns

5.0 V REFERENCE

Output Voltage (IREF = 0 mA) VREF 4.9 5.0 5.1 V

Load Regulation (IREF = 0 to 6 mA) VREF(Load) − 10 50 mV

Line Regulation (VAUX = 7.5 V to 16 V) VREF(Line) − 50 100 mV

CONTROL OUTPUTS

Output Voltage (IOUT = 0 mA) V

Low State VOL − 0.25 −
High State VOH − 11.8 −

Overlap Delay (Vin = 36 V) tD ns

RD = 1 M
Leading − 342 −
Trailing − 312 −
RD = 60 k
Leading 50 77 130
Trailing 32 77 130

Drive Resistance (Vin = 15 V) 

Sink (VEA = 0 V, VOUT = 2 V) RSNK 20 40 80
Source (VEA = 3 V, VOUT = 10 V) RSRC 50 90 170

Rise Time (CL = 100 pF, 10% to 90% of VOH) ton − 30 − ns

Fall Time (CL = 100 pF, 90% to 10% of VOH) toff − 12 − ns

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 NCP1560

TYPICAL CHARACTERISTICS

12 20
VAUX, AUXILIARY SUPPLY VOLTAGE (V)

ISTART, STARTUP CIRCUIT OUTPUT

19 Vin = 48 V
11
STARTUP 18
10 THRESHOLD
17

CURRENT (mA)
16 VAUX = 0 V
9
15
8 14
7 13
MINIMUM VAUX = VAUX(on) − 0.2 V
12
6 OPERATING
THRESHOLD 11
5 10
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Auxiliary Supply Voltage Thresholds Figure 4. Startup Circuit Output Current
versus Junction Temperature versus Junction Temperature
17.5 20
ISTART, STARTUP CIRCUIT OUTPUT

ISTART, STARTUP CIRCUIT OUTPUT

17.0 Vin = 48 V
TJ = −40°C
16
16.5
CURRENT (mA)

CURRENT (mA)

16.0 12 TJ = 25°C

15.5
TJ = 125°C
15.0 8

14.5
4 VAUX = VAUX(on) − 0.2 V
14.0
13.5 0
0 2 4 6 8 10 12 0 25 50 75 100 125 150
VAUX, AUXILIARY SUPPLY VOLTAGE (V) Vin, LINE VOLTAGE (V)
Figure 5. Startup Circuit Output Current Figure 6. Startup Circuit Output Current
versus Auxiliary Supply Voltage versus Line Voltage
IAUX, AUXILIARY SUPPLY CURRENT (mA)

40 4.0
VAUX = 12 V
ISTART(off), STARTUP CIRCUIT OFF−

TJ = −40°C
STATE LEAKAGE CURRENT (A)

35 3.5 VAUX = 12 V

30 3.0
VEA = 0 V
25 TJ = 25°C 2.5

20 2.0
TJ = 125°C
15 1.5 VUV/OV = 0 V
10 1.0

5 0.5
0 0
0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
Vin, LINE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Startup Circuit Off−State Leakage Figure 8. Auxiliary Supply Current versus
Current versus Line Voltage Junction Temperature

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 NCP1560

TYPICAL CHARACTERISTICS

7 4.0
VAUX = 12 V
fOSC = 440 kHz DC [ 50% 3.5
IAUX3, OPERATING AUXILIARY

VUV/OV, UV/OV VOLTAGE (V)

OV THRESHOLD
SUPPLY CURRENT (mA)

fOSC = 300 kHz 3.0

5
2.5
4
2.0
3
fOSC = 87 kHz 1.5
2 UV THRESHOLD
1.0
1 0.5
0 0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Operating Auxiliary Supply Current Figure 10. Line Under/Overvoltage Thresholds
versus Junction Temperature versus Junction Temperature

ILIM, CURRENT LIMIT THRESHOLDS (mV)

160 600

575
VUV/OV(H), UV/OV THRESHOLD

150
VOLTAGE HYSTERESIS (mV)

CYCLE SKIP
OV HYSTERESIS 550
140
525
130
500
120 CYCLE−BY−CYCLE
475
110
450
100 UV HYSTERESIS
425
90 400
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Line Under/Overvoltage Thresholds Figure 12. Current Limit Thresholds versus
Hysteresis versus Junction Temperature Junction Temperature
120 450
fosc, OSCILLATOR FREQUENCY (kHz)

115 VAUX = 12 V 400

RT = 68 k
PROPAGATION DELAY (ns)

110 Measured from VOH to 0.5 VOH 350

tILIM, CURRENT LIMIT

105
300
100 RT = 101 k
250
95
200
90
150
85
80 100
RT = 390 k
75 50
70 0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Current Limit Propagation Delay Figure 14. Oscillator Frequency versus
versus Junction Temperature Junction Temperature

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 NCP1560

TYPICAL CHARACTERISTICS

315 600
fosc, OSCILLATOR FREQUENCY (kHz)

fosc, OSCILLATOR FREQUENCY (kHz)

TJ = 25°C
310 500 DC [ 50%
RT = 101 k
305 400

300 300

295 200

290 100

285 0
−50 −25 0 25 50 75 100 125 150 50 100 150 200 250 300 350 400
TJ, JUNCTION TEMPERATURE (°C) RT, TIMING RESISTOR (k)
Figure 15. Oscillator Frequency versus Figure 16. Oscillator Frequency versus
Junction Temperature Timing Resistor
FEEDFORWARD INTERNAL RESISTANCE (k)

19 90
DCMAX, MAXIMUM DUTY CYCLE (%)

18 80 VEA = 3.0 V
VDCMAX = 0 V
17 70
16
60
15
50
14 TJ = −40°C
40
13
30
12
11 20
TJ = 125°C
10 10
9 0
−50 −25 0 25 50 75 100 125 150 0 75 150 225 300 375 450 525
TJ, JUNCTION TEMPERATURE (°C) IFF, FEEDFORWARD CURRENT (A)
Figure 17. Feedforward Internal Resistance Figure 18. Maximum Duty Cycle versus
versus Junction Temperature Feedforward Current

ISS(D), SOFT−START DISCHARGE CURRENT (mA)

ISS(C), SOFT−START CHARGE CURRENT (A)

100 7.0 70
DCMAX, MAXIMUM DUTY CYCLE (%)

Vin = 36 V
RFF = 432 k 6.5 CHARGE 65
90
6.0 60
RP = OPEN, RMDP = OPEN
80 5.5 55

5.0 DISCHARGE 50
70
4.5 45
RP = 0 , RMDP = OPEN
4.0 40
60
3.5 35
50 3.0 30
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 19. Maximum Duty Cycle versus Figure 20. Soft−Start Charge/Discharge
Junction Temperature Currents versus Junction Temperature

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 NCP1560

TYPICAL CHARACTERISTICS

50 0.85
RIN(VEA), VEA INPUT RESISTANCE (k)

VEA(L), PWM COMPARATOR LOWER

40 0.75

INPUT THRESHOLD (V)

30 0.65

20 0.55

10 0.45

0 0.35
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 21. VEA Input Resistance versus Figure 22. PWM Comparator Lower Input
Junction Temperature Threshold versus Junction Temperature

5.03 350
tD, OUTPUTS OVERLAP DELAY (ns)
VREF, REFERENCE VOLTAGE (V)

300
5.01
250
IREF = 0 mA
4.99 200
IREF = 6 mA
150
4.97

100 RD = 60 k, LEADING

4.95
50

4.93 0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 23. Reference Voltage versus Junction Figure 24. Outputs Overlap Delay versus
Temperature Junction Temperature
RSNK/SRC OUTPUTS DRIVE RESISTANCE ()

450 200
tD, OUTPUTS OVERLAP DELAY (ns)

TJ = 25°C Vin = 36 V
400 CD = 220 pF VAUX = 12 V
160 RMDP = 100 k
350
LEADING
300 120
TRAILING
250
RSRC (VEA = 0 V, VOUT = 10 V)
80
200

150
40
100 RSNK (VEA = 3 V, VOUT = 2 V)

50 0
0 200 400 600 800 1000 1200 1400 −50 −25 0 25 50 75 100 125 150
RD, DELAY RESISTOR (k) TJ, JUNCTION TEMPERATURE (°C)
Figure 25. Outputs Overlap Delay versus Figure 26. Outputs Drive Resistance Voltage
Delay Resistor versus Junction Temperature

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 NCP1560

TYPICAL CHARACTERISTICS
80 35
Measured from 10% to 90% of VOH Measured from 90% to 10% of VOH
70 VAUX = 12 V 30 VAUX = 12 V
ton, OUTPUTS RISE TIME (ns)

toff, OUTPUTS FALL TIME (ns)

TJ = 125°C
60 TJ = 25°C
25 TJ = 125°C
50
20
40 TJ = 25°C
15
30

20 TJ = −40°C 10 TJ = −40°C

10 5

0 0
0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200
CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF)
Figure 27. Outputs Rise Time versus Load Figure 28. Outputs Fall Time versus Load
Capacitance Capacitance

DETAILED OPERATING DESCRIPTION

The NCP1560 PWM controller contains all the features as Dynamic Self Supply (DSS). The VAUX pin can be biased
and flexibility needed for implementation of externally above 7 V once the outputs are enabled to prevent
Voltage−Mode Control in high performance DC−DC the startup regulator from turning ON. It is recommended to
converters. This device cost effectively reduces system part bias the VAUX pin using an auxiliary supply generated out of
count with the inclusion of a high voltage startup regulator. an auxiliary winding from the power transformer. An
The NCP1560 provides two control outputs. Output 1 independent voltage supply can also be used. However, if
controls the main switch of a forward or flyback topology. VAUX is biased before the outputs are enabled or while a
Output 2 has an adjustable overlap delay, which can be used fault is present, the One Shot Pulse Generator (Figure 2) will
to control an active clamp/reset switch, a synchronous not be enabled and the outputs will remain OFF.
rectifier switch, or both. Other distinctive features include: As the DSS sources current to the VAUX pin, a diode should
two mode overcurrent protection, line under/overvoltage be placed between CAUX and the auxiliary supply as shown
lockout, fast line feedforward, soft−start and a maximum in Figure 29. This will allow the NCP1560 to charge CAUX
duty cycle limit. The Functional Block Diagram is shown in while preventing the startup regulator from sourcing current
Figure 2. into the auxiliary supply.
The features included in the NCP1560 provide all the
advantages of Current−Mode Control, fast line ISTART
ISTART To auxiliary supply
feedforward, and cycle−by−cycle current limit. It eliminates Vin VAUX
the disadvantages of low power jitter, slope compensation
and noise susceptibility. IAUX CAUX Isupply

High Voltage Startup Regulator Disable

The NCP1560 contains an internal high voltage startup
regulator that eliminates the need for external startup Figure 29. Recommended VAUX Configuration
components. In addition, this regulator increases the Power to the controller while operating in the self−bias or
efficiency of the supply as it uses no power when in the DSS mode is provided by CAUX. Therefore, CAUX must be
normal mode of operation, but instead uses power supplied sized such that a VAUX voltage greater than 7 V is
by an auxiliary winding. maintained while the outputs are switching and the
The startup regulator consists of a constant current source converter reaches regulation. Also, the VAUX discharge time
that supplies current from the input line voltage (Vin) to the (from 11 V to 7 V) must be greater that the soft−start charge
capacitor on the VAUX pin (CAUX). The startup current is period to assure the converter turns ON.
typically 13.8 mA. Once VAUX reaches 11 V, the startup The startup circuit is rated at a maximum voltage of 150 V.
regulator turns OFF and the outputs are enabled. When VAUX If the device operates in the DSS mode, power dissipation
reaches 7.0 V, the outputs are disabled and the startup should be controlled to avoid exceeding the maximum
regulator turns ON. This “7 − 11” mode of operation is known power dissipation of the controller.

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 NCP1560

Line Under/Overvoltage Shutdown
The NCP1560 incorporates a line under/overvoltage
shutdown (UV/OV) circuit. The undervoltage (UV)
threshold is 1.52 V and the overvoltage threshold (OV) is
3.61 V, for a ratio of 1:2.4.
The UV/OV circuit can be biased using an external
resistor divider from the input line. The resistor divider must
be sized to enable the controller once Vin is within the
required operating range. If the UV or OV threshold is
reached, the soft−start capacitor is discharged, and the
outputs are immediately disabled with no overlap delay as
shown in Figure 30. Also, if an UV condition is detected, the
5.0 V Reference Supply is disabled.

VAUX(on)

VAUX
VAUX(off)

0V

VOV
UV/OV Voltage UV or OV Fault
VUV
0V
Propagation delay to
outputs (tUV or tOV)

OUT2

0V

OUT1

0V

Figure 30. UV/OV Fault Timing Diagram

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 NCP1560

Once the UV or OV condition is removed and VAUX The UV/OV pin can also be used to implement a remote
reaches 11 V, the controller initiates a soft−start cycle. enable/disable function. Biasing the UV/OV pin below its
Figure 31 shows the relationship between the UV/OV UV threshold disables the converter.
voltage, the outputs and the soft−start voltage.

SOFT−START
VAUX(on)
VAUX
VAUX(off)

0V
2V UV/OV Voltage
0V
Soft−Start Voltage
0V

OUT2

0V

OUT1

0V

Figure 31. Soft−Start Timing Diagram (Using Auxiliary Winding)

Feedforward Ramp Generator Figure 18 shows the relationship between IFF and DCMAX.
The NCP1560 incorporates line feedforward (FF) to For example, if a system is designed to operate at 300 kHz,
compensate for changes in line voltage. A FF Ramp with a 60% maximum duty cycle at 36 V, the DCMAX pin can
proportional to Vin is generated and compared to VEA. If the be grounded and IFF is calculated as follows:
line voltage changes, the FF Ramp slope changes T+1+ 1 + 3.33 s
accordingly. The duty cycle will be adjusted immediately f 300 kHz
instead of waiting for the line voltage change to propagate ton(max) + DCMAX T + 0.6 3.33 s + 2.0 s
around the system and be reflected back on VEA.
A resistor between Vin and the FF pin (RFF) sets the CFF VDC(inv) 125 k
IFF +
feedforward current (IFF). The FF Ramp is generated by 6.7 k ton(max)
charging an internal 10 pF capacitor (CFF) with a constant
10 pF 0.888 V 125 k
current proportional to IFF. The FF Ramp is finished + + 82.8 A
6.7 k 2.0 s
(capacitor is discharged) once the Oscillator Ramp reaches
2.0 V. Please refer to Figure 2 for a functional drawing of the As the minimum line voltage is 36 V, the required
Feedforward Ramp generator. feedforward resistor is calculated using the equation below:
IFF is usually a few hundred A, depending on the V
RFF + in * 12.0 k + 36 V * 12.0 k [ 434 k
operating frequency and the required duty cycle. If the IFF 82.8 A
operating frequency and maximum duty cycle are known, From the above calculations it can be observed that IFF is
IFF is calculated using the equation below: controlled predominantly by the value of RFF, as the
CFF VDC(inv) 125 k resistance seen into the FF pin is only 12 k. If a tight
IFF + maximum duty cycle control over temperature is required,
6.7 k ton(max)
RFF should have a low thermal coefficient.
where VDC(inv) is the voltage on the inverting input of the
Max DC Comparator and ton(max) is the maximum ON time.

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 NCP1560

Current Limit The cycle skip period is set by an external capacitor

The NCP1560 has two over current protection modes,
cycle−by−cycle and cycle skip. It allows the NCP1560 to
handle momentary and hard shorts differently for the best
tradeoff in performance and safety. The outputs are disabled
typically 90 ns after a current limit fault is detected.
The cycle−by−cycle mode terminates the conduction
cycle (reducing the duty cycle) if the voltage on the CS pin
exceeds 0.48 V. The cycle skip mode is enabled if the
voltage on the CS pin reaches 0.57 V. Once a cycle skip fault
is detected, the outputs are disabled, the soft−start and cycle
skip capacitors are discharged, and the cycle skip period
(TCSKIP) commences.
(CCSKIP). Once a cycle skip fault is detected, the cycle skip
capacitor is discharged followed by a charge cycle. The
charge current is 12.3 A. The cycle skip period ends when
the voltage on the cycle skip capacitor reaches 2.0 V. The
cycle skip capacitor is calculated using the equation below:
TCSKIP 12.3 A
CCSKIP [
2V
Using the above equation, a cycle skip period of 11.0 s
requires a cycle skip capacitor of 68 pF. The differences
between the cycle−by−cycle and cycle skip modes are
observed in Figure 32.

NORMAL
NORMAL ILIM1 ILIM2 OPERATION
OPERATION RESET SOFT−START
VAUX(on)
VAUX
VAUX(off)

0V

OUT2

0V

OUT1

0V
ILIM2
ILIM1
CS Voltage
0V
TCSKIP

Cycle Skip
Voltage
0V

Figure 32. Over Current Faults Timing Diagram

Once the cycle skip period is complete and VAUX reaches
11 V, a soft−start sequence commences. The possible
minimum OFF time is set by CCSKIP. However, the actual
OFF time is generally greater than the cycle skip period
because it is the cycle skip period added to the time it takes
VAUX to reach 11 V.
Oscillator
The NCP1560 oscillator frequency is set by a single
external resistor connected between the RT pin and GND.
The oscillator is designed to operate up to 500 kHz.
The voltage on the RT pin is laser trim adjusted during
manufacturing to 1.3 V for an RT of 101 k. A current set
by RT generates an Oscillator Ramp by charging an internal
10 pF capacitor as shown in Figure 2. The period ends
(capacitor is discharged) once the Oscillator Ramp reaches
2.0 V. If RT increases, the current and the Oscillator Ramp
slope decrease, thus reducing the frequency. If RT decreases,
the opposite effect is obtained. Figure 16 shows the
relationship between RT and the oscillator frequency.

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 NCP1560

Maximum Duty Cycle 5.0 V Reference

A dedicated internal comparator limits the maximum ON
time of OUT1 by comparing the FF Ramp to VDC(inv). If the
FF Ramp voltage exceeds VDC(inv), the output of the Max
DC Comparator goes high. This will reset the Output Latch,
thus turning OFF the outputs and limiting the duty cycle.
Duty cycle is defined as:
t when an UV fault is present.
DC + on + ton f
T
Therefore, the maximum ON time can be set to yield the
desired DC if the operating frequency is known. The
maximum ON time is set by adjusting the FF Ramp to reach
VDC(inv) in a time equal to ton(max) as shown in Figure 33.
The maximum ON time should be set for the minimum line
voltage. As line voltage increases, the slope of the FF Ramp
increases. This reduces the duty cycle below DCMAX, which
is a desirable feature as the duty cycle is inversely
proportional to line voltage.
Oscillator Ramp
2V
The NCP1560 includes a precision 5.0 V reference output.
The reference output is biased directly from VAUX and it can
supply up to 6 mA. Load regulation is 50 mV and line
regulation is 100 mV within the specified operating range.
It is recommended to bypass the reference output with a
0.1 F ceramic capacitor. The reference output is disabled
PWM Comparator
The output of an external error amplifier is compared to
the FF Ramp by means of the PWM Comparator. The
external error amplifier drives the VEA input. There is a
0.7 V offset between the VEA input and the PWM
Comparator inverting input. The offset is provided by a
series diode and resistor. If the voltage on the VEA input is
below 0.7 V, the outputs are disabled.
The PWM Comparator controls the duty cycle by turning
OFF the outputs once the FF Ramp voltage exceeds the
offset VEA voltage. The VEA range required to control the
DC from 0% to DCMAX is given by the equation below:
VEA(L) t VEA t ǒ186.56
IFF DC
pf f
) VEA(L)Ǔ

0V where, VEA(L) is the PWM comparator lower input

T
threshold.

Soft−Start
FF Ramp VDC(inv) Soft−start (SS) allows the converter to gradually reach
0V steady state operation, thus reducing startup stress and
ton(max) surges on the system. The duty cycle is limited during a
Figure 33. Maximum ON Time Limit Waveforms soft−start sequence by comparing the Oscillator Ramp to the
SS voltage (VSS) by means of the Soft−Start Comparator.
An internal resistor divider from a 2.0 V reference is used A 6.2 A current source starts to charge the capacitor on
to set VDC(inv). If the DCMAX pin is grounded, VDC(inv) is the SS pin once faults are removed and VAUX reaches 11 V.
0.88 V. If the pin is floating, VDC(inv) is 1.19 V. This is The Soft−Start Comparator controls the duty cycle while the
equivalent to 60% or 80% of a 1.5 V FF Ramp. VDC(inv) can SS voltage is below 2.0 V. Once VSS reaches 2.0 V, it exceeds
be adjusted to other values by using an external resistor the Oscillator Ramp voltage and the Soft−Start Comparator
network on the DCMAX pin. For example, if the minimum does not limit the duty cycle. Figure 34 shows the
line voltage is 36 V, RFF is 434 k, operating frequency is relationship between the outputs duty cycle and the
300 kHz and a maximum duty cycle of 70% is required, soft−start voltage.
VDC(inv) is calculated as follows:
IFF 6.7 k ton(max) Oscillator
VDC(inv) + Ramp VSS
CFF 125 k
88.2 A 6.7 k 2.33 s
VDC(inv) + +1.10 V
10 pF 125 k
This can be achieved by connecting a 45.3 k resistor OUT2
from the DCMAX pin to GND. The maximum duty cycle
limit can be disabled connecting a 100 k resistor between
the DCMAX and VREF pins.
OUT1

Figure 34. Soft−Start Timing Diagram

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 NCP1560
If the soft−start period is too long, VAUX may discharge to
7.0 V before the converter output is completely in regulation
causing the outputs to be disabled. If the converter output is
not completely discharged when the outputs are reenabled,
the converter will eventually reach regulation exhibiting a
nonmonotonic startup behavior. But, if the converter output
is completely discharged when the outputs are reenabled, the
cycle may repeat and the converter will not start.
In the event of an UV, OV, or cycle skip fault, the soft−start
capacitor is discharged. Once the fault is removed, a
soft−start cycle commences. The soft−start steady state
voltage is approximately 4.1 V.
Control Outputs
The NCP1560 has two in−phase control outputs, OUT1
and OUT2, with adjustable overlap delay (tD). OUT2
precedes OUT1 during a low to high transition and OUT1
precedes OUT2 at any high to low transition. Figure 35
shows the relationship between OUT1 and OUT2.
tD (Leading) tD (Trailing)
OUT1
OUT2
Figure 35. Control Outputs Timing Diagram
Generally, OUT1 controls the main switching element.
Output 2, once inverted, can control a synchronous rectifier.
The overlap delay prevents simultaneous conduction.
Output 2 can also be used to control an active clamp reset.
Once VAUX reaches 11 V, the internal startup circuit is
disabled and the One Shot Pulse Generator is enabled. If no
faults are present, the outputs turn ON. Otherwise, the
outputs remain OFF until the fault is removed and VAUX
reaches 11 V again.
The control outputs are biased from VAUX. The outputs
can supply up to 10 mA each and their high state voltage is
usually 0.2 V below VAUX. Therefore, the auxiliary supply
voltage should not exceed the maximum input voltage of the
driver stage.
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17
If the control outputs need to drive a large capacitive load,
a driver should be used between the NCP1560 and the load.
ON Semiconductor’s MC33152 is a good selection for an
integrated driver. Figures 27 and 28 shows the relationship
between the output’s rise and fall times vs capacitive load.
Time Delay
The overlap delay between the outputs is set connecting
a resistor (RD) between the tD and VREF pins. An overlap
delay of 80 ns is obtained when RD is 60 k. A higher delay
is obtained by increasing RD. As RD increases, the bias
current of the time delay circuit is reduced, increasing its
noise susceptibility. If a delay higher than 150 ns is required,
it is recommended to place a small capacitor between the tD
pin and ground.
The output duty cycle can be adjusted from 0% to 85%
selecting appropriate values of RFF and VDC(inv). It should
be noted that the overlap delay may cause OUT2 to reach
100% duty cycle. Therefore, if OUT2 is used, the maximum
duty cycle of OUT2 needs to be kept below 100%. The
maximum overlap delay, tD(max), depends on the maximum
duty cycle and frequency of operation. The maximum
overlap delay is calculated using the equation below.
(1 * DC)
tD(max) v
2ƒ
For example, if the converter operates at a frequency of
300 kHz with a maximum duty cycle of 80%, the maximum
allowed overlap delay is 333 ns. However, this is a
theoretical limit and variations over the complete operating
range should be considered when selecting the overlap
delay.
Additional Information
A 100 W DC−DC converter for telecom systems is
designed and implemented using the NCP1560. The
converter delivers 100 W at 3.3 V and achieves a full load
efficiency of 85%. The system is built using a 4 layer FR4,
single sided board. The components location within the
board is shown in Figure 36 and the complete circuit
schematic is shown in Figure 37. The converter design is
discussed in Application Note AND8105/D. Please contact
your sales representative for board availability.
 NCP1560

2.70”

3.10”

Figure 36. Board Arrangement

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 NCP1560

C29 R6

3.3 V
C30

E4
−
+
E5
100 p 1k
4
R31 R21 R22 1000 p

C20 330 10 249 k 150 k

3 5
C19 330 U3

IRFR9220
C25 0.1 R29 TLV431
C18 47 2 3 5.1 k

C26*

X2
C31

0.1
C24 470 p 4 + 8

−
C17 47
R20 2k U6A

MMBD914
LM358 1 0.1
C16 47
D9

B
R19

R17
C15 47

10k
10 k

A
SEC_PWR
2 H

1000 p
L2

6 5
C21
R26
6.2

+ U6B C13

−
R30

MMBD914
D4
10 k LM358 0.047

NTB75N03 L09 7

OUT2 (Isolated)
X4
X5 D5

EA (out)
MMBT2907

OUT2 (Isolated)
R25 MMBD914
SEC_PWR

10 k D7 R28
C23
MMBD914 0 (Short) X1 0.1
R24 10 k
NTB75N03L09

X3 C22 1000 p NTB30N20

R23

0 (Short) R27 6.2 R16

6,7 1T 8,9 10 k C12 XT3

EA (out)
49.9
XT2

R13

VAUX
1PMT5929BT1

A
0.1
10 3T 1 11 5T 2 4 2T 5 R15

Open
Open
0 (Short)

D3
R34
MMBD914 D2 C14

R33
1.27 k

0
D10
R14
MURS120T3

XT1
MJD44H11

1:100
0.1

0
D6*

8
7
6
5

R9
X6

C10

SFH6156A−4
OUT_A

OUT_B
N/C

VCC

R12
10 k
MC33152

0.1

U4
MMBT914

U2
D8

D1
IN_A
GND
IN_B
N/C

MMBD914 R18
R11
VREF
VAUX

6.81 5.1 k
1
2
3
4

R8
R10
100 C11 0 (Short)

*Note: D6 is removed for active clamp/reset operation.

C9 2200 p
1000 p

C26 is removed for reset winding operation.

R3 487 k R7
15
13
10

110 k
4
5

8
9
7

R2 100
FF

OUT1
OUT2
VEA
DCMAX
SS
CS

RT
NCP1560

R1 1M
U1

C4 4.7
UV/OV

CSKIP

C27
VREF
VAUX

GND
N/C

C5 0.1
Vin

tD

C3 4.7
0.1
1
3
2

6
16

12

14
11

C2 4.7
C28 1000 p
C1 4.7
C6 0.01 R5
110 k
L1 R4 C8 0.1
10 H
47.5 k
E1

E3
E2

VREF
C7 10
VAUX
Vin
−
+

ON/OFF

Figure 37. Complete Circuit Schematic

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 NCP1560

PACKAGE DIMENSIONS

SO−16
D SUFFIX
CASE 751B−05
ISSUE J

−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
−B− MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
−T− SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

The product described herein (NCP1560) may be covered by one or more U.S. patents. There may be other patents pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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