Prof. S.

Ben-Yaakov , DC-DC Converters [6- 1]

Output Voltage Ripple, Parasitic Effects

6.1 Output voltage ripple (Buck)

6.2 Parasitic effects
6.2.1 Diode recovery
6.2.2 Internal delay of switching
6.2.3 Stray and leakage inductances
● Clamp
● Diode snubber (clamp)
● Switch snubbers

Prof. S. Ben-Yaakov , DC-DC Converters [6- 2]

Output voltage ripple

IL
L
S Iav
Vin C R
D IL IC
control IR t
IR Iav DC

zAssumption: t
Low output ripple voltage IC Capacitor Current
AC
t

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 Prof. S. Ben-Yaakov , DC-DC Converters [6- 3]

IC Ripple
∆IL
2 t
t1 t2 ∆IL
VC Ts

∆Vc t

t2
∆Q
∆VC = ; ∆Q = ∫ IL dt;
C ∆IL 1
t1
∆VC =
∆IL Ts 1 ∆IL 8C fs
∆Q = ⋅ ⋅ ; ∆Q = Ts
2 2 2 8

Prof. S. Ben-Yaakov , DC-DC Converters [6- 4]

∆IL = Vo t off / L ∆IL =

Vo VD
Doff Ts = o off Ripple
L Lfs
VoDoff 1 VD
∆VC = = o off2
CLfs 8fs 8CLfs
VoDoff
The effect of fs ∆I =
Lfs
∆IL
L; fs can be traded for same ∆I ∆VC =
8fsC

C;fs can be traded for same ∆I& ∆VC VoDoff

∆VC =
if fs is increased for given L, C 8LCfs2

∆VC goes down -40 db/dec (second order)

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 Prof. S. Ben-Yaakov , DC-DC Converters [6- 5]

L
Example
S ∆IL = 1A
Vin R
D IL IC
C C = 47 µF
control IR
Ts = 10 µS
ESR = 10 mΩ
Find the output voltage ripple ∆V
1A ⋅ 10 µS
∆VC = = 25 mV
8 ⋅ 47µF
∆VESR = 10 mΩ ⋅ 1A = 10 mV

zApproximate (upper limit) of total ripple)

∆V = ∆VC + ∆VESR = 25 mV + 10 mV = 35 mV

Prof. S. Ben-Yaakov , DC-DC Converters [6- 6]

Application of Simulation
10meg
R4

D1
out
Dbreak
L1 L2
V1 {L1} C1 RL
{Vin} {L1*(n*n)}
220u {Load}
out_gnd IC = 6
drain

S1 K K1
0 gate + K_Linear PARAM ET ERS:
+
- - COUPLING = 1 n = 0.5
L1 = l1 Vin = 12
V1 = 0 V2 Sbreak L2 = l2 L1 = 300u
V2 = 15 Load = 10
TD = 0
TR = 0.01u 0
TF = 0.01u
PW = 10u
PER = 20u
0
Modify circuit to include
ESR=100mΩ
Find ripple at output

3
 Prof. S. Ben-Yaakov , DC-DC Converters [6- 7]

Diodes Recovery – Implications

L Vx Vo
Vin
R Reverse current at
C
switch turn on

zSoft and hard recovery

Prof. S. Ben-Yaakov , DC-DC Converters [6- 8]

Stages in diode recovery

Lstray Diode voltage

Lstray VD t
ESR
Lstray VO

VDmax

Lstray
Lstray
ESR

4
 Prof. S. Ben-Yaakov , DC-DC Converters [6- 9]

Turn “off” of transistor

Lmain Lmain
Lstray Lstray

Co Vo
Lstray Lstray
Lstray ESR

V DS

VO

Prof. S. Ben-Yaakov , DC-DC Converters [6- 10]

Diode forward recovery

+VC

I L

t
VD
VPK clamp

VF t

5
 Prof. S. Ben-Yaakov , DC-DC Converters [6- 11]

Parasitic effects: Internal delay

To turn “on”
RL RG
CGS ′ (real)
Vgs
RL
Vgs
LS

Vgs
LS
Cgs
V'gs Depend on Q Q=
RL + R G

Prof. S. Ben-Yaakov , DC-DC Converters [6- 12]

Clamps
Vin
∗ limiting maximum voltage Vo′

VO Ipk
Vin Llkg

Vds Cdss

V DS
Llkg
VO
Cdss
t

6
 Prof. S. Ben-Yaakov , DC-DC Converters [6- 13]

Solutions

n:1 VO Vin n:1 VO

Vin

Very fast diode

Llkg Llkg

Cdss Rc Cc

Vz > Vin + Vo’ = Vin + nVo

Prof. S. Ben-Yaakov , DC-DC Converters [6- 14]

Simple Example
Vin

Clamp B is better
A
from the point of view
Vin of efficiency.

VC ( A ) = Vin + Vo′

B
But ...

7
 Prof. S. Ben-Yaakov , DC-DC Converters [6- 15]

Parasitic inductance
L1
Vin
Energy of L1 L2 L3 L4 will
cause high spike on C (FET).
The FET is not protected!

L4
L2 L3

Rule:
Connect clamps and snubbers directly to the
elements to be protected

Prof. S. Ben-Yaakov , DC-DC Converters [6- 16]

To protect FET
Vin
Line

LD
Line RG
Still: G

LS

8
 Prof. S. Ben-Yaakov , DC-DC Converters [6- 17]

Designing the Snubber Components

Vin
Rc
Cc
Llkg

Prof. S. Ben-Yaakov , DC-DC Converters [6- 18]

Snubber
VCc ∆V
Vav

Ts

L lkg Parasitic energy Ipav

+
Ip
Vo' CC R C VCc

VCc Cc Rc
VCc > Vo’

9
 Prof. S. Ben-Yaakov , DC-DC Converters [6- 19]

Leakage discharge
dI
Ipk Ip
dt
Ip av· Rc = VCc av

Rc· Cc = T > Ts
tp

dIp VCc av − Vo '

=
dt L lkg

L lkg Ipk
tp =
VCc av − Vo '

Prof. S. Ben-Yaakov , DC-DC Converters [6- 20]

Leakage average current

Ipk ⋅ t p
Ip av = ⋅ fs
2
Procedure

1. Select VCc av

2. Calculate Ip av
VCc av
3. Select R c =
Ip av
4. Select Cc T > Ts

5. Trim in-circuit

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 Prof. S. Ben-Yaakov , DC-DC Converters [6- 21]

Simulation Exercise
10meg
R4

D1
out
Dbreak
L1 L2
V1 {L1} C1 RL
{Vin} {L1*(n*n)}
220u {Load}
out_gnd IC = 6
drain

S1 K K1
0 gate K_Linear PARAM ET ERS:
+ +
- - COUPLING = 1 n = 0.5
L1 = l1 Vin = 12
V1 = 0 V2 Sbreak L2 = l2 L1 = 300u
V2 = 15 Load = 10
TD = 0
TR = 0.01u 0
TF = 0.01u
PW = 10u
PER = 20u
0

z Add 1uH leakage to Flyback converter. Design a

clamp and check it by simulation.

Prof. S. Ben-Yaakov , DC-DC Converters [6- 22]

Diode Snubber (clamp)

Vo

CD

Lstray Lstray

Diode Snubber

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 Prof. S. Ben-Yaakov , DC-DC Converters [6- 23]

Snubber waveforms
VD
no snubber bad snubber
CS RS
Vo

VO
CD
Lstray
VD
CS is very l arg e
good snubber
VO
Cs > CD

V 2CS
Energy lost to snubber
2

Prof. S. Ben-Yaakov , DC-DC Converters [6- 24]

Snubber design
Design - use simulation in circuit tuning
CS R
S
Needed information
Ipk ( Reverse )
Lstray Ipk VO
Lstray

2
L stray Ipk
⇒ moves to Cs ⇒ Vo + ∆V
2
R s ⇒ damping

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 Prof. S. Ben-Yaakov , DC-DC Converters [6- 25]

Switch Snubbers
control
VGS
t

VS VS
IS

t
Jd
Pswitching

Switching losses due to overlap Pd linear with fS !

Prof. S. Ben-Yaakov , DC-DC Converters [6- 26]

Snubber types

dV dI
Snubbers = control of or
dt dt

dV
snubbers
dt

dI
snubbers
dt

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 Prof. S. Ben-Yaakov , DC-DC Converters [6- 27]

Snubber types
Passive (dissipative) snubber
∗ Energy lost to heat

Non-dissipative (lossless) snubber

∗ Energy recovered

Passive Snubbers
∗ by passive network

Active snubbers
∗ by auxiliary active devices

Prof. S. Ben-Yaakov , DC-DC Converters [6- 28]

Switching overlap
control
VGS
t

VS dV
dI IS dt
dt
t
Jp

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 Prof. S. Ben-Yaakov , DC-DC Converters [6- 29]

Switch Snubber
Vo

dV
dt (at turn off) can be slow down by adding external
snubber capacitor C
Vo
At turn off
Cdss C

Prof. S. Ben-Yaakov , DC-DC Converters [6- 30]

dV/dt
dV I
=
dt C + Cdss

Cdss - output capacitance of FET

I = 1 Amp
C + Cdss= 1nF

dV 1 103
= = = 1 kV
dt 10 − 9 10 − 6 µS

15
 Prof. S. Ben-Yaakov , DC-DC Converters [6- 31]

Capacitor losses
Vo

2 2
CVO CV
Problem at turn on ! EC = (J ) Pd = O ⋅ fs
2 2
Example : VO = 400 V C = 1 nF
fs = 100 kHz

10 − 9 ⋅16 ⋅ 10 4
Pd = ⋅ 105 = 8 W
2

Prof. S. Ben-Yaakov , DC-DC Converters [6- 32]

Solution
VO

CS

RS

VO
CS
Snubbing

16
 Prof. S. Ben-Yaakov , DC-DC Converters [6- 33]

Reset
VO
If Rds on < Rs most energy will
CS be lost to Rs → Heat
RDSon
Selection of Cs →
RS Selection of Rs → to ensure reset

1
T= << t on t on ≈ 4R sCs
R sC s

Prof. S. Ben-Yaakov , DC-DC Converters [6- 34]

CV 2 Losses
2

Cdss 2 
 Cdss Vmax
  fs → lost to heat
 2 

Linear with fs !
Switching losses (overlap) also
linear with fs !

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 Prof. S. Ben-Yaakov , DC-DC Converters [6- 35]

Lossless snubbing (simple example)

Q1

VC t
C1
L 2 Q2
delay
t
VC IL
C2
2 t

VDS1
C1 , C2 of transistor t
plus external (if any) VDS2

Prof. S. Ben-Yaakov , DC-DC Converters [6- 36]

Dead time requirement

Q1

t
Q2
delay
t
IL
t

VDS1

t
VDS2

18