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International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882

132 EATHD-2015 Conference Proceeding, 14-15 March, 2015

Design of CMOS Inverter Using Different Aspect Ratios


1
Pankaj Gautam, 2Devesh Kaushik, 3Rahul Sharma
Student, B. Tech. 4th Year, Shanti Institute Of Technology Kurali, Meerut
4
Gyan Prakash Pal
Assistant Professor, Shanti Institute Of Technology Kurali, Meerut

ABSTRACT CMOS logic circuits dissipate much less power than


The aim of this paper is to show the effect of W/L ratio bipolar logic circuits and thus one can pack more
parameters of CMOS, which characterized the CMOS CMOS circuits on a chop than is possible with bipolar
structure. It is also analysis the current value, threshold circuits. The high input impedance of the MOS
voltage value and other related parameters of CMOS transistor allows the designer to use charge storage as
inverter. MOSFET device is the 4 terminal devices a means for the temporary storage of information in
GATE, DRAIN, SOURCE AND BODY (substrate). both logic and memory circuits.
W/L is the most important factor of CMOS. Hence
considering we can change the value of W/L of CMOS II. NMOS LOGIC DESIGN & NMOS
and then measure the physical parameters to reach the INVERTER CIRCUIT
accepted goal using Microwind 3.1 software. MOS transistors (both PMOS and NMOS) can be
combined with resistive loads to create single channel
Key words: CMOS parameters, threshold voltage, W/L logic gates.
ratio. The circuit designer is limited to altering circuit
topology and the width-to-length (W/L) ratio since the
I. INTRODUCTION other factors are dependent upon processing parameters.
CMOS is by far the most popular technology for the Resistive load inverter takes up too much area for and IC
implementation of digital systems. The small size, ease design. The saturated load configuration is the simplest
of fabrication, and low power dissipation of MOSFETS design, but V never reaches V , and it has a slow
H DD
enable extremely high levels of integration of both logic
switching speed. The linear load inverter fixes the speed
and memory circuit’s .Digital IC Technologies and
and logic level issues, but it requires an additional power
Logic-Circuit Families. CMOS: CMOS technology is,
supply for the load gate. The depletion-mode NMOS
by a large margin, the most dominant of all the IC
load requires the most processing steps, but needs small
technologies available for digital-circuit design. These
area to achieve the high speed, V = V , and best
are a number of reasons for this development, the most H DD
important of which is the much lower power dissipation combination of noise margins. The Pseudo NMOS
of CMOS circuits. Generally all parameters of CMOS inverter offers the best speed with the lowest area.
are depending on the w/l ratio. Analysis the parameters
of CMOS after changing in the w/l ratio. CMOS III. CMOS INVERTER
parameters change when w/l ratio is followed. CMOS transistors use all three bias states described
here: OFF-state, saturated-state, and the linear -state
1. w = 1 µm, & L = 1 µm (ohmic, non-saturated). We will next look at curves
2. w= 0.5 µm & L=1 µm illustrating MOS transistor parameters, and learn the
3. w = 1 µm & L = 0.5 µm analytical equations that predict and analyze transistor
4. w = 0.5 µm & L = 0.2 µm behavior. It is important to work through all examples
and exercises. It is instructive to return to this transistor
description after acquiring skill in transistor circuit
analysis.
CMOS inverter is the combination network of pull-up-
network and pull- down-network. Pull-up-network is
known as load part, where as we can use totally PMOS.
The PMOS pull-up-network, on other hand, must be the
dual network of the n-net. This means that all the
parallel connection in the NMOS pull-down-network

Shanti Institute of Technology, Meerut (U.P.) - 250501, India


International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
133 EATHD-2015 Conference Proceeding, 14-15 March, 2015

will correspond to a series connection in the PMOS pull- V. MOSFET PARAMETERS


up-network, and all the series connection in the NMOS  iD – Drain current
pull-down-network will correspond to a parallel  VTP,VTN – Threshold voltage (VTH)
connection in the PMOS pull-up-network
 vDS – Drain to source voltage
 vGS – Gate to source voltage
 vB – Bulk voltage

VI. OXIDE CAPACITANCE


 Cox=EOX / TOX
 EOX=3.9O
 O=8.85*10-14 F/CM

VII. PARAMETER DEFINITIONS


 n,p – Electron or hole mobility
 ox – Permittivity of oxide
 tox – Oxide thickness
Figure 1: CMOS inverter circuit  (W/L) – Aspect ratio
IV. CHARACTERISTICS OF CMOS vGS  VTH  iD  0
INVERTER
 W  1 2 
vDS  vGS  VTH   iD  k n'   vGS  VTH vDS  vDS 
 L  2

1 ' W 
vDS  vGS  VTH   iD  k n  vGS  VTH 
2

2 L

VIII. DURING CHANGE THE W/L RATIO


W/L ratio is the most important parameter of the
inverter .inverter channel & flow of current and all
parameters of CMOS /NMOS are effected . In this
paper we have study the all parameters of CMOS
Figure 2: CMOS inverter characteristics curve
during changing in the w/l ratio .change the w/l ratio as
half, double and same width or as requirement of
We know that an inverter how can acts. an
operation. The following layout of a MOSFET has
inverter provides maximum output on minimum input.
given L=4 λ and W= 8 λ. Use the EE143 layout graph
A CMOS inverter performs this operation in different
paper to layout a minimum-size transistor. Label the
modes as CUTT OFF, SATURATION, LINEAR.
design rules you used.
CMOS provide maximum output on minimum input
and minimum output on max input. CMOS operates in
those modes, they are followed...

VIN VOUT NMOS PMOS (LOAD)


(DRIVER)
VOL ~ VOH CUTT OFF LINEAR
VIN
VIL VOH SATURATION LINEAR
VTH VTH SATURATION SATURATION
VIH VOL LINEAR SATURATION
VOH VOL LINEAR CUTT OFF

Figure 3: CMOS inverter layout

Shanti Institute of Technology, Meerut (U.P.) - 250501, India


International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
134 EATHD-2015 Conference Proceeding, 14-15 March, 2015

swing b/w 0 and Vdd, and therefore, the noise margins


are relatively wide. Proper design of W/L ratio is very
important to find the current driving capability of gate
in both directions. Reorganizing yields
√ (1/kr) = (vth-vto, n)/ (vdd+vto,p-vth) (1)

Now solve for Kr that is required to achieving the


given Vth.
Kr=kn/kp= (vdd+vto, p-vth)2/(vth-vto,n)2 .(2)
Figure 4: CMOS inverter Recall that the switching threshold voltage of an ideal
inverter is defined as,
[Note: An integrated circuit usually has MOSFETs with Vth, ideal=1/2 Vdd (3)
different L and W values. To reduce the contact
resistance, it is desirable to maximize the metal contact Substituting (3) in (2) gives
area to the source/drain regions. To optimize optical (Kn/kp) ideal= (0.5vdd+vto,p)2/(0.5vdd-vto,n0)2 (4)
lithography and reactive ion etching steps, it is
preferable to place several identical-size contact holes For a near-ideal CMOS VTC that statics the (3).since
within the S/D regions instead of a single large one.] the operation of the NMOS & the PMOS transistor of
the CMOS INVERTER are fully complement.
(kn/kp) symmetric inverter=1

Note that, the ratio kr is defined as


Kn/kp=µncox. (W/L)N / µPcox. (W/L)P= µn. (w/L) N / µP
(w/L)

Assuming that the gate oxide thickness tox and


hence, the gate gate oxide capacitance Cox have the
same value for both nmos and pmos transistors. The
unity ratio condition for the ideal symmetric invert
requires that
IX. CHANNEL LENGTH MODULATION (W/L)N / (W/L) P= µP / µn =230CM2 V-S /580 CM2 V-S
Hence,

(W/L)p=2.5(W/L)n

Example
Calculate ID and VDS if Kn = 100 μA/V2, Vtn = 0.6
V, and W/L = 3 for transistor M1.The bias state of M1
is not known so we must initially assume one of the
two states, then solve for bias voltages and check for
consistency against that transistor bias condition.
Initially, assume that the transistor is in the saturated
state so that
When W/L ratio is 3.we can say that w=6 µm and
L=2µm then W/L=3
Id = µn Cox/2Tox* W/L (VGS −Vtn)2 = KnW/L
(VGS-Vtn)2
X. TRANSISTOR SIZING = (100 µA) (3) (1.5 − 0.6)2
The inverter threshold voltage vth was identified as one = 243µA
of the most important parameters that characterize the Using Kirchhoff’s Voltage Law (KVL)
steady-state I/O behavior of the CMOS inverter circuit. VDS = VDD − IDR
The CMOS inverter can, by virtue of its complementary = 5 − (243µA) (15 kΩ)
push-pull operating mode, provide a full output voltage =1.355V

Shanti Institute of Technology, Meerut (U.P.) - 250501, India


International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
135 EATHD-2015 Conference Proceeding, 14-15 March, 2015

We assumed that the transistor was in saturation, so W/L α CURRENT α 1/VOLTAGE OR W/L α i α 1/V
we must check the result to see if
That is true. For saturation 1. w=1µm and L=1µm, (EXTRINSIC TYPE CMOS)
VGS < VDS + Vtn
1.5 V <1.355V + 0.6V
So the transistor is in saturation, and our assumption
and answers are correct.

(a) changing the W/L ratio:- w=1µm and l=1µm,


so w/l=1
Id = µn Cox/2Tox* W/L (VGS −Vtn)2 = KnW/L
(VGS-Vtn)2
= (100 µA) (1) (1.5 − 0.6)2
= 81µA
Using Kirchhoff’s Voltage Law (KVL)
VDS = VDD − IDR
= 5 − (81µA) (15 kΩ)
=3.785V

(b) changing the W/L ratio:- w=1µm and


l=0.5µm, so w/l=2
Id = µn Cox/2Tox* W/L (VGS −Vtn) 2 = KnW/L
(VGS-Vtn)2
= (100 µA) (2) (1.5 − 0.6)2
= 162 µA
Using Kirchhoff’s Voltage Law (KVL)
VDS = VDD − IDR
= 5 − (162µA) (15 kΩ)
=2.57V

(c) changing the W/L ratio:- w=0.5µm and


l=1µm, so w/l= 0.5
Id = µn Cox/2Tox* W/L (VGS −Vtn) 2 = KnW/L
(VGS-Vtn)2
= (100 µA) (0.5) (1.5 − 0.6)2
= 40.5 µA
Using Kirchhoff’s Voltage Law (KVL) Figure 5: CMOS inverter with w=1µm and L=1µm
VDS = VDD − IDR
= 5 − (40.5µA) (15 kΩ) 2. When. w=1µm and l= 0.5µm, so w/l=2
=4.3925V

Operation Vds ( vout ) Id (drain


current)
w=0.5µm and 4.3925V 40.5 µA
l=1µm, so w/l=
0.5
w=1µm and 3.785V 81µA
l=1µm, so w/l=1
w=1µm and 2.57V 162 µA
l=0.5µm, so
w/l=2
w=6 µm and 1.355V 243µA
L=2µm then
W/L=3

Shanti Institute of Technology, Meerut (U.P.) - 250501, India


International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
136 EATHD-2015 Conference Proceeding, 14-15 March, 2015

Figure 5: CMOS inverter with w=1µm and l= 0.5µm

3. W=0.5µM AND L=1µM, SO W/L=0.5 Figure 6: CMOS inverter with W=0.5µM AND L=1µM

4. VALUES OF W/L ARE W=6µM AND L=2µM ….


(INTRINSIC TYPE CMOS)

Figure 7: CMOS inverter with W=6µM AND L=2µM

Shanti Institute of Technology, Meerut (U.P.) - 250501, India


International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
137 EATHD-2015 Conference Proceeding, 14-15 March, 2015

XI. CONCLUSION
Let’s we have to study the effective parameter of CMOS
during changing the W/L ratio. W/L is the most effective
parameter, which is the ratio of width/length of the
NMOS or PMOS device. When we change (increase) the
w/l ratio then output voltage (vout) is decrease as well as
drain current (Id) is increase or Visa - versa.

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Shanti Institute of Technology, Meerut (U.P.) - 250501, India