Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Bin Yu, Leland Chang*, Shibly Ahmed, Haihong Wang, Scott Bell, Chih-Yuh Yang, Cyrus Tabery,
Chau Ho, Qi Xiang, Tsu-Jae King*, Jeffrey Bokor*, Chenming Hu*, Ming-Ren Lin, and David Kyser
10.2.1
0-7803-7462-U02/$17.M
02002 IEEE IEDM 251
Device Characteristics reduced vertical electric field in the inversion layer and the
A. Scaling Performance different channel crystal orientation. Both conditions of
Figure 3 is the TEM of a FinFET with a IOnm-long sacrificial oxidation resulted in comparable mobility,
poly-Si gate. Nisi was formed on top of the poly-Si gate suggesting that a clean gate oxide interface can be obtained
electrode. Figure 4 is the TEM of a narrow Si fin etched with a sacrificial oxidation of 50A (Figure 16). The direct
from the SO1 wafer. Figure 5 is the Id-Vd characteristics of tunneling leakage through thin gate oxide (formed on
the 1 Onm gate length CMOS FinFETs. The drive currents sidewalls ofthe etched silicon) in the FinFET is comparable
are 446pAipm for n-channel FinFET and 356pAipm for p- to what was measured in a planar FET with the same gate
channel FinFET, both measured at a gate over-drive of IV oxide physical thickness (Figure 17).
and a Vdd of 1.2V. All the currents are normalized by two C. Gate Delay and CMOS Inverter
times the tin height (i.e., the total channel width of a Figure 18 shows the intrinsic gate delay (CV/I) of the
double-gate device). A large Vdd is selected due to the thick fabricated CMOS FinFETs as compared with that of the
gate oxide used. Figure 6 is the subthreshold Id-V, behavior published planar devices. Gate delays of 0 . 3 4 ~ sfor n-FET
for the same devices. In this experiment the threshold and 0 . 4 3 ~ sfor p-FET, respectively, were achieved for the
voltages are shifted from the desired values due to the use lOnm gate length FinFETs at Vdd=1.2V. Figure 19 is the
of poly-Si gate and lightly doped channels. The threshold schematic layout of a FinFET CMOS inverter with
voltage can be fixed by proper channel implant and/or using multiple-fin device configuration. Figure 20 is the voltage
alternative gate materials with appropriate workfunction. transfer characteristic measured from the fabricated CMOS
Figure 7 is the gate C-V characteristics measured from a FinFET inverter at a supply voltage of IV.
multiple-fin device with large gate area (1Ox10pm').
At lOnm gate length, the sub-threshold slopes are Summary
125mVidec for n-channel FinFET and IOlmVidec for p- Double-gate CMOS FinFETs were fabricated with the
channel FinFET, respectively. The DIBL's are 7 l m V N for smallest physical gate length ever reported. With the
n-channel FinFET and I20mVIV for p-channel FinFET, demonstrated scalability and potential performance benefit
respectively. Despite the relatively thick fin body used (under the penalty of adding some fabrication complexity to
(17-26nm), the good short-channel performance is the existing planar process), the FinFET would be a strong
observed because of the dual gate control and the competitor or successor to classical CMOS. While a few
significant grading of the sourceidrain junction. A largely non-show-stopper issues (e.g., gate material engineering
graded sourceidrain junction helps reducing the electrical and parasitics reduction) need to be addressed, the FinFET
coupling from the drain biasing, relaxing the strict is promising for the extremely scaled CMOS in which the
requirement on fin width scaling. Figure 8 shows the sub- packing density, scalability, performance, and power
threshold slopes and DIBL's measured from a group of dissipation would be among the vital challenges.
F i n F E T s with different gate lengths but the same tin width.
Table-I summarizes the short-channel effects of several Acknowledgment
recently published FinFETs from different sources. The authors would like to appreciate technical supports
B. Parasftics and Carrier Transport from STG/APD/SDC at AMD. The research collaboration
Figure 9 is the TEM of a 12nm-wide silicon fin between AMD and the University of California at Berkeley
(patterned by optical lithography). The fin aspect ratio is has been through the SRC customized research program.
determined by circuit design and fabrication considerations
as illustrated in Figure IO. The short-channel performance References
of the FinFET could be further improved by reducing the X. Huang, W:C. Lee, C. Kuo, D. Hisamato, L. Chang, cl al. "Sub-
tin width. However, this introduces a large parasitic 50nm FinFET: PMOS." IEDM Tech. Dig.. Dec. 1999, pp. 67-70.
D. Hiramato, W.-C. Lee, I. Kedzierski. E. Anderson, H. Takeuchi.et
sourceldrain resistance, degrading the device drive current. al, "A folded-channel MOSFET for deep-sub-tenth micron era."
With a wide fin (hence less parasitics), FinFETs with longer IEDM Tech. Dig., Dec. 1998, pp. 1032-1034.
channel show good DC performance (Figure 11-12), In N. Linden, Y:K. Choi, L. Chang, E. Anderson, W:C. Lee, et al.
particular, the peak transconductance (at Vdd =1.2V) of the "Quasi-planar NMOS FinFETs with sub-100nm gale lengths,"
Device Research Conference, June 2001, pp.26-27.
p-channel FinFET is very high (633pSipm) measured from D.M. Fried,A.P. Johnson, E.J. Nowak, J.H. Rankin,C.R. Willets,"A
a device with 105nm gate length (Figure 13), which is sub40nm body thickness n-type FinFET," Device Research
consistent with the large hole mobility observed. While the Conference, June 2001, pp. 24-25.
electron mobility in a (1 IO) FinFET channel is decreased as Y:K. Choi, N. Linden, P. Xuan, S. Tang, D. Ha, E. Anderson. et al.
"Sub-2Onm CMOS FinFET technologies," IEDM Tech. Dig., Dec.
compared with that in a (100) channel (conventional planar 2001. pp. 421424.
FET) (Figure 14), the hole mobility in a (110) FinFET J. Kedzierski, D.M. Dried. E.J. Nowak, T.Kananky, J.H. Rankin, et
channel is remarkably improved from that in a (100) al, "High-performance symmetric-gate and CMOS-compatible VI
channel (Figure 15). Hole mobility in a p-channel FinFET asymmetric-gate FinFET devices,'' IEDM Tech. Dig., Dec. 2001, pp.
437440.
is roughly 100% higher than that in a planar FET (measured F:L. Yang, H.Y. Chen, F:C. Chen,Y.-L. Chan, et al,"35nmCMOS
at the same gate overdrive of 0 . W ) due to the significantly FinFETs," Symp. VLSl Tech., June2001, pp. 104-105.
10.2.2
252-lEDM
hoto resist Si02 cap Gate msi
\
Tz1
a
22OA Si02 cap
,
.........!z
.......................
; ......... .;: p a p ,+.;:......................
..........................
:
,
:
g.....
atesoi ' ........ :.. ..
:,.. ....:,. :.;:,.,:.
~
L/
I -
..:. Fig2 Layout of FinFET with single fin structure. Fig.3 Cross-sectionTEM of lOnm polysiiimn gate
with Nisi formed on top.
I - . - 500, I
im
I 7 L
.^^
4""
1 p-FinFET 1 n-FinFET A
4
2c
I
300
??
5 200
0
E
0
100
(9)
I.L
'BOX
- ...
- .--
I -12 -08 -04 00 04 08 12
rKl
3160 160
1 P-FinFET I N-FinFET I v
m
7E 120
Square: n-FinFET
Circle: pFinFf3 120
Tfin = 17-26nm
mn
0
m 80 80 g.
z0 -1
Area = l o o p 2
c m
pFinFET
0.4
0 0-2 -1 0 1 2 $ 40 40
52
0 7 0 0
0 20 40 60 80 100
Gate Voltage (v) Gate Voltage (V)
Gate Length (nm)
Fig.6 Subthreshold Id-Vg behavior of l0nm gale Fig.7 Gate C-V CuNes of FinFET (Tox(phys)=17A). Fig.8 Sholl-channeleffects of CMOS FinFET.
length CMOS FinFET transiston.
10.2.3
IEDM 253
1wO
800
600
4w
-
200
I
BOX -4 I+ 12nm c
-1.0 0.5 0.0 0.5 1.0
Drain VoitaaeM _ I ,
Fig.9 12nrn wide fin patterned by optical lithcgraphy. Fig.10 Fin height is determined by process and circuit Fig.11 Longchannel FinFET Id-Vd characteristics.
desgn mnsiderations.
l"M ,
l0O0
s
I
(1 IO)Takagi '94
--
-6
-(110) Measured
j ,r---;
%
-
._
.-
5w-
I I)
.. .. i
.' ; ..
C N-FinFET E
'",
Tfin=46nm . . m
.. . . 0
5 -1 0 -0.5 0.0 0.5 1.0 1.5 0.0 0.2 0.4 0.6
~ ~~ ~~
Fig.12 LongIhannel FinFET subthreshold behavior. Fig.13 Longchannel FinFET transmnductance Fig.14 Electron mbility is reduced as the channel
measured at IVdI=I.ZV. orientation ischanged frorn(100)to(ll0)direction
0 0 0 ,
= 1w
0 50Asacox
I 0 ~OOAS~COX
Capacitor oxide
m
0.0 0.2 0.4 0.6 0.0 0.2 -1 0 1
........................................
Wp: Wn ; P-FinFET
10: 5fins
Vin
0.1
10 1w
Input Voltage (v)
Physical G a t e Length (nm) GND
Fig.18 Gate intrinsic delay (CVA) of FinFET mmpared Fig.19 CMOS inverter made by FinFET wivl multiple- Fig.20 Voltage transfer characteristicsof CMOS
with published planar CMOS transistors. fin mnfguration. FinFET inverter at a supply voltage of 1V.
10.2.4
254-IEDM