15-3

Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As

Complimentary Heterojunction Vertical Tunnel FETs for Ultra-Low Power Logic
R. Pandey1, H. Madan1, H. Liu1, V. Chobpattana2, M. Barth1, B. Rajamohanan1, M. J. Hollander1, T. Clark1, K. Wang1, J- H.
Kim3, D. Gundlach3, K. P. Cheung3, J. Suehle3, R. Engel-Herbert1, S. Stemmer2 and S. Datta1
1
The Pennsylvania State University, University Park, PA 16802, USA; 2University of California, Santa Barbara, CA 93106, USA;
3
National Institute of Standards and Technology (NIST), MD, USA; Email: rop5090@psu.edu
Abstract: Extremely scaled high-k gate dielectrics with high qual-
ity electrical interfaces with arsenide (As) and antimonide (Sb)
channels are used to demonstrate complimentary ‘all III-V’ Het-
erojunction Vertical Tunnel FET (HVTFET) with record perfor-
mance at |VDS|=0.5V. The p-type TFET (PTFET) has ION
=30µA/µm and ION/IOFF =105, whereas the n-type TFET (NTFET)
has ION =275µA/µm and ION/IOFF=3×105, respectively. NTFET
shows 55mV/decade switching slope (SS) while PTFET shows
115mV/decade SS in pulsed mode measurement. Vertical TFET
offers 77% higher effective drive strength than Si-FinFET for
given inverter standard cell area. Energy-delay performance of
TFET shows gain over CMOS for low VDD logic applications.
Introduction: TFETs are promising devices for realization of
transistors with sub-kT/q switching slope. Heterojunction TFET
using mixed arsenide-antimonide materials can achieve high on-
current (ION), high ION/IOFF ratio, through source-side tunnel bar-
rier height (Eb,eff) engineering. To implement energy-efficient
complementary logic, both NTFETs and PTFETs need to be real-
ized preferably in the same material system. Here, for the first time,
we demonstrate complementary TFETs with high on-current, high
ION/IOFF in arsenide-antimonide material sharing the same meta-
morphic buffer layer. We demonstrate sub-kT/q switching slope
(SS) for NTFETs. The advantages of complimentary HVTFET-
based FO1 inverter over FinFET FO1 inverter are quantified from
circuit layout and energy-delay performance perspective.
Fabrication: Fig. 1(a) illustrates the schematic of complimentary
HVTFETs sharing a common metamorphic buffer. Figs. 1(b) and
(c) depict the epitaxial hetero-structures and the cross-sectional
TEM micrographs of N and PTFETs, respectively. The TFET fab-
rication process flow is outlined in Fig. 2. Due to the differences
in channel composition (As vs. Sb), NTFET and PTFET employ
separately optimized ZrO2 and HfO2 gate stacks, respectively.
Gate Stack Development: A primary bottleneck for steep slope
III-V TFETs has been development of high-k dielectric/III-V
channel interface with low interface trap density (Dit) and low
leakage current. Particularly, in the case of antimonide (Sb) chan-
nel PTFET, the surface Fermi level movement is typically re-
stricted due to high mid-gap Dit. For PTFET with GaAs0.35Sb0.65
channel, we achieve the highest accumulation capacitance density
(Cacc) with a high temperature (250oC) plasma clean due to effi-
cient desorption of native oxide, albeit with formation of elemental
Sb which worsens Dit [1] (Fig. 3(a)). Optimization of the H2
plasma surface clean temperature with 3.5 nm thick HfO2 gate di-
electric leads to the thinnest CET ~1.2 nm (capacitance equivalent
thickness) with lowest mid-gap Dit (Figs. 3(b,c)). We achieve ef-
ficient Fermi level movement between valence band and the mid-
gap but sluggish movement away from mid-gap, as observed from
the normalized conductance maps in Fig. 3(d). For NTFET with
In0.65Ga0.35As channel we employ 4nm thick ZrO2 high-k dielectric
(Fig. 4(a-c)) and achieve CET of 1.1 nm [2] with low mid-gap Dit.
The conductance peak maximum trace indicates efficient Fermi
level movement with gate voltage. The dual gate stack approach
is essential for realizing complimentary TFETs with high on-cur-
rent, steep switching slope and high ION/IOFF ratio.
DC and Pulsed I-V Characterization: Experimental room tem-
perature transfer (IDS-VGS), switching (SS-IDS) and output charac-
teristics (IDS-VDS) for the fabricated PTFET and NTFET are shown
in Fig. 5(a-c) and Fig. 5(e-g), respectively. GaAs0.35Sb0.65 channel
PTFETs exhibit ION =30µA/µm at ION/IOFF =105. The PTFET out-
put characteristics exhibit negative differential resistance (NDR)
and saturation at low temperature (77K, Fig. 5(d)) due to the sup-
pression of mid-gap Dit response. In0.65Ga0.35As channel NTFET
shows ION =275µA/µm at ION/IOFF=3×105. The mid-gap Dit with
slow trap response time causes the DC switching slope (SS) in the
fabricated N and PTFETs to exceed the thermal limit of 60
mV/decade at room temperature. We perform pulsed IDS-VGS
measurements on TFETs with input gate voltage pulse with rise
time varying from 10µs down to 300 ns to evaluate SS under actual
switching environment. Fig. 6(a-d) shows the improvement in
switching characteristics for both N and PTFET due to suppressed
response of slow mid-gap Dit. We achieve SS=55mV/decade for
NTFET and SS=115mV/decade for PTFET at room temperature.
The high ION with sub-kT/q SS demonstration for NTFET and high
ION with improved SS demonstration in case of PTFET, is a direct
consequence of engineering high-quality scaled gate dielectrics
and tunnel barriers in the As-Sb system.
Complementary HVTFET vs. FinFET Benchmarking: Fabri-
cated HVTFETs are benchmarked against published results in Fig.
7. Previous PTFETs utilize Si/SOI/SiGe materials and some
achieve sub-kT/q SS albeit with poor ION [3,4]. Sb-channel PTFET
presented in this work shows superior performance and, in con-
junction with As-channel NTFET demonstrates the potential of
III-V complimentary TFET logic. Figs. 8(a-e) show 9-metal-track
based standard cell layout for an FO1 inverter using FinFETs and
VHTFETs. FinFET device width set by the maximum number of
fins (e.g. 4 for a 9-metal-track standard cell) provides an effective
drive strength improvement of 13% for an inverter (INV1) (2*Hfin/
fin-pitch) over a planar MOSFET, assuming a fin-pitch of 60 nm
and fin height Hfin of 34 nm at 22 nm node (Fig. 8(f)) [10]. For the
same layout area, VHTFET improves the effective drive strength
by 100% over planar MOSFET, benefiting from the double mesa
edge gate structure. Fig.9 (a) shows the transfer characteristics of
complimentary VHTFETs, calibrated using experimental results
in this work, and benchmark against 22nm Si FinFETs. Assuming
lower Dit than the experimental values, we obtain steep SS ~40
mV/decade for both P and NTFETs. Fig. 9(b) shows the energy-
delay evaluation of a fan-out=1 (FO1) inverter, where TFETs
show improved energy efficiency for below 0.3V applications.
Conclusions: Complimentary ‘all III-V’ heterojunction vertical
Tunnel FET (TFET) with record ION, ION/IOFF and SS performance
are demonstrated at |VDS| = 0.5V. This work shows the feasibility
of Tunnel FETs for low VDD applications beyond FinFETs.
References: [1] A. Ali et al., APL, Oct. 2010 [2] V. Chobpattana
et al., APL, May 2014 [3] R. Gandhi et al., EDL, Nov. 2011 [4] K.
Jeon et al., VLSI 2010 [5] L. Knoll et al., EDL, June 2013 [6] G.
Dewey et al., IEDM 2011 [7] M. Noguchi et al., IEDM 2013 [8]
Bijesh et al., EDL 2014 [9] A. C. Seabaugh, Proc. IEEE Dec 2010
[10] C.-H. Jan et al., IEDM 2012

T206 978-4-86348-501-3 2015 Symposium on VLSI Technology Digest of Technical Papers

 I. Complimentary III-V TFET Structure Detail
(a) (b) PTFET NTFET
(c)
200nm In Ga As
400nm In0.7Ga0.3As 0.65 0.35 PTFET NTFET
N+ (Si-5X1019 cm-3) N+ (Si-1018 cm-3)
200nm GaAs0.35Sb0.65 150nm In0.65Ga0.35As
Intrinsic Intrinsic
500nm GaAs0.35Sb0.65 10nm GaAs0.4Sb0.6
P+ (C-1019 cm-3) P++ (C-1020 cm-3)
100nm Al0.3In0.7As 300nm GaAs0.4Sb0.6
Buffer P+ (C-5X1019 cm-3)
Al1-XInXAs linear Al1-XInXAs linear
grade relaxed buffer grade relaxed buffer
InP Substrate InP Substrate

Fig. 1. (a) Schematic of complimentary PTFET and NTFET on common metamorphic buffer technology; (b) Starting hetero-structures, and (c) Cross-section TEMs
TFET Process flow II. Process Details Gate Dielectric Deposition Steps  III. Scaled PTFET Gate Stack: CET of 1.2 nm on p-GaAsSb
o Mo Sputter. Ti/Cr etch mask formation PTFET
o MESA dry etch, wet etch undercut o Ex‐situ 40s (1:1) HCl:H2O wet etch  4 H2 Plasma clean 4 1015
2
Normalized Gp/ [/cm /eV]
150oC surface clean EV EC 6
o Gate Dielectric Deposition o In‐situ 1.5 min H2 plasma at 150oC
(d)
1.0E+11
Temperature optimization
(c)

Capacitance Density [F/cm2]

1.5 min H2 Plasma

Capacitance Density [F/cm2]

5.0E+12
o Ni (Thermal Evap.) gate deposition o 3.5 nm HfO2 ALD at 250oC 250oC FGA @350oC
1.0E+13
1.5E+13
o Source contact definition (Ti/Pd/Au)  o 20 min FGA [65% Ar, 35% H2] at 350oC 3 3 2.0E+13
110oC 2.5E+13
o ILD (BCB) planarization and etch back NTFET [2] 150oC 5 3.0E+13

Log10 (f [Hz])
Dit [ev-1cm-2]
3.5E+13
1014 10-1
o Drain pad definition (Ti/Pd/Au) o Ex‐situ 3 min BOE  4.0E+13

o Selectively dry etch ILD to form  o In‐situ 9 cycles N2 /TMA at 300oC

2
(a) 2 (b) 10-2
10-3
4.5E+13
5.0E+13
5.5E+13

JG [A/cm2]
Gate/Source Via  o 4 nm ZrO2 ALD at 300oC 10-4 6.0E+13
6.5E+13
10-5 4
o Gate, Source pad definition (Ti/Pd/Au) o 15 min FGA [95% N2,  5% H2] at 400oC 10-6
7.0E+13
1 1 10 KHz to 1MHz 7.5E+13
8.0E+13
10-7
Fig. 2. Process flow details for vertical TFET 10 13
10-8 -1 0 1
8.5E+13
9.0E+13
9.5E+13
70 KHz to 1MHz Gate Voltage [V] 1.0E+14
IV. NTFET Gate Stack [2]: CET 1.1 nm on n-InGaAs 0
-1 0 1 2
0
-1 0 1 2 -0.4 -0.2 0.0 0.2 0.4 0.6
3
0.0 0.5 1.0 1.5 2.0
1014 Gate Voltage [V] Gate Voltage [V] Band Bending [eV] Gate Voltage [V]
4 EV Normalized Gp/ [/cm /eV]
2

(b) EC
Fig. 3. (a) CV characteristics of p-type GaAs0.35Sb0.65 MOSCAPs with 3.5 nm HfO2 with H2 plasma
Capacitance Density [F/cm2]

o
300 C surface-clean 6
9 cycles N2/TMA 1.0E+11

(c) surface clean at various temperatures; (b) CV characteristics of optimized gate stack; (c) Dit extraction
5.0E+11
o 1.0E+12
3 FGA @400 C 1.5E+12
2.0E+12
10-1
3nm 5
2.5E+12
3.0E+12 using Terman method. Gate leakage is shown in the inset; (d) Normalized parallel conductance plot
(a) 10-2
13 3.5E+12
Dit [ev-1cm-2]

10
with dotted line trace showing movement of the conductance peak maximum.
Log10 (f [Hz])

4nm 4.0E+12
2 10-3 4.5E+12
JG [A/cm2]

5.0E+12
10-4 5.5E+12

V. DC I-V Characterization
6.0E+12
10-5 6.5E+12
4 7.0E+12
1
10-6
10-7 ZrO2
7.5E+12
8.0E+12
102
PTFET 300
Switching Slope [mV/dec.]
8.5E+12
10
Drain Current [A/m]

NS= 51019 cm-3

Drain Current [A/m]

1012 10-8 9.0E+12
VDS = -0.05 V T=77K
-1 0 1 T = 300K

Drain Current [A/m]

9.5E+12

10 KHz to 1MHz Gate Voltage [V] 1.0E+13

1.1E+13
101 LG= 200 nm
0 3 30 VGS = -0.5
-1 0 1 -0.6 -0.4 -0.2 0.0 -2.0 -1.5 -1.0 -0.5 0.0 10 0
T= 300K 200 VGS = -0.5 to -1.5 V
Gate Voltage [V] Band Bending [eV] Gate Voltage [V]
171 mV/dec.
to -1.5 V
10-1 20
Fig. 4. (a) CV characteristics of n-type In0.53Ga0.47As MOSCAPs (a) (b) (c)
5
10-2 100 (d)
with 4nm ZrO2 with N2 plasma/TMA clean [2]; (b) Dit extraction 10-3
VDS= -0.05,-0.5 V 60 mV/dec. 10
using Terman method. Gate leakage for both 3nm and 4nm ALD 10-4
T=300K
0 0 0
ZrO2 is shown in the inset; (c) Normalized parallel conductance -2 -1 0 1 10-3 10-2 10-1 -1.0 -0.5 0.0 0.5 -1.0 -0.5 0.0 0.5
Gate Voltage [V] Drain Current [A/m] Drain Voltage [V] Drain Voltage [V]
plots for 4nm ZrO2. Dotted line trace shows the movement of
conductance peak maximum. NTFET 200 60
60
Switching Slope [mV/dec.]
Drain Current [A/m]

102 LG=150 nm VDS = 0.05 V T = 77K

VI. Pulsed I-V Characterization

Drain Current [A/m]

T = 300K
Drain Current [A/m]

10 1 101 T=300K 150 VGS=0.5 V to 1.0 V VGS=0.5 V to 1.0 V

NS=81018cm-3
250
100 40 (g) 40
Drain Current [A/m]

Switching Slope [mV/dec.]

100 VDS= -0.5V 200

DC
10-1 (e) 100 102 mV/dec (f) (h)
10s 20
PTFET (a) 150 1s
(b) 10-2
50 60 mV/dec
20
10-1 T=300K
10-3 VDS=0.05V,0.5V T=300K
T=300K 100 115mV/dec. 10-4 0 0 0
10 -2 60 mV/dec. -0.5 0.0 0.5 1.0 1.5 10-3 10-2 10-1 100 -0.5 0.0 0.5 -0.5 0.0 0.5
DC, 10s, 1s 50 Gate Voltage [V] Drain Current [A/m] Drain Voltage [V] Drain Voltage [V]
VDS= -0.5V NS=81018cm-3
10-1.5 -3 (Gate Pulse)
0
Fig. 5. DC Transfer, Switching and Output characteristics of (a-d) PTFET and (e-h) NTFET. All meas-
-1.0 -0.5 0.0
Gate Voltage [V]
10-2 10-1
Drain Current [A/m] urements are at T=300K, except the additional T=77K data in (d) and (h). NDR is visible in PTFET
250 output characteristics at T=77K, due to the suppression of trap response. NS denotes PTFET source
102 VDS= 0.5V
Switching Slope [mV/dec.]

T=300K
VDS= 0.5V doping concentration.
Drain Current [A/m]

101 T=300K 200

104
NTFET 150
VIII. TFET Inverter layout and Performance Benchmark (a) Lg=20nm,EOT=0.5nm
Tb=7nm,IOFF=5×10-4uA/um
100 103
Drain Current IDS (A/m)

(c) DC (d) (c)Cell Layout Design

9‐Track Standard 
(d) (e) HTFET INV1
22nm Si FinFET 22nm Si FinFET
(a) Vertical PTFET
2
1s Si FinFET INV1 10
10-1 100 Metal N-HTFET
300ns 40mV/dec
60 mV/dec. Source POWER POWER POWER 101 44mV/dec
10-2 50 P-HTFET
DC, 1s, 300ns 55 mV/dec. Gate
100 V =-0.3V,-0.5V VDS=0.3V,0.5V
Side‐Gate
Fin‐Pitch

(Gate Pulse) Drain Gate‐Pitch DS

10-3 0 Dummy Gate
10-1
0.0 0.5 1.0 1.5 10-2 10-1 100 101
Drain Current [A/m] Gate‐ Contact Via GaAs0.35Sb0.65 GaAs0.4Sb0.6
Gate Voltage [V] 10-2
Contact P‐Diffusion  In0.7Ga0.3As In0.65Ga0.35As
Fig. 6. Pulsed mode transfer and switching characteristics Metal‐Pitch IN region 10-3
of (a-b) PTFET and (c-d) NTFET. All measurements at (b) Vertical NTFET
IN OUT OUT Eb,eff=0.4eV (Quantized) Eb,eff=0.45eV (Quantized)
N‐Diffusion 
region 10-4
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8
300K VII. TFET Device Benchmark
Drain Fin Gate Voltage VGS (V)
Source Side‐Gate Cell Boundary
PTFET NTFET 10 1 0.9V HTFET Inverter
Energy per cycle (aJ)

[3] [5] This work This work [6] [7] [8] This Work This work  0.6V Si FinFET Inverter
Gate‐ 0.6V 0.5V
III‐V GND GND GND 0.5V 0.4V 0.3V
Structure SiNW GAA SiNW
III‐V  III‐V [Pulsed I‐V]  Contact 10 0
III‐V III‐V III‐V III‐V  [Pulsed  0.1V
Ns=5X1019cm‐3 Ns=8X1018cm‐3 0.4V 0.2V

VDS [V] ‐0.6 ‐0.5 ‐0.5 ‐0.5 0.3 0.3 0.5 0.5
IV]
0.5 22 nm Planar  22nm FinFET  22nm Vertical
(b) 0.3V
0.2V

(f)
-1
ION Technology 10 0.1V
[µA/µm]
1.8 10 14 10 12 6 109 245 275 MOSFET INV1 INV1 HTFET INV1 1% Switching
Layout Induced Drive Strength  Activity Factor Lg=20nm
IMIN
1.2X10‐6 2.0X10‐6 3.0X10‐4 2X10‐3 1.0X10‐4 2.0X10‐6 2.9X10‐4 1.4X10‐3 1.4X10‐3 1X 1.13X 2X -2
[µA/µm] Enhancement at the same Device Area 10
10-1 100 101 102 103 104 105
1.4X106 5.0X106 4.7X104 5X103 1.2X105 3.0X106 3.8X105 1.8X105 2.0X105 Delay (ps)
ION/IMIN
Fig. 8. Device layout of (a) vertical P-HTFET and (b) vertical N-
SSEff
122 112 161 202 89 85 134 143 132 HTFET; (c) Layout illustration of a 9-metal-track standard cell library Fig. 9. (a) Simulated device character-
[mV/dec.]
SSMin
30 90 171 115 58 64 97 102 55 design. Layout area is determined by 9N×Gate-pitch×9metal-pitch. N istics of the proposed complementary
[mV/dec.]
1.1 1.4 0.7 0.7 0.7 is number of gate-pitches in the lateral direction. Inverter layout of (d) HTFET (b) Energy vs. delay of a FO1
EOT [nm] 4.5 0.7 0.8 0.8

Lg [nm] 140 200 200 200 100 ‐ 150 150 150 Si FinFETs at a maximum fin number of 4 and (e) proposed comple- inverter comparing 22nm Si FinFET
Fig. 7. Benchmark of Si and III-V TFETs. SSEff= (VON- mentary vertical HTFETs; (f) Layout induced device drive strength and HTFET with 1% switching activ-
VMIN)/ (2log (ION/IMIN)) [9]; VON (VMIN) corresponds to the enhancement (effective device width at a given device area) compar- ity factor at different supply voltages.
gate voltage at ION (IMIN). |VON| is limited to 1.5V from ing the INV1 using 22 nm planar MOSFETs, 22 nm FinFETs and 22 Cross-over at 0.3V shows energy effi-
|VMIN|. nm vertical HTFETs ciency advantage of HTFET inverter.

2015 Symposium on VLSI Technology Digest of Technical Papers T207