International Conference on VLSI Design, 2019

List of Accepted Full Papers

ID Title Status
22 A Double Pumped Single-line-cache SRAM Architecture for Ultra-low Energy IoT and Machine Full Paper
Learning Applications
23 An Efficient Design Approach for Implementation of 2 bit Ternary Flash ADC Using Optimized Full Paper
Complementary TFET Devices
28 k-core: Hardware Accelerator for k-mer Generation and Counting used in computational Full Paper
genomics
36 Area efficient & High performance Word line Segmented architecture in 7nm FinFET SRAM Full Paper
compiler
39 Enhanced IIP2 Chopper Stabilized Direct Conversion Mixer Architecture Full Paper
42 Performance Enhancement of Caches in TCMPs using Near Vicinity Prefetcher. Full Paper
43 Scheduling of Dual Supercapacitor for Longer Battery Lifetime in Systems with Power Gating Full Paper
47 Improving Performance of Path Based Equivalence Checker using Counter-example Full Paper
53 Efficient Heap Data Management on Software Managed Manycore Architectures Full Paper
56 IIP3 Improvement in Subthreshold LNAs using Modified Derivative Superposition Technique Full Paper
for IoT Applications
58 A Methodology for SAT-based Electrical Error Debugging during Post-silicon Validation Full Paper
61 High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio Full Paper
64 Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked With Standard 45 Full Paper
nm CMOS Technology for Ternary Logic Applications
65 Low Power Design Technique in Passive Tag to Reduce the EMD Noise for Reliable Full Paper
Communication with Reader
70 SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection Full Paper
84 Perturbation based Workload Augmentation for Comprehensive Functional Safety Analysis Full Paper
86 Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination Full Paper
93 Reducing the Overhead of Stochastic Number Generators Without Increasing Error Full Paper
94 In situ Latency Monitoring for Heterogeneous Real-time Systems Full Paper
97 MAVI: Mobility Assistant for Visually Impaired Using Deep Learning and Cloud Services Full Paper
98 RTL Test Generation on Multi-Core and Many-Core Architectures Full Paper
101 Synthesizing Performance-aware (m,k)-firm Control Execution Patterns under Dropped Samples Full Paper
103 Parallelization of brute-force attack on MD5 hash algorithm in FPGA Full Paper
105 Efficient Post-Silicon Validation of Network-on-Chip using Wireless Links Full Paper
107 Current DAC based -40dB PSRR Configurable Output LDO in BCD Technology Full Paper
110 Modelling and fabrication of mixing in low-cost passive PDMS micromixers Full Paper
117 Optimizing Quantum Circuits for Modular Exponentiation Full Paper
118 Design of Continuous-Flow Lab-on-Chip with 3D Microfluidic Network for Sample Preparation Full Paper
121 Design and Physical Implementation of Array Signal Processor ASIC for Sector Imaging Full Paper
Systems
123 A 75-μW 2.4 GHz Wake-up Receiver in 65-nm CMOS for Neonatal Healthcare Application Full Paper
128 Adaptive Fractional Open Circuit Voltage Method for Maximum Power Point Tracking in a Full Paper
Photovoltaic Panel
133 Modeling and Characterization of VBUS Power Discharge for Embedded Superspeed USB Full Paper
Host/Devices
137 Security Assessment of Microfluidic Fully-Programmable-Valve-Array Biochips Full Paper
151 RSBST: A Rapid Software-based Self-test Methodology for Processor Testing Full Paper
153 A 19.3-24.8 GHz Dual-Slope VCO in 65-nm CMOS for Automotive Radar Applications Full Paper
156 Delay Skew Reduction in IO Glitch Filter Full Paper
162 EdgeCoolingMode: An Agent Based Thermal Management Mechanism for DVFS Enabled Full Paper
Heterogeneous MPSoCs
164 A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration Full Paper
165 Energy Efficient Power Distribution on Many-Core SoC Full Paper
173 UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs Full Paper
174 Low-Complexity Continuous-Flow Memory-Based FFT Architectures for Real-Valued Signals Full Paper
178 Large dynamic range Readout Integrated Circuit for Infrared Detectors Full Paper
186 Low Complexity & Improved Efficiency of Encoded Data Using Peres Half Adder in BWA with Full Paper
Testable Feature
192 A Capacity-Aware Wash Optimization for Contamination Removal in Programmable Full Paper
Microfluidic Biochip Devices
195 Write Variation Aware Non-Volatile Buffers for On-Chip Interconnects Full Paper
201 Analysis and Design of Low Phase Noise LC Oscillator for Sub-mW PLL-Free Biomedical Full Paper
Receivers
209 Machine Learning based Power Efficient Approximate 4:2 Compressors for Imprecise Full Paper
Multipliers
210 Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA Full Paper
212 Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Full Paper
Transistors
213 Insights on anisotropic dissipative quantum transport in n-type Phosphorene MOSFET Full Paper
217 Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis Full Paper
222 Ultra Low Energy Reduced Switching DAC for SAR ADC Full Paper
225 Two-Pattern Delta-IDDQ Test for Recycled IC Detection Full Paper
227 An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Full Paper
Gate MOS Transistors
230 Improved Look-ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits Full Paper
232 An Energy efficient In-Memory Computing Machine-Learning Classifier Scheme Full Paper
234 HEART: A Heterogeneous Energy-Aware Real-Time scheduler Full Paper
235 MOS Varactor RO architectures in Near Threshold Regime using Forward Body Biasing Full Paper
techniques
237 Ultra Low Power Digital Front-End for Single Lead ECG Acquisition Full Paper
241 A Current Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Full Paper
Feed-forward Compensation
244 An Efficient Memory Zeroization Technique Under Side-Channel Attacks Full Paper
246 Linear Approximation and Differential Attacks on Logic Locking Techniques Full Paper
248 The Ramifications of Making Deep Neural Networks Compact Full Paper
264 Novel Randomized & biased Placement For FPGA Based Robust Random Number Generator Full Paper
with Enhanced Uniqueness
268 Write Variation aware Cache Partitioning for improved lifetime in Non-Volatile Caches Full Paper
274 Multidimensional Grid Aware Address Prediction for GPGPU Full Paper
281 Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications Full Paper
283 Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Full Paper
Periphery VDD Collapse in SRAMs
286 Structural and Behavioural Facets of Digital Microfluidic Biochips with Hexagonal-Electrode- Full Paper
based Array
287 Parasitic-Aware Automatic Analog CMOS Circuit Design Environment Full Paper
288 VLSI Architectures for Jacobi Symbol Computation Full Paper
294 Ultra Low Power Low Frequency On-Chip Oscillator for Elapsed Time Counter Full Paper
297 Test Configuration Generation for different FPGA Architectures for Application Independent Full Paper
Testing
300 Majority Logic: Prime Implicants and n-input Majority Term Equivalence Full Paper
302 On-chip MISR compaction technique to reduce diagnostic effort and test time Full Paper
305 Investigation of Unified emerging-NVM SoC Architecture for IoT-WSN Applications Full Paper
307 Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays Full Paper
310 Design of an optimized CMOS ELM accelerator Full Paper
313 RiverOpt: A Multiobjective Optimization Framework based on Modified River Formation Full Paper
Dynamics Heuristic
321 A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Full Paper
Algorithm-Architecture Co-design
323 Applying Modified Householder Transform to Kalman Filter Full Paper
324 Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop Full Paper
325 A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits Full Paper
327 A Mismatch Resilient 16-bit 20 MS/s Pipelined ADC Full Paper
 List of Accepted Interactive Presentations (IP)
ID Title Status
8 A simple Synthesis Process for Combinational QCA Circuits: QSynthesizer IP (Poster)
26 WCET-Aware Stack Frame Management of Embedded Systems using Scratchpad Memories IP (Poster)
33 A Machine Learning Based Approach to Predict Power Efficiency of S-boxes IP (Poster)
50 On chip RF to DC power converter for biomedical applications IP (Poster)
55 Self-Organizing Maps-based Flexible and High-Speed Packet Classification in Software Defined IP (Poster)
Networking
75 Mapping of Boolean Logic Functions onto 3D Memristor Crossbar IP (Poster)
76 Design and Implementation of Threshold Logic Functions using Memristors IP (Poster)
83 RF and RFID based Object Identification and Navigation system for the Visually Impaired IP (Poster)
87 Design and analysis of a minimally invasive and ECG controlled Ventricular Assistive Device IP (Poster)
88 Continuous Transparent Mobile Device Touchscreen Soft Keyboard Biometric Authentication IP (Poster)
134 Intelligent Scheduling of Smart Appliances in Energy Efficient Buildings: A Practical Approach IP (Poster)
139 Comparative Study of Analog Matching Structures in 28FDSOI IP (Poster)
175 A Model of Spurs for ∆Σ Fractional PLLs IP (Poster)
187 Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process IP (Poster)
189 Exploiting Negative Control Lines and Nearest neighbor for Improved Comparator Design IP (Poster)
190 Design and Implementation of Low-power High-throughput PRNGs for Security Applications IP (Poster)
206 A Transimpedance Amplifier with Improved PSRR at High Frequencies for EMI Robustness IP (Poster)
208 Realizing Boolean functions using Probabilistic Spin Logic (PSL) IP (Poster)
211 Energy Efficient Communication with Lossless Data Encoding for Swarm Robot Coordination IP (Poster)
224 A 0.8V VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology using IP (Poster)
Repeated-Pulse Wordline Suppression Scheme
242 Stability Analysis of SRAM designed using In$_{0.53}$Ga$_{0.47}$As nFinFET with underlap IP (Poster)
region
249 Hardware Trojan Detection by Stimulating Transitions in Rare Nets IP (Poster)
263 Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications IP (Poster)
272 Reconfigurable Digital Logic Gate based on Neuromorphic Approach IP (Poster)
278 Multi-Application based Network-on-Chip Design for Mesh-of-Tree topology using Global IP (Poster)
Mapping and Reconfigurable Architecture
289 An Enhanced Artificial Bee Colony Algorithm and Automatic Analog CMOS Circuit Design IP (Poster)
298 Current Collapse reduction technique using N-doped buffer layer into the bulk region of a Gate IP (Poster)
Injection Transistor
312 Extending STL basic operators used in 3GPP codecs to leverage features of modern DSP IP (Poster)
architectures