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FPGA Implementation of an IF Sampled FM Receiver

Conference Paper · December 2004

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 FPGA Implementation of an IF Sampled FM Receiver

Benjamin Egg fred harris Chris Dick

San Diego State University CUBIC Signal Processing Chair DSP Chief Architect
San Diego College of Engineering Signal Processing Group
CA 92182 San Diego State University Xilinx
San Diego CA 95124
CA 92182

Abstract: This paper describes the hardware and
digital signal processing algorithms applied to the task
of implementing an FPGA-based commercial FM band
receiver. Analog signal conditioning is limited to a sin-
gle band pass filter, a programmable gain amplifier
and high speed analog-to-digital converter. The re-
maining signal processing required of the radio, such
as spectral translation, channel filtering, FM demodula-
tion, and stereo separation, are performed in the digital
domain using signal processing techniques imple-
mented on the FPGA. We describe how multirate sig-
nal processing techniques are applied efficiently to
perform the required processing tasks.
1 Introduction
This paper documents a case study on the FPGA im-
plementation of an FM receiver. One requirement of
the implementation is to minimize the content of ana-
log signal processing employed in the system. To this
end, the analog processing is limited to a single band-
pass filter, programmable gain amplifier and a high-
speed analog-to-digital converter (ADC).
The paper is organized as follows. Since our objective
is to demodulate commercial FM broadcasts, we start
by describing the frequency floorplan of the commer-
cial FM band. Next, the receiver architecture is de-
fined. The signal processing datapath that performs
channelization, automatic gain control (AGC), de-
modulation and stereo separation is then described.
Finally, conclusions are drawn

Field programmable gate arrays (FPGAs) [5][6][7] are

being increasingly employed in digital communication
equipment. These devices have been successfully
used for some years now to resource the demanding
arithmetic requirements of the signal processing func-
tions used in, for example, a digital radio physical layer
sub-system. FPGAs are commonly used for digital up-
and down-conversion, spectrum channelization using
polyphase transform filter banks, various types of
modulation and demodulation, adaptive equalization,
and for space-time coding. They are also used for
baseband processing in many systems, implementing
a range of channel coding functions that span common
concatenated codes through to high-data rate (>100
Mbps) advanced Turbo convolutional codes (TCC),
Turbo product codes (TPC) and low density parity
check codes (LDPC).
2 The FM Radio Band
In the United States, the FM radio band spans 88.1 to
108.1 MHz. Channels occupying this band are allo-
cated 200 KHz bandwidth. Standard practice assigns
adjacent frequency channels to different geographical
locations to simplify the task of separating neighboring
channels. If a given location has a channel centered at
90.1 MHz, then in this region, the nearest channels are
separated by at least 400 kHz. In heavily populated
areas, in the spectral sense, it may not be possible to
sustain this frequency staggering, and the 200 kHz
bandwidth requirement may need to be strictly en-
forced. Each channel must be sufficiently attenuated at
its band edges as to not interfere with neighboring
channels.

In many application spaces there are requirements for The next section in the paper describes our intermedi-
highly flexible radio systems that can accommodate ate-frequency (IF) sampled receiver architecture that
many tens of waveforms. For example, many of the performs channel access without the need of an ana-
radios in the joint tactical radio system (JTRS) [1] suite log heterodyne to down convert the spectrum to base-
of systems must support wideband OFDM-based band.
modulation, narrowband quadrature amplitude modu-
lation (QAM), right through to ubiquitous non-coherent
frequency modulation (FM), in addition to many other
waveforms. There are a number of references in the
literature that report on the FPGA implementation of
narrowband [2][3] and multicarrier OFDM systems [4].
3 Radio System
3.1 Receiver Architecture

Current generation communication systems tend to

digitize early in the signal flow path. The earlier a sig-
nal is digitized, the less susceptible it is to impairments Figure 3. Receiver architecture with digitization at RF.
introduced by analog variants that degrade signal in-
tegrity. In particular, analog quadrature mixers intro-
duce gain and phase imbalances that vary as a func-
tion of time and temperature. Analog systems can only
achieve balance within 1%, a level insufficient for high
performance radio systems. First generation digital
radios operate at a low sample rate and digitize a
down converted and baseband filtered signal as
shown in Figure 1. Figure 2 is a second generation
architecture with the sampling process relocated from
baseband to the IF strip. The (analog) down-converted
signal is digitized with the final channel selection per-
formed in the digital domain using a digital down-
converter (DDC). In third generation radios like that
illustrated Figure 3, the sampler is located as close as
possible to the antenna. There are minimal analog
components employed in the system with all of the
processing being performed by more cost effective
digital techniques.

Analog Analog Analog Digital

Image Reject Analog Analog Mixers Low Pass Base Band
Band Pass Mixer Band Pass
ADC
Base
A Band
Proc
ADC Figure 4. RF-sampled receiver card.
RF IF
VCO π/2 fs
Tune
Osc
Clock 3.2 Analog Front-End

The hardware platform constructed for this project is

shown in Figure 3. The antenna output is first condi-
Figure 1. Early generation receiver employing analog down- tioned by an analog anti-aliasing filter. This 5-pole el-
conversion and baseband sampling.
liptic filter is designed to attenuate all frequencies out-
side the FM spectrum of 88.1 to 108.1 MHz by 60 dB.
Analog Digital Digital Digital Following the analog filter is a series cascade of digi-
Image Reject Analog Analog Multipliers Low Pass Base Band
Band Pass Mixer Band Pass tally controlled amplifiers that provide gain to ensure
Base
that the full dynamic range of an 8-bit, 80 MSample/s
A ADC k:1 Band analog-to-digital converter is utilized. The digitized
Proc
K fs
data is supplied directly to the FPGA that performs all
RF IF the digital signal processing. Additional inputs to the
VCO Clock
π/2
Tune FPGA are 4 user I/O switches that control the signal
DDS gain from the antenna and provide FM channel selec-
tion. Several status light emitting diodes (LEDs) dis-
play channel number and the analog AGC gain setting.
Two digital-to-analog (DACs) convert the demodulated
Figure 2. IF sampled receiver – one or two stages of analog data to a stereo output audio signal. A liquid crystal
down-conversion followed by digitization and digital down
display (LCD) is provided to visualize the spectrum of
conversion are typically employed in these designs.
the FM band or to observe the spectrum of a single
FM channel.
3.3 The FPGA Signal Processor
All of the receiver signal processing is performed by a
Xilinx VirtexTM series field programmable gate array
(FPGA) [5]. The FPGA is in fact a massively parallel
processor, some might argue the first commercially
successful massively parallel machine. The vast array
of multipliers (444 in a XC2VP100 [5] device) are eas-
ily deployed to service the concurrent aspects of a
complex signal processing system [8]. Computation is
only one aspect of the problem, storage and band-
width to memory are key factors that define the overall
compute capability of a signal processing system.
Supporting the computational structures implemented
using the multiplier fabric and logic cell array [5] is a
highly parallel memory sub-system. Associated with
each multiplier on the device is an 18x18 kbit dual port
memory structure. Capable of delivering 36 bits of data
on each clock cycle, the theoretical peak memory read
bandwidth of a device running at 300 MHz is
36x444x300e6 = 4.8 Terabits per second.
New generation FPGAs like the Virtex-4 [6] family offer
a domain optimized approach to system design. For
example, the SX variant of the Virtex-4 family is opti-
mized for signal processing. With a high ratio of DSP
processing tiles and memory blocks to logic elements,
the Virtex-4 SX devices provide extremely high per-
formance in a cost effective form factor. Each DSP tile
in a Virtex-4 FPGA implements an 18x18 multiply-
accumulate (MAC) at a rate of 500 MHz. With signifi-
cantly higher DSP bandwidth at much reduced power
consumption of the Virtex-II Pro devices, the SX family
offers unprecedented performance per dollar of any
FPGA on the market.
Our radio card is populated with a Virtex-II XC2V2000
FPGA [7]. This device offers 56 18x18 embedded mul-
tipliers and 10,752 logic slices.
4 Signal Processing Datapath
4.1 Band-pass Sampling
Bandpass sampling is employed in our radio. Using
this approach the ADC sample rate is selected to sup-
port the double sided bandwidth of the input signal. In
this case. The entire 20 MHz FM radio spectrum is to
be digitized, so the sample rate must be at least 40
MHz. If the sampling frequency is carefully selected,
the aliasing caused by under-sampling will cause the
spectrum of interest to alias, or fold, to a new center
frequency close to baseband. A sample rate of 80
MHz was selected for the receiver. Figure 4 depicts
how the radio’s sample rate of 80 MHz causes the
positive frequency spectrum to alias from its center
frequency, f + c = 98.1 MHz to 18.1 MHz. Similarly, the
negative spectrum aliases from -98.1 MHZ to a -18.1
MHz. The controlled aliasing effectively replaces the
analog down-conversion of a standard analog re-
ceiver.
Analog IF Filter Spectrum
First Alias First Alias of Analog Input
....
...
f
-1.25 fs -fs -0.25 fs -0.25 fs 0 0.25 fs 0.75 fs fs 1.25 fs 2.75 fs 2 fs 2.25 fs 2.75 fs
-80 MHz -20 MHz 20 Mhz 80 Mhz 160 MHz
Zeroth
-First +First +Second +Third
Nyquist Zone
Nyquist Zone (Primary Strip)
Nyquist Zone Nyquist Zone Nyquist....
Figure 5. Bandpass sampling the FM radio band. The 80
MHz system sample rate aliases the required spectral region
to baseband.
4.2 Spectrum Channelization
Now that the FM radio band has been spectrally relo-
cated to a low frequency digital IF, the next task is to
isolate the FM radio channel of interest via spectral de-
multiplexing using a channelizer. The de-multiplexed
channel will subsequently be handed off to the FM
discriminator for demodulation.
The bandwidth of a single channel is less than 200
kHz which we choose to sample at a 400 KHz rate.
The higher rate permits a wider transition bandwidth in
the channelizer’s filter, which in turn allows us to de-
sign a digital filter with reduced number of taps. The
input signal sample rate is 80 MHz. However, the out-
put sample rate required to satisfy the Nyquist rate of
the down-sampled channel will be 400 kHz. We can,
and should reduce the sample rate as we reduce the
bandwidth of the signal. The ratio of input to output
sample rates is 80e6/400e6 = 200. The allowable tran-
sition bandwidth of the channelizer filter is 200 kHz.
The length of a FIR filter can be estimated from the
ratio of the sample rate to transition bandwidth, cou-
pled with the required out-of-band attenuation. A 1091-
tap will satisfy these requirements. It is useful to have
a filter length evenly divisible by the sample rate
change of 200 and so a 1200-tap filter was selected.
The increased filter length provides additional attenua-
tion.
The data delivered by the analog-to-digital converter is
heterodyned to baseband via a quadrature mixer. The
complex baseband time series requires two low pass
filters to perform the bandwidth reduction and sample
rate adjustment. Figure 6 shows this aspect of the
datapath. A 200-phase polyphase filter is used to gen- Mixer I/Q Samples
Finite State Machine

erate the filtered 400 kHz complex output time series. Regressor vector Address Coefficient Address

Each filter phase consists of 1200/200 = 6 filter taps.

R0 C0 R1 C1 R2 C2 R3 C3 R4 C4 R5 C5

H0(z)

H1(z)
cos(θ0n) I(n) Rm = Regressor Vector Memory Bank m I/Q Baseband Stream
H2(z)
Cm = Filter Coefficient Memory Bank m

H199(z)
Digitized Figure 7. Polyphase filter architecture – I-channel only. The
Input receiver uses the above structure to process the mixer out-
Data put. A separate filter is used for the I and Q streams. 12
H0(z) FPGA embedded multipliers are deployed in total – 6 each
for the I and Q phases. During each clock cycle an I/Q out-
H1(z) put sample is generated.
-sin(θ0n) Q(n) The FPGA is clocked at the ADC sample rate of 80
H2(z)
MHz. Counting the two multiplications in the mixer, the
arithmetic performance of the channel selection and
H199(z) filtering is

2N × 14
N × 400
N e3 = 1.12e9
Figure 6. Receiver front-end, showing quadrature mixer and
Complex Mixer+Filter MPYs Output Rate
polyphase filter channelizer.

which is in excess of 1 billion operations/second. This

The input heterodyne is straightforward to implement
in the FPGA. The multipliers in Figure 6 map directly to
the embedded multipliers in the FPGA. A simple table
lookup approach is used to generate the heterodyning
signal. Independent 6-tap convolution engines are
used to process the in-phase (I) and quadrature (Q)
mixer outputs. Figure 7 exposes some implementation
details of the polyphase filter. A fully parallel 6-tap filter
is used for each of the I and Q signal phases. This
requires a total of 12 embedded multipliers. The down-
converted input samples are written into block memory
[7]. Each MAC engine, of which there are 6 in each of
the I and Q processors, is allocated its own block
memory storage, so 12 block memories are required in
total. The filter coefficients for each MAC engine are
also stored in block memory. 12 block memories are
used for this purpose – one block being associated
with each of the 12 MAC engines in the complex filter.
Further architecture optimization could actually reduce
the block memory requirements. Considering only one
phase of the filter, on each processing clock cycle, 6
regressor vector values and the corresponding 6 coef-
ficient values are read from memory and supplied to
the 6-MAC filter structure. A total of 200 clock cycles
are employed to produce the final filtered and down-
sampled output sample. A simple combining tree and
accumulator structure is used to sum the outputs of
the 6-MAC processors in each filter.
level of performance is achieved using only a small
fraction of the available FPGA resources.
4.3 Digital AGC
Each selected channel will have varying power levels
due to distance, transmitter power, and other vari-
ables. An automatic-gain-control (AGC) function is
implemented to optimize channel power and ensure
that the full dynamic range of the receiver datapath is
utilized. The digital AGC control signal is obtained by
averaging the instantaneous magnitude M(n) (Eq. (1))
of the complex signal.
M ( n) = I 2 ( n) + Q 2 ( n) (1)
Preferring not to perform the square root function, nor
the squaring operations, a simple linear approximation
provides a close approximation to M(n) with both re-
duced arithmetic complexity and hardware require-
ments. The approximation used in the design is shown
in Eq. (2)
M (n) ≈ 0.915 ⋅ L( n) + 0.415 ⋅ S (n) (2)
where L(n) and S(n) represent the larger and smaller
magnitudes of the complex I/Q sample respectively.
The magnitude error from this magnitude approxima-
tion is less than 5% for a sine wave input.
4.4 FM Demodulation
Demodulating an FM signal is performed as the de-
rivative of the arc-tangent of the ordered pair formed at
the output of the polyphase filter. Rather than perform-
ing the arc-tangent and then performing the derivative,
we can form the derivative directly from the Quadra-
ture components without need for explicitly computing
arc-tangent. This is shown in Eq. (3).
• •
• I (n) Q (n) − Q (n) I (n)
φ ( nT ) = (3)
I (n) 2 + Q (n) 2
•
The resulting value, φ (nT ) , represents the derivative
of the phase of the FM modulated signal, and supplies
the required modulation waveform information. The
hardware implementation of the discriminator is illus-
trated in Figure 8. The derivative filter has an odd
number of weights and the filtering operation per-
formed in the differentiator block provides a valid de-
rivative after of an input sample delay of [N-1]/2 sam-
ples. Due to the filter delay before a valid derivative is
available, the raw input data must also be suitable de-
layed in order to maintain proper time alignment. Pre-
ferring not to perform the divide operation, the de-
nominator of [9], which is a scaling factor, can be ig-
nored if the incoming signal is relatively constant.
I(n-(N-1)/2)
. to form the required 38 kHz reference required to
I(n)
I(n) Digital Differentiator
Q(n) Digital Differentiator .
Q(n)
Q(n-(N-1)/2)
Figure 8. FM discriminator.
4.5 Stereo Separation
A stereo FM channel consists of two sub channels,
one residing at baseband and the other offset on a 38
kHz sub-carrier - Figure 9. The two channels, denoted
L+R (sum of left (L) and right (R) audio) and L-R are
15 kHz audio signals.
Pilot Sub-carrier
L+R L-R
15 kHz 19 kHz 38 kHz
23 kHz 53 kHz
L = Left channel audio
R = Right channel audio
Figure 9. Broadcast FM stereo encoding.
The commercial FM format is designed to provide ste-
reo signals to receivers designed for stereo reception
and to provide a mono audio for non-stereo receivers.
The stereo components are added (L+R) and placed
at baseband for use in non-stereo receivers. A stereo
receiver also extracts the second signal containing (L-
R) from which the two separate components (L and R)
are formed as a sum and difference as shown in Eq.
(4).
[ L + R ](n) + [ L − R ](n) = 2 L(n)
(4)
[ L + R ](n) − [ L − R ](n) = 2 R (n)
The demodulation of the double sideband suppressed
carrier (DSB-SC) (L-R) signal is accomplished by a
heterodyne to baseband. The coherent local oscillator
required for the demodulation is obtained from the ac-
companying 19 kHz pilot signal. This pilot signal is
isolated by a band pass filter and is frequency doubled
down-convert the (L-R) signal. The delay inserted by
the low pass filtering of the down converted (L-R) sig-
nal precisely matches the delay inserted by the same
low pass filter inserted by the filter processing the
(L+R) signal.
Standard FIR filters can be used to perform all the fil-
tering needed for the stereo separation. Polyphase
filter structures lend themselves well to perform these
operations with a remarkable workload reduction.
The complete radio design occupies 2,226 logic slices,
25 block memories and 29 multipliers. With additional
work to increase resource sharing the block memory
and multiplier requirements could be reduced.
5 Conclusion
Potential revenue streams for communications service
suppliers based on new business models are driving
infrastructure equipment manufacturers to develop
new hardware platforms that provide unprecedented
performance. However, the performance aspects of
these new generation systems is only one component
of the very complex set of parameters that must be
 considered when building new equipment. Time-to- [6] Virtex-4 FPGAs, Xilinx Inc.,
market pressure continues to increase, which in turn http://www.xilinx.com/xlnx/xil_prodcat_landingpag
impacts the device technologies that are used in new e.jsp?title=Virtex-4
generation communication equipment. In the past,
system designers may have looked to application spe- [7] Virtex-II Datasheet, Xilinx Inc.,
cific integrated circuits (ASIC) or DSP processor array http://www.xilinx.com/xlnx/xweb/xil_publications_di
solutions. ASIC-based designs are increasingly not play.jsp?category=/Data+Sheets/FPGA+Device+F
sustainable due to escalating non-recurring engineer- amilies/Virtex-II&iLanguageID=1
ing (NRE) costs associated with advanced 90 or 65
nm process nodes. DSP processor arrays are chal- [8] C. Dick, “The Platform FPGA: Enabling the
lenging due to problem partitioning, inter-processor Software Radio”, SDR’02, Software Defined
communication and software flow issues. New genera- Radio Technical Conference, 11-12 Novem-
tion field programmable gate arrays provide a silicon ber 2002, San Diego, CA.
platform for building state-of-the-art communication
systems. The FPGA s suitable for addressing the
physical layer and multi-media processing require-
ments, in addition to providing support, by way of em-
bedded processors, or running protocol stacks associ-
ated with broader system connectivity.

This paper provided an overview of an FPGA imple-

mentation of a FM receiver. While FM is a simple
waveform by today’s standards, it is nevertheless a
modulation scheme that needs to be supported in a
number of application segments, e.g. military commu-
nications. A perspective of the work presented in the
paper is as one possible radio personality of a soft-
ware defined radio system.

6 References
[1] The Joint Tactical Radio System (JTRS) Program,
http://jtrs.army.mil/

[2] C. Dick, f. harris and M. Rice, “FPGA Implementa-

tion of Carrier Phase Synchronization for QAM
Demodulators”, J. of VLSI Signal Processing,
Special Issue: Special Issue on Field Programma-
ble Logic, Eds., Roger Woods and Russ Tessier,
Kluwer Academic Publishers, pp. 57-71, Jan.
2004.

[3] C. Dick and f. harris, “FPGA QAM Demodulator

Design”, 12th International Conference on Field
Programmable Logic and Applications, September
2-4, 2002 Montpellier(La Grande-Motte), France.

[4] C. Dick and f. harris, “FPGA Implementation of an

OFDM PHY”, IEEE Thirty-Seventh Asilomar Con-
ference on Signals, Systems and Computers, Pa-
cific Grove, CA, Nov. 9-12, 2003.

[5] Virtex-II Pro Datasheet, Xilinx Inc.,

http://www.xilinx.com/xlnx/xweb/xil_publications_di
splay.jsp?category=Publications/FPGA+Device+F
amilies/Virtex-II+Pro&iLanguageID=1

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