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Sequential circuits
primitive sequential elements
combinational logic
Models for representing sequential circuits
finite-state machines (Moore and Mealy)
representation of memory (states)
changes in state (transitions)
Basic sequential circuits
shift registers
counters
Design procedure
state diagrams
state transition table
next state functions
FSMs 1
Any sequential system can be represented
with a state diagram
Shift register
OUT1 OUT2 OUT3
input value shown
on transition arcs
output values shown IN D Q D Q D Q
within state node CLK
1
100 110
1 0 1 1
1
0
0 0 1 0
001 011
0
FSMs 2
State machine model
output Outputs
logic
Inputs
next state Next State
logic
Current State
FSMs 3
State Machine Model
output Outputs
logic
States: S1, S2, ..., Sk Inputs
next state Next State
Inputs: I1, I2, ..., Im logic
Outputs: O1, O2, ..., On
Transition function: Fs(Si, Ij) Current State
Next State
State
Clock 0 1 2 3 4 5
FSMs 4
How do we turn a state diagram into logic?
e.g. counter
flip-flops to hold state
logic to compute next state
clock signal controls when flip-flop memory can change
wait just long enough for combinational logic to compute new value
D Q D Q D Q
CLK
"1"
FSMs 5
FSM design procedure
FSMs 6
Synthesis Example
Derive the state transition table from the state transition diagram
note the don't care conditions that arise from the unused state codes
FSMs 7
Don’t cares in FSMs (cont’d)
Synthesize logic for next state functions derive input equations for flip-
flops
C+ C B+ C A+ C
X 1 1 0 X 0 0 1 X 1 0 0
A X 1 X 0 A X 1 X 1 A X 0 X 1
B B B
C+ = B
B+ = A + B’ C
A+ = A’ C’ + AC
FSMs 8
Self-starting FSMs
C+ C B+ C A+ C
0 1 1 0 1 0 0 1 1 1 0 0
A 0 1 1 0 A 1 1 1 1 A 0 0 1 1
B B B
FSMs 9
Self-starting FSMs
Start-up states
at power-up, FSM may be in an used or invalid state
design must guarantee that it (eventually) enters a valid state
Self-starting solution
design FSM so that all the invalid states eventually
transition to a valid state may limit exploitation of don't cares
011
000
FSMs 10
Mealy vs. Moore Machines
L’ R / TL, F
L / TL
A
L’ R’ / TR, F
FSMs 11
Specifying outputs for a Moore machine
FSMs 12
Specifying outputs for a Mealy machine
1/0
FSMs 13
Comparison of Mealy and Moore machines
logic for
inputs inputs outputs
combinational outputs
logic for
next state logic for combinational
reg outputs logic for reg
outputs
next state
Example: serial adder - add bits arriving serially on two input wires
P.S. N.S.
S A B Cin Cout S
A
combinational 0 0 0 0 0
B
logic Cout 0 0 1 0 1
0 1 0 0 1
Cin 0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
Adding 5 serial numbers on 5 separate lines 1 1 1 1 1
C D E
B
A A A A
A Sum
B S B S B S B S
FSMs 15
Moore Implementation - Pipelined
A2
A1
A A A A
A0 Sum
B S B S B S B S
FSMs 16
Example Abstract Verilog FSM –
Breshenham’s Algorithm
FSMs 17
Design Problem – Run-Length Encoder
7 8
RLE
clk valid
FSMs 18
RLE Design
FSMs 19
Start with Datapath
eq
=
7 7 7 valid
cnt
0 7 8
count 1
7
inc
FSM inputs clr
cen
clr cnt
eq
FSM outputs
clr, inc, valid, cnt,
FSMs 20
FSM Controller
START1
inc=x valid=0
clr=x count=x
START2
inc=x valid=0
clr=x count=x
SENDING
~eq
inc=x valid=1
clr=x count=0
inc=x valid=1
eq
clr=1 count=0
inc=x valid=1
~eq
clr=x count=1
eq
inc=1 valid=0
clr=0 count=x
COUNTING
FSMs 21
Verilog For State Machines
Mealy outputs
current state
FSMs 22
Implementing an FSM
FSMs 23
RLE State Table
- START1 START2 x x 0 x
- START2 SENDING x x 0 x
0 SENDING SENDING x x 1 0
1 SENDING COUNTING 1 x 1 0
0 COUNTING SENDING x x 1 1
1 COUNTING COUNTING 0 1 0 x
FSMs 24
RLE State Table
- 00 01 x x 0 x
- 01 10 x x 0 x
0 10 10 x x 1 0
1 10 11 1 x 1 0
0 11 10 x x 1 1
1 11 11 0 1 0 x
FSMs 25
Logic Synthesis
eq 0 0 1 1 1 eq 0 1 0 0 0 eq 0 X X X X
1 0 1 1 1 1 1 0 1 1 1 X X 0 1
eq 0 X X X X eq 0 0 0 1 1 eq 0 X X X 0
1 X X 1 X 1 0 0 0 1 1 X X 1 0
Q1 = Q1 + Q0
Q0 = Q1’ Q0’ + eq Q1
clr = Q0’
6 gates
inc = 1
valid = eq’ Q1 + Q1 Q0’ = Q1 (eq’ + Q0’)
cnttag = Q0
FSMs 26
RLE State Table
1-hot encoding
there are 8 output functions
- 0001 0010 x x 0 x
- 0010 0100 x x 0 x
0 0100 0100 x x 1 0
1 0100 1000 1 x 1 0
0 1000 0100 x x 1 1
1 1000 1000 0 1 0 x
FSMs 27
1-Hot Logic Functions
Q0 = reset
Q1 = Q0
Q2 = Q1 + eq’ (Q2 + Q3)
Q3 = eq (Q2 + Q3)
inc = 1
clr = Q2
valid = Q2 + eq’ Q3
cnttag = Q3
FSMs 28