Fr.

Conceicao Rodrigues College of Engineering, Bandra (W)

BE Electronics (SEM VII)
Project Proposal Form
2019 - 20
1. Name of the student(s) with roll numbers

• Prajwalita Agare (Roll No. 8145)

• Rajesh Dabade (Roll No. 8146)
• Peter D’souza (Roll No. 8147)
2. Title of the Project:

“32 bit 5 stage pipelined RISC based processor”

3. Project Category:
Research √ Software
Application Hardware
Product Software and Hardware √

4. Project Area:
Robotics & Instrumentation, Control Image Processing
systems
Internet of things µC and Embedded Systems

VLSI Design Computer Networks

Digital Signal Processing Communication Systems /Wireless

Communication
Fuzzy Logic OR Neural Networks Mobile Application

Artificial Intelligence Power Systems/ Solar systems

Others (Please Specify): Verilog HDL √

5 A. Project Abstract:
In this project VLSI architecture for 32 bit 5 stage pipelined RISC based is proposed in which this
processor will perform functions like addition, subtraction, multiplication, logic AND, logic OR. It will
consist instruction set through which operation to be performed.

5 B. Project Objectives:

 To design instruction set for processor.

 To design processor module using Verilog HDL.
 To verify processor module by Verilog Testbench.

6. Technical Feasibility

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References

1. .32-Bit Risc Processor For Computer Architecture

International Journal of Engineering Research & Technology (IJERT) Vol. 1 Issue 8, October - 2012
ISSN: 2278-0181.

2. .DESIGN AND IMPLEMENTATION OF 32-BIT RISC PROCESSOR

WITH FIVE STAGE PIPELINE
NEHA DWIVEDI, PRADEEP CHHAWCHARIA
Electronics and Communication Department, TINJRIT, Udaipur.