Digital Design through Verilog

UNIT-4: Digital Design with State Machine Charts

A finite state machine can be divided in to two types: 1.Moore state machine 2. Mealy state machine

Moore state machine: Fig. 1 has the general structure for Moore .The current state of the machine is
stored in the state memory, a set of n flip-flops clocked by a single clock signal (hence “synchronous”
state machine). The state vector (also current state, or just state) is the value currently stored by the state
memory.

The next state of the machine is a function of the state vector in Moore

Mealy state machine: Fig. 2 has general structure for Mealy. The current state of the machine is stored in
the state memory, a set of n flip-flops clocked by a single clock signal (hence “synchronous” state
machine). The state vector (also current state, or just state) is the value currently stored by the state
memory. The next state of the machine is a function of state vector and the inputs in Mealy.

Verilog Coding

The logic in a state machine is described using a case statement or the equivalent (e.g., if-else). All
possible combinations of current state and inputs are enumerated, and the appropriate values are specified
for next state and the outputs. A state machine may be coded as in Code 1 using two separate case
statements, or, as in code 2, using only one.

A single case statement may be preferred for Mealy machines where the outputs depend on the state
transition rather than just the current state.

Ex: Consider the case of a circuit to detect a pair of 1's or 0's in the single bit input. That is, input will be a
series of one's and zero's. If two one's or two zero's comes one after another, output should go high.
Otherwise output should be low.

1 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY

 Digital Design through Verilog

Here is a Moore type state transition diagram for the circuit.

When reset, state goes to 00; If input is 1, state will be 01 and if input is 0, state goes to 10. State will be
11 if input repeats. After state 11, goes to 10 state or 01 depending on the input, since overlapping pair
should not be considered. That is, if 111 comes, it should consider only one pair.

Following code the Verilog implementation of the state machine. Note that we updated outp and state in
separate always blocks, it will be easy to design. inp is serial input, outp is serial output, clk is clock and
rst is asynchronous reset. I have used nonblocking statements for assignments because we use previous
state to decide the next state, so state should be registered.

module fsm( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;

always @( posedge clk, posedge rst )

begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end

2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
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 Digital Design through Verilog

end

2'b10:
begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end

2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end

always @(posedge clk, posedge rst)

begin
if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;

end

endmodule

module fsm_test;

reg clk, rst, inp;

wire outp;
reg[15:0] sequence;
integer i;

fsm dut( clk, rst, inp, outp);

initial
begin

clk = 0;
rst = 1;
sequence = 16'b0101_0111_0111_0010;
#5 rst = 0;

for( i = 0; i <= 15; i = i + 1)

begin
inp = sequence[i];
3 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY
 Digital Design through Verilog
#2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

end
test2;
end
task test2;
for( i = 0; i <= 15; i = i + 1)
begin
inp = $random % 2;
#2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

end
endtask

endmodule

Now, let us re-design the above circuit using Mealy style state machine. Output depends on both state and
input. State transition diagram is as follows:

When reset, state becomes idle, that is 00. Next, if 1 comes, state becomes 01 and if 0 comes state
becomes 10 with output 0. We have showed input 1, output 0 as 1/0. If input bit repeats, output becomes
1 and state goes to 00. I implemented this state machine as in the code bellow. Only one always block is
used because both outp and state are dependent on state and inp.

module mealy( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;

always @( posedge clk, posedge rst ) begin

4 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY
 Digital Design through Verilog

if( rst ) begin

state <= 2'b00;
outp <= 0;
end
else begin
case( state )
2'b00: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b10;
outp <= 0;
end
end

2'b01: begin
if( inp ) begin
state <= 2'b00;
outp <= 1;
end
else begin
state <= 2'b10;
outp <= 0;
end

end

2'b10: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b00;
outp <= 1;
end

end

default: begin
state <= 2'b00;
outp <= 0;
end
endcase
end

5 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY

 Digital Design through Verilog

end

endmodule

Now, let us discuss difference between Moore and Mealy state machines depending on these codes.

• Moore state machine is easier to design than Mealy. First design the states depending on the
previous state and input. Then design output only depending on state. Whereas in Mealy, you
have to consider both state and input while designing the output.
• Mealy state machine uses less states than the Moore. Since inputs influence the output in the
immediate clock, memory needed to remember the input is less. So, it uses less flip flops and
hence circuit is simpler.
• In Mealy, output changes immediately when the input changes. We can observe this point when
you simulate the codes above. In Moore example, output becomes high in the clock next to the
clock in which state goes 11. So, Mealy is faster than Moore. Mealy gives immediate response to
input and Moore gives response in the next clock.

Sequence detector:

Let us design a circuit to detect a sequence of 1011 in serial input. This is an overlapping sequence. So, if
1011011 comes, sequence is repeated twice. Consider these two circuits. First one is Moore and second
one is Mealy. In Moore design below, output goes high only if state is 100. Note that we have used 1 less
state than Mealy and hence one flip flop less will be enough to design state machine.

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 Digital Design through Verilog

This time I will try to implement only Mealy machine. Try to understand the state diagram and compare
them first.

When reset, state goes to 00, where there is no previous inputs. State remains same until we get a '1' in the
input since there is no possibility of start of sequence. If a 1 comes in the input, it may be start of
sequence, so go to state 01. From 01, if again 1 comes, that means sequence is broken. But there is a
possibility of start of another new sequence. So, 01 is start of sequence and stay in the same state. If zero
comes, go to state 10. Another 0 when state is 10 breaks the sequence and state goes to 00, no sequence.
If 1 comes, continue to next state 11. If again 1 comes, sequence completes. Make the output high and go
to state 01, because there may be a overlapping sequence as I mentioned earlier. If zero comes, sequence
breaks and state goes to 10 since it may be second bit of another sequence.

module m1011( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;

always @( posedge clk, rst )

begin
if( rst )
state <= 2'b00;
else
begin
case( {state,inp} )
3'b000: begin
state <= 2'b00;
outp <= 0;
end
3'b001: begin
state <= 2'b01;
outp <= 0;
end
3'b010: begin
state <= 2'b10;
outp <= 0;
end
3'b011: begin
state <= 2'b01;
outp <= 0;
end

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 Digital Design through Verilog

3'b100: begin
state <= 2'b00;
outp <= 0;
end
3'b101: begin
state <= 2'b11;
outp <= 0;
end
3'b110: begin
state <= 2'b10;
outp <= 0;
end
3'b111: begin
state <= 2'b01;
outp <= 1;
end

endcase
end
end

endmodule

This time I combined state and inp using concatenation operator {} to make code smaller. state and inp is
used together to select the case. Using this a I avoided if-begin-end-else-begin-end in every case.

SM Charts:

As flowcharts are useful in software design, in the same way ASM Charts or State Machine charts are
useful in the hardware design of digital systems. This SM chart is a special type of state machine
flowchart, or SM chart for short. SM charts are also called ASM (algorithmic state machine) charts.
These SM Charts have many advantages. It is easier to understand the operation of a digital system by
inspection of the SM chart instead of the equivalent state graph. A given SM chart can be converted into
several equivalent forms, and each form leads directly to a hardware realization.

State diagram: State diagram is a pictorial representation of a behavior of a sequential circuit. The state
is represented by the circle, and the transition between states is indicated by directed lines connecting the
circles. A directed line connecting a circle with itself indicates that next state is same as present state.

State table: The information of the state diagram represented in a tabular form is known as state
synthesis table or simply state table.

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 Digital Design through Verilog

Transition table: A transition table is the next step to state table. The state diagram and state table
represent state using symbols or names. In the transition table, specific state variable values are assigned
to each state. Assignment of values to state variables is called state assignment.

ASM Charts: A State Machine chart or Algorithmic State Machine (ASM), which is similar to a flow-
chart is used to describe the behavior of a digital system or state machine. Algorithmic State Machine
charts are also known as State Machine (SM) Chart.

The basic difference between an ordinary flow chart and SM chart is that ,certain specific rules must be
followed in the construction of SM chart ,but no such specific rules are to be followed in the case of
flow-chart.

An Algorithmic State Machine Chart can be constructed from the State Graph of a Digital system.

ASM CHART –COMPONENTS:

There are three important components in an ASM Chart. They are (i) State Box (ii) Decision Box and (iii)
Conditional output Box.

State Box: The state box contains a state name followed by a slash (/) and an optional output list. After
the state assignment, a state code must be placed outside the box at the top.

Decision Box: A decision box is represented by the diamond shape symbol with true and false branches.
The condition placed in the box is a Boolean expression that is evaluated to determine which branch is
true.

(a).State box (b).Decision box (c).Conditional Output box

Conditional output Box: The conditional output box, which has curved ends, contains a conditional
output list. The conditional outputs depend on both the state of the system and inputs.

Specific Rules for constructing ASM Chart: Certain rules must be followed while constructing an SM
block. For every valid combination of input variables, there must be exactly one exit path defined .This is
necessary because, each allowable input combination must lead to a single next state.

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 Digital Design through Verilog

The second rule is no internal feedback within an SM block is allowed. This is shown in the diagram
below.

Wrong feedback correct feedback

Conversion of State graph into Equivalent ASM Chart: Let us consider a state graph with three states
S0, S1 and S2 as shown below. Here Za, Zb and Zc are the Moore outputs. And Z1 ,Z2 are the Mealy
outputs which change after a state change or input change.

The Moore outputs change only after a state change. The equivalent state chart is shown below.

10 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY

 Digital Design through Verilog

Derivation of ASM Charts: To derive the ASM chart for any digital system ,first its block diagram
must be drawn. Next ,the required input,output signals must be defined .Then the ASM Chart must be
constructed ,that tests the input signals and generates the proper sequence of the output signals.

Let us consider the case of a binary Multiplier .In the binary Multiplier ,there will be a add shift controller
which generates required sequence of add and shift signals.The counter counts the number of shifts and
outputs K=1 ,just before the last shift occurs. The block diagram and ASM Chart for Binary Multiplier
is shown below.

11 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY

 Digital Design through Verilog

Figure: ASM chart

In the ASM chart ,in the state S0,where the start signal St is 1 ,the registers are loaded.In S1,the Multiplier
bit M is tested. If M=1, an add signal is generated and the shift signal is generated and K is tested. If K=1
,this will be the last shift and the next state is S3. In S2, a shift signal is generated , since a shift must
always follow and add . If K=1 ,the network goes to S3 at the time of the last shift, otherwise ,the next
state is S1. In S3 ,the Done signal is turned ON.

ASM Chart for Dice Game:

Let us derive the SM chart for the electronic dice game. Figure below shows the block diagram for the
dice game. Here two counters are used to simulate the roll of the dice. Each counter counts in the
sequence 1, 2, 3, 4, 5, 6, 1, 2, . . . . Thus, after the “roll” of the dice, the sum of the values in the two
counters will be in the range 2 through 12.

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 Digital Design through Verilog

The two important rules of the game are as follows:

1. After the first roll of the dice, the player wins if the sum is 7 or 11. He loses if the sum is 2, 3, or 12.
Otherwise, the sum which he obtained on the first roll is referred to as his point, and he must roll the dice
again.
2. On the second or subsequent roll of the dice, he wins if the sum equals his point, and he loses if the
sum is 7. Otherwise, he must roll again until he finally wins or loses.
The inputs to the dice game come from two push buttons, Rb (roll button) and Reset. Reset is used to
initiate a new game.
When the roll button is pushed, the dice counters count at a high speed, so the values cannot be read on
the display. When the roll button is released, the values in the two counters are displayed and the game
can proceed. Because the button is released at a random time, this simulates a random roll of the dice. If
the Win light or Lose light is not on, the player must push the roll button again.
The components for the dice game shown in the block diagram include an adder which adds the two
counter outputs, a register to store the point, test logic to determine conditions for win or lose, and a
control circuit. The input signals to the control circuit are defined as follows:
D7 = 1 if the sum of the dice is 7
D711 = 1 if the sum of the dice is 7 or 11
The ASM Chart for Dice game is shown below.

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 Digital Design through Verilog

D2312 = 1 if the sum of the dice is 2, 3, or 12

Eq = 1 if the sum of the dice equals the number stored in the point register
Rb = 1 when the roll button is pressed
Reset = 1 when the reset button is pressed
The outputs from the control circuit are defined as follows:
Roll = 1 enables the dice counters
Sp = 1 causes the sum to be stored in the point register
Win = 1 turns on the win light
Lose = 1 turns on the lose light.

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 Digital Design through Verilog

In the ASM Chart control circuit waits in state S0 until the roll button is pressed (Rb = 1). Then, it goes to
state S1, and the roll counters are enabled as long as Rb = 1. As soon as the roll button is released (Rb =
0), D711 is tested. If the sum is 7 or 11, the circuit goes to state S2 and turns on the Win light; otherwise,
D2312 is tested. If the sum is 2, 3, or 12, it goes to state S3 and turns on the Lose light; otherwise, the
signal Sp becomes 1, and the sum is stored in the point register. It then enters S4 and waits for the player
to “roll the dice” again. In S5, after the roll button is released, if Eq = 1, the sum equals the point and state
S2 is entered to indicate a win. If D7 = 1, the sum is 7 and S3 is entered to indicate a loss. Otherwise, the
control returns to S4 so that the player can roll again. When in S2 or S3, the game is reset to S0 when the
Reset button is pressed.

Hardware description language:

Though the ASM chart methodology is very useful in the digital design process ,its main disadvantage is
that it is time consuming to draw the charts for large systems and also become cumbersome. So,
hardware oriented programming languages are used to express specific features of the design are used.
These hardware description languages also provide the schematic of the corresponding digital system or
even obtain the layout of an integrated circuit to realize it. There are two important popular Hardware
Description Languages, VHDL and VeriLog Though these languages are complex, they have the features
to declare flip-flops, registers, counters etc., which are the building blocks of any digital system.

A state machine can be modeled in VHDL as a structural description, dataflow description, or a

behavioral description. In this text, the behavioral description is considered. The structure of the
behavioral description is based here on two processes within the architecture of the design .

(i). The first process describes the transition from the current state to the next state.
(ii). The second process describes the output values for the current state and describes the next state.
The behavioral description uses the If-then-else and Case-when statements to achieve the required state
machine behavior.
VHDL Code For Multiplier:
Let us write a behavioral VHDL model for the multiplier based on the block diagram shown below
figure (i) and the state graph of figure (ii). As the control circuit has ten states, it is declared an integer
in the range 0 to 9 for the state signal . The signal ACC represents the 9-bit accumulator output .

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 Digital Design through Verilog

As indicated in figure (i) above , 4 bits from the accumulator (ACC) and 4 bits from the multiplicand
register are connected to the adder inputs ; the 4 sum bits and the carry output from the adder are
connected back to the accumulator. When an add signal (Ad ) occurs, the adder outputs are loaded into
the accumulator by the next clock pulse, thus, causing the multiplicand to be added to the accumulator.
An extra bit at the left end of the product register temporarily stores any carry which is generated when
the multiplicand is added to the accumulator. When a shift signal (Sh) occurs , all 9 bits of ACC are
shifted right by the next clock pulse.

16 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY

 Digital Design through Verilog

The following Behavioral code is written for the 4-bit Multiplier based on the above block diagram and
state graph.

Example 2-Verilog Code for a Serial Adder:

Let us consider the Verilog code for the serial adder with accumulator shown in figure(i) below. In figure
(i) below, if Sh = 1, the carry from the full adder is stored in the flip-flop at the same time the registers are
shifted on the falling edge of the clock.The VHDL code is based on the state graph for the controller
shown in figure(ii).

In the present VHDL program two processes are used to represent the state machine.

3. 4 to 2 Encoder using if else statement

module encoder4_2 ( din ,dout );

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 Digital Design through Verilog

output [1:0] dout ;

reg [1:0] dout ;
input [3:0] din ;
wire [3:0] din ;
always @ (din) begin
if (din==8)
dout = 0;
else if (din==4)
dout = 1;
else if (din==2)
dout = 2;
else dout = 3;
end
endmodule

One hot circuit: One-hot encoding is an alternative state assignment method which attempts to minimize
the combinational logic by increasing the number of flip-flops. The goal of the method is to try to reduce the
number of connections between the logic gates in the combinational circuit of the FSM. The presence of more
gate interconnections results into longer propagation delays and a slower FSM. Since the propagation delay
through the flip-flops is faster, FSMs require fewer logic gates but not necessarily fewer flip-flops.

There are 3 main points to making high speed state machines by one-hot encoding:

1. Use 'parallel_case' and 'full_case' directives on a 'case (1'b1)' statement

2. Use state[3] style to represent the current state
3. Assign next state by:

• default assignment of 0 to state vector

• fully specify all conditions of next state assignments, including staying in current state.

Also, these points are also recommended:

• Separate the code for next state assignment from output logic/assignments.
• Use parameters to assign state encoding (or `define)
• The output logic assignments may
o use continuous assignments,
o set/reset at specific conditions, holding value at all other times

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 Digital Design through Verilog

In the one-hot encoding (OHE) only one bit of the state variable is “1” or “hot” for any given
state. All other state bits are zero. Therefore, one flip-flop (register) is used for every state in the
machine i.e. n states uses n flip-flops. Using one-hot encoding, the next-state equations can be
derived easily from state diagrams. State decoding is simplified, since the state bits themselves
can be used directly to indicate whether the machine is in a particular state. In addition, with a
one-hot encoded state machine, the inputs to the state bits are often simply the functions of other
state bits

FPGAs are programmable logic devices that are rich in flip-flops and poor in combo logic. One-
Hot state machines use one flip-flop per state and thus need much less decode logic. This makes
OHE more efficient for FPGAs. The One-Hot encoding for a 5 state variables is shown below
in table.
State State Variables

One-Hot Code Binary Code Gray Code

S0 00001 000 000
S1 00010 001 001
S2 00100 010 011
S3 01000 011 010
S4 10000 100 110

One-hot encoding (OHE) is better suited for use with the fan-in limited and flip-flop-rich
architectures of the higher gate count filed-programmable gate arrays (FPGAs), such as offered
by Xilinx, Actel, and others. OHE maps very easily in these architectures. One-hot state
machines are typically faster. Speed is independent of the number of states, and instead depends
only on the number of transitions into a particular state.
FPGA have plenty of registers but the LUTs are limited to few bits wide. One-hot increases the
flip-flop usage (one per state) and decreases the width of combinatorial logic. It makes it easy to
decode the next state, resulting in large FSMs. And finally, since one hot code state assignment
reduces the area (area optimization) by using less logic gates, it consumes less power.
There are numerous advantages to using the one hot design methodology :
• Maps easily into register-rich FPGA architectures such as QuickLogic and Xilinx.

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 Digital Design through Verilog

• One-hot state machines are typically faster. Speed is independent of the number of states, and
instead depends only on the number of transitions into a particular state. A highly-encoded
machine may slow dramatically as more states are added.
• Don’t have to worry about finding an "optimal" state encoding. This is particularly beneficial as
the machine design is modified, for what is "optimal"for one design may no longer be best if you
add afew states and change some others. One-hot is equally "optimal" for all machines.
• One-hot machines are easy to design. Schematics can be captured and HDL code can be written
directly from the state diagram without coding a state table.
• Modifications are straightforward. Adding and deleting states, or changing excitation
equations, can be implemented easily without affecting the rest of the machine.
• Easily synthesized from VHDL or Verilog.
• There is typically no area penalty over highly encoded machines.
• Critical paths are easy to find using static timing analysis.
• Easy to debug. Bogus state transitions are obvious, and current state display is trivial.

Using a One-Hot State Assignment :

In designing with sequential CPLDs and FPGAs , it is considered that each logic cell contains
one or more flip-flops. These flip-flops are there whether we use them or not. This means that it
may not be important to minimize the number of flip-flops used in the design. Instead, we should
try to reduce the total number of logic cells used and try to reduce the interconnections between
cells. When several cells are cascaded to realize a function the propagation delay is increased
and the logic runs slower. In order to design faster logic, we should try to reduce the number of
cells required to realize each equation. The one-hot state assignment help to solve this.
The one-hot assignment uses one flip-flop for each state, so a state machine with N states
requires N flip-flops. Exactly one of the flip-flops is set to one (Hot) in each state and all others
are reset.(cold or zero).

Foe example let us consider the implementation of an LUT in FPGA device .

The output of the LUT can be written as

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 Digital Design through Verilog

F= a’b’c’d’ + a’b’c’d + a’bcd + ab’c’d + ab’cd’ +----------------------+ abcd

Here each one of the term requires one function generator.
If we use one-Hot assignment , the system with four states a,b,c,d (S0, S1, S2, and S3) could
use four flip-flops (Q0, Q1, Q2, and Q3) with the following state assignment .
S0 : Q0 Q1 Q2 Q3 = 1000 ,
S1: Q0 Q1 Q2 Q3 = 0100 ,
S2 : Q0 Q1 Q2 Q3 = 0010 and ,
S3 : Q0 Q1 Q2 Q3 = 0001 the remaining 12 combinations are not considered.

The next-state and output equations are written by inspecting the state graph. Consider the
partial state graph given in Figure below. In the graph all the four arcs lead into S3, so,there are
four conditions under which the next state is S3. These conditions are
Present state (PS) = S0 and X1 = 1,
PS = S1 and X2 = 1,
PS = S2 and X3 = 1,
PS = S3 and X4 = 1.
The next state of flip-flop Q3 is 1 under these four conditions (and 0 otherwise).
Therefore, the next-state equation for Q3 can be written as

Q+3 = X1 (Q0 Q1′ Q2′ Q3′ ) + X2 (Q0′ Q1 Q2′ Q3′) +X3 (Q0 ′ Q1′ Q2 Q3′ ) + X4 (Q0′ Q1′ Q2′ Q3 )

Here as Q0 = 1 means Q1 = Q2 = Q3 = 0, and the Q1 ′ Q2′ Q3′ term is redundant and so it can be
eliminated. Similarly, all of the primed state variables can be eliminated from the other terms, so
the next-state equation reduces to
Q+3 = X1Q0 + X2Q1 + X3Q2 + X4Q3

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 Digital Design through Verilog

In general, when a one-hot state assignment is used, each term in the next-state equation for each
flip-flop contains exactly one state variable, and the reduced equation can be written by
inspecting the state graph. Similarly, each term in each reduced output equation contains exactly
one state variable. Because Z1 = 1 when PS = S0 and X1 = 1, and also when PS = S2 and X3 = 1,
we can write that Z1 = X1Q0 + X3Q2.
By inspecting the state graph,
we can also write that Z2 = X2Q1 + X4Q3

When a one-hot assignment is used, resetting the system requires that one flip flop be set to 1
instead of resetting all flip-flops to 0. If the flip-flops used do not have a preset input, then we
can modify the one-hot assignment by replacing Q0 with Q0′ throughout.

The assignments for this are S0 : Q0 Q1 Q2 Q3 = 0000,

S1 : Q0 Q1 Q2 Q3 = 1100,
S2: Q0 Q1 Q2 Q3 = 1010,
S3: Q0 Q1 Q2 Q3 = 1001

And the modified equations are Q3+ = X1Q0′ + X2Q1 + X3Q2 + X4Q3

Z1 = X1Q0′ + X3Q2,
Z2 = X2Q1 + X4Q3

While designing with CPLDs or FPGAs, one should try both an assignment with a minimum
number of state variables and a one-hot assignment to check which one leads to a design with
the smallest number of logic cells. Alternatively, if the speed of operation is important, the
design which leads to the fastest logic should be chosen. When a one-hot assignment is used,
more next-state equations are required, but for some state graphs both the next-state and output
equations may contain fewer variables. An equation with fewer variables may require fewer
logic cells to realize. The more cells which are cascaded, the longer the propagation delay, and
the slower the operation.

22 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY

 Digital Design through Verilog

Simple example:
reg [2:0] state ;
parameter IDLE=0, RUN=1, DONE=2 ;
always @ (posedge clock or negedge resetl)
if ( ! resetl) begin
state <= 3'b001 ;
out1 <= 0 ;
end
else begin
state <= 3'b000 ;
case (1'b1) // synthesis parallel_case full_case
state[IDLE]:
if (go)
state[RUN] <= 1 ;
else
state[IDLE] <= 1 ;
state[RUN]:
if (finished)
state[DONE] <= 1 ;
else
state[RUN] <= 1 ;
state[DONE]:
state[IDLE] <= 1 ;
endcase
out1 <= state[RUN] & ! finished ;
end

Figure: Logic Implementation of the FSM

23 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY

 Digital Design through Verilog

One-hot encoding assigns one flip-flop for each state. For example, a finite-state machine
with N states requires N flip-flops. The states are assigned N-bit binary numbers; where only the
corresponding bit position is equal to 1, the remaining bits are equal to0. For example, in a finite-
state machine with four states S0, S1, S2, and S3, the states are assigned the binary values 0001,
0010, 0100, and 1000, respectively. Notice that only one bit position is equal to 1; the other bits
are all equal to 0. The reamaining 12 binary combinations are assigned to don't-care states.
Consider the Mealy-type finite-state machine described by the state diagram shown in Figure
9.19. The state diagram has three states: S0, S1, and S2. One-hot encoding assigns the binary
number values 001, 010, and 100 ...

Test bench writing:

 A test bench is an HDL program used for applying stimulus to an HDL design in order to
test it and observe its response during simulation.

 In addition to the always statement, test benches use the initial statement to provide a
stimulus to the circuit under test.

 The always statement executes repeatedly in a loop. The initial statement executes only
once starting from simulation time=0 and may continue with any operations that are
delayed by a given number of units as specified by the symbol #.

initial begin

A=0; B=0; #10 A=1; #20 A=0; B=1;

end

 The block is enclosed between begin and end. At time=0, A and B are set to 0. 10 time
units later, A is changed to 1. 20 time units later (at t=30) a is changed to 0 and B to 1.

 Inputs to a 3-bit truth table can be generated with the initial block

initial begin

D = 3’b000; repeat (7); #10 D = D + 3’b001;

end

 The 3-bit vector D is initialized to 000 at time=0. The keyword repeat specifies looping
statement: one is added to D seven times, once every 10 time units.

 A stimulus module is an HDL program that has the following form.

24 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY

 Digital Design through Verilog

module testname

Declare local reg and wire identifiers

Instantiate the design module under test.

Generate stimulus using initial and always statements

Display the output response.

endmodule

 A test module typically has no inputs or outputs.

 The signals that are applied as inputs to the design module for simulation are declared in
the stimulus module as local reg data type.

 The outputs of the design module that are displayed for testing are declared in the
stimulus model as local wire data type.

 The module under test is then instantiated using the local identifiers.

The stimulus model generates inputs for the design module by declaring identifiers TA
and TB as reg data type, and checks the output of the design unit with the wire identifier
TC. The local identifiers are then used to instantiate the design module under test.

 The response to the stimulus generated by the initial and always blocks will appear at the
output of the simulator as timing diagrams.

 It is also possible to display numerical outputs using Verilog system tasks.

 $display – display one-time value of variables or strings with end-of-line return,

 $write – same $display but without going to next line.

 $monitor – display variables whenever a value changes during simulation run.

25 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY
 Digital Design through Verilog

 $time – displays simulation time

 $finish – terminates the simulation

 The syntax for $display,$write and $monitor is of the form

Task-name (format-specification, argument list);

E.g. $display(%d %b %b, C,A,B);

$display(“time = %0d A = %b B=%b”,$time,A,B);

Ex:

//Stimulus for mux2x1_df

module testmux;

reg TA,TB,TS; //inputs for mux

wire Y; //output from mux

mux2x1_df mx (TA,TB,TS,Y); // instantiate mux

initial begin

$monitor(”select=%b A=%b B=%b OUT=%b",TS,TA,TB,Y);

TS = 1; TA = 0; TB = 1;

#10 TA = 1; TB = 0;

#10 TS = 0;

#10 TA = 0; TB = 1;

end

endmodule

26 Dr.Sreenivasa Rao Ijjada,Dept of ECE GITAM UNIVERSITY