ASSIGNMENT 2

SCAN INSERTION
1. Explain full scan and partition scan
Full scan : all sequential cell made scan able in full scan design. Sequential cell which is non
scan able is black box. Combination atpg algorithm is used

Partition scan: Scanning is done block by block.

2. Why do designs require scan insertion

The main idea in scan design is to obtain control and observability for flip-flops.
This is done by adding a test mode to the circuit such that when the circuit is in
This mode, all flip-flops functionally form one or more shift registers. The inputs and
Outputs of these shift registers (also known as scan registers) are made into primary
Inputs and primary outputs. Thus, using the test mode, all flip-flops can be set to
Any desired states by shifting those logic states into the shift register. So in scan design we
need to insert a test logic that’s why we need scan insertion.

Explain the different types of scan with diagrams.

Multiplex scan design
Level sensitive scan design
Scan clocked design

1. Explain the inputs needed for carrying out scan insertion for a design
Input needed for scan insertion is SI (Scan INPUT), DI (DATA input), SE (Scan Enable), and
TEST Clk Reset AND AT OUTPUT WE NEED SO (SCAN output).
2. What is scan chain balancing and what is the need of it
3. Balancing the scan chain is critical because if you have scan 10 scan chains and 9
chains has 10 flops but the 10th chain has 100 flops each shift has to be 100 clock
pulses and unnecessarily the tool has to insert X for 90 clock cycles. So your overall
test time for one pattern will be 100 clock cycles to scan in, 100 to scan out and one
capture cycle. It could have been 10 to shift in, 10 to shift out and 1 capture cycle. So
you overall test time for one pattern is 201 instead of 21. Now multiple these by the
number of patterns.
4. What is lockup latches? Why we need lockup latch? Write waveform

5. What is the impact of having latches in the design?

6. Can latches be part of scan chains, explain.

Latches are very often part of a scan chain, but most commonly as "lock-up
latches" that occur between clock domains, to guard against hold time violations in scan
shift mode. Yes.. If you design is latch based then you can implement the LSSD style
scan instead of mux-scan
7. What are DRC Rules during scan insertion?
In scan design, before insertion we have to check DRC Violation .there is various DRC
Violation some important Violation is:
Scan Rule Violation: Scan ability checking ensures that the tool can safely convert a
sequential element to a scan element. For each sequential element in the design, the
tool performs two main checks This Violation is related to scan non scan category denoted
by S

S1 Violation:

Category: Scannability
Contexts Supported: dft -scan, dft -test_points
Default Handling: Warning
(S Rules)

report_drc_rules: Supported
Scannability rule S1 checks all the clock inputs (including sets and resets) of each
non-scan
memory element to ensure that these inputs can be turned off or we can say The first
check, S1, ensures that when all defined clocks—including sets and resets—are at
their off states, the sequential elements remain stable and inactive.
This rule ensures that non-scan elements that may be converted to scan can be
controlled to hold their current data.

S2:
Category: Scannability
Contexts Supported: dft -scan, dft -test_points
Default Handling: Warning
report_drc_rules: Supported

Scannability rule S2 checks all clock inputs (not including sets and resets) of each
non-scan memory element to see whether they can capture data. This rules ensures
that a non-scan cell can capture data using one of the defined clocks. In order to be
converted to scan, a non-scan cell must be able to capture data when a single clock is
on.

S3:
Category: Scannability
Contexts Supported: dft -scan, dft -test_points
Default Handling: Warning
report_drc_rules: Supported

All non-clock primary input pins in the clock cone of non-scan memory elements
must be constrained. If these pins are unconstrained and made scannable, trace
violations may occur.
Non-clock primary input pins in the clock cone of non-scan memory elements should
be constrained in the ATPG dofile or load_unload procedure to correctly sensitize the
clock path.
2.CLOCK RULE : The application checks the scan clocks to ensure their proper definition
and operation. You may select the handling of any clock rule to be error, warning, note, or
ignore.

C1 : A scan or non-scan cell must not capture data when all specified clocks are set to their
off states.
C5 : A clock pin must not be capable of simultaneously capturing data on multiple ports of
the same scannable memory element.
The rule violation occurs on a clock pin when multiple clock inputs of a scannable memory
element are in the same clock cone and the clock inputs may be on at the same time.
The tool performs a mutual exclusivity check to determine if both clock inputs associated
with the failure can be active at the same time. If the justification results in a conflict without
justifying decision nodes, it will not be considered a rules violation.
C6 :
A clock must not affect data that it is capturing. If it does, a race condition may result that
produces inaccurate simulation results. The application performs this check by determining
the forward cone of influence for a clock pin (clock cone). The bounds for the clock cone are
scan cells and circuitry set to a fixed value when constrained pins are set to their constrained
values and initialized non-scan cells are set to Design Rule Checking their stable states. The
rule violation occurs on a clock pin when a clock input of a scannable memory element and
its data line are in the same clock cone.

C7 :
Each clock input (not including set and reset lines) of a scan or non-scan cell memory
element must be capable of capturing data when a single clock primary input line is on and
all other clocks are off. It is acceptable that this may require placing values on non-clock
primary inputs or scan cells.

Scan Cell Data Rules (D Rules)

D5 :
All memory elements (latches and flip-flops) must be scannable. The application performs
this check after identifying all scan memory elements. The rule violation occurs for all
memory elements not identified as part of a scan cell.

D6 :
All non-scan latches must behave as transparent latches. The application performs this check
for
all nonscan latches that are not set to a stable binary value. The rule violation occurs if a
candidate latch fails one of the following conditions:

If the latch creates a potential feedback path, that path must be broken by scan cells or
non-scan cells other than transparent latches. For more information, refer to the
set_tla_loop_handling command.

The latch must have a propagable path to an observable point.

The latch must be capable of passing a value when all defined clocks are at their offstate.

All clock, set, and reset inputs of the latch must either be set to a determinate state when
all clocks are off and pin constraints are set, or must not connect to defined clocks.
The latch must not have more than one set/reset/clock input on when all defined clocks
are at their off-state.

D7:
At the end of the shift procedure, the clock inputs of scan flip-flops must not be set to a one
State. The application performs this check using the simulated values of the last time period
of the shift procedure. The rule violation occurs if any clock input (not including set and reset
Lines) of any scan flip-flop (except COPY) is set to 1. A possible cause of a rules violation is
an incorrect definition of the off-state of a clock.

8. What is Scan? What are the difference between full scan and partial Scan?
Partial scan : A subset of flip-flops is scanned.
# Minimize area overhead and scan sequence length, yet
achieve required fault coverage

#Exclude selected flip-flops from scan:

Improve performance
Allow limited scan design rule violations
#Allow automation:
_ In scan flip-flop selection
_ In test generation
Shorter scan sequences – reduce application time
Select a minimal set of flip-flops for scan to
eliminate all cycles.
Alternatively, to keep the overhead low only long
cycles may be eliminated.
In some circuits with a large number of self-loops,
all cycles other than self-loops may be eliminated.

What are the benefits of scan?

9. What are the different scan styles? Explain each scan styles?
10. What are the scan methodology?
11. What is scan chain and scan group?
Scan chain is a technique used in design for testing. The objective is to make testing
easier by providing a simple way to set and observe every flip-flop in an IC.The basic
structure of scan include the following set of signals in order to control and observe the
scan mechanism
12. Explain the scan flow?
13. What is observability and controllability?
14. What is the use of Shift Enable & Test Enable signal?
15. What are the inputs and outputs for Scan?
16. How do you take care neg-edge flops during scan insertion?
17. What are the advantages and disadvantages clock mixing and clock domain stiching?
18. What is top down and bottom up approach scan insertion?
19. Explain clock gating circuit with diagram? Why we need clock gating circuit?
20. What is link library and target library?
21. If the entire design is a shift register, do you need scan insertion, explain

22. Where is negative edge flops placed in the scan chains? ) Can negative edge flops be in
between the scan chains, if yes explain what precautions to be taken care

Part-2
1. How you take care of design while inserting scan chain?
2. How to avoid hold issues when scan chain is stitched from +ve edge to –ve edge flop?
3. How asynchronous and synchronous resets are handled for scan?
4. How tri-states are handled during scan?
5. How does scan chain works? Explain with an example?