Mixed-Signal Front End For Broadband Applications AD9878: Features Functional Block Diagram

Mixed-Signal Front End
for Broadband Applications

AD9878
FEATURES FUNCTIONAL BLOCK DIAGRAM
Low cost 3.3 V CMOS MxFE™ for broadband applications I
12
DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant TxID[5:0] Tx Q 16 SINC–1 DAC Tx
232 MHz quadrature digital upconverter

DDS
12-bit direct IF DAC (TxDAC+®) Σ -∆ Σ-∆ OUTPUT
Up to 65 MHz carrier frequency DDS 3
4
CONTROL REGISTERS CA PORT
Programmable sampling clock rates SDIO
MCLK
Analog Tx output level adjust
PLL OSCIN
Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input
10
10-bit, 29 MSPS sampling ADC IF10[4:0] MUX ADC IF10 INPUT
8-bit ∑-∆ auxiliary DAC

12 IF12B INPUT
Direct interface to AD832x family of PGA cable drivers ADC MUX
Σ VIDEO IN
APPLICATIONS –
IF12[11:0] MUX CLAMP
Cable set-top boxes LEVEL
MUX
Cable and wireless modems 12
ADC IF12A INPUT
FLAG[2:1]
03277-001
Figure 1.
GENERAL DESCRIPTION
The AD9878 is a single-supply, cable modem/set-top box, The 12-bit ADCs provide excellent undersampling performance,
mixed-signal front end. The device contains a transmit path allowing this device to typically deliver better than 10 ENOBs
interpolation filter, a complete quadrature digital upconverter, with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at
and a transmit DAC. The receive path contains dual 12-bit rates up to 29 MHz, allowing them to process wideband signals.
ADCs and a 10-bit ADC. All internally required clocks and an
output system clock are generated by the phase-locked loop The AD9878 includes a programmable ∑-∆ DAC, which can be
(PLL) from a single crystal oscillator or clock input. used to control an external component such as a variable gain
amplifier (VGA) or a voltage controlled tuner.
The transmit path interpolation filter provides an upsampling
factor of 16× with an output signal bandwidth up to 4.35 MHz. The AD9878 also integrates a CA port that enables a host
Carrier frequencies up to 65 MHz with 26 bits of frequency tuning processor to interface with the AD832x family of programmable
resolution can be generated by the direct digital synthesizer gain amplifier (PGA) cable drivers or industry equivalent via
(DDS). The transmit DAC resolution is 12 bits and can run at the MxFE serial port (SPORT).
sampling rates as high as 232 MSPS. Analog output scaling from The AD9878 is available in a 100-lead, LQFP package. The
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when AD9878 is specified over the extended industrial (−40°C to
reduced output levels are required. +85°C) temperature range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
AD9878
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 4 Transmit Timing......................................................................... 21
Absolute Maximum Ratings............................................................ 7 Interpolation Filter..................................................................... 21
Explanation of Test Levels ........................................................... 7 Half-Band Filters (HBFs) .......................................................... 21
Thermal Characteristics .............................................................. 7 Cascade Integrator Comb (CIC) Filter.................................... 21
ESD Caution.................................................................................. 7 Combined Filter Response........................................................ 21
Pin Configuration and Function Descriptions............................. 8 Digital Upconverter ................................................................... 22
Typical Performance Characteristics ........................................... 10 Tx Signal Level Considerations ................................................ 22
Terminology .................................................................................... 13 Tx Throughput and Latency ..................................................... 23
Register Bit Definitions.................................................................. 14 DAC.............................................................................................. 23
Register 0x00—Initialization .................................................... 15 Programming the AD8321/AD8323 or

AD8322/AD8327/AD8238 Cable-Driver Amplifiers............ 23
Register 0x01—Clock Configuration....................................... 15
OSCIN Clock Multiplier ........................................................... 24
Register 0x02—Power-Down.................................................... 15
Clock and Oscillator Circuitry ................................................. 24
Register 0x03—Flag Control..................................................... 15
Programmable Clock Output REFCLK .................................. 24
Register 0x04—∑-∆ Control Word........................................... 15
Power-Up Sequence ................................................................... 26
Register 0x07—Video Input Configuration............................ 16
Reset ............................................................................................. 26
Register 0x08—ADC Clock Configuration ............................ 16
Transmit Power-Down .............................................................. 26
Register 0x0C—Die Revision.................................................... 16
∑-∆ Outputs ................................................................................ 27
Register 0x0D—Tx Frequency Tuning Words LSBs.............. 16
Receive Path (Rx) ....................................................................... 27
Register 0x0E—DAC Gain Control ......................................... 16
IF10 and IF12 ADC Operation ................................................ 27
Register 0x0F—Tx Path Configuration ................................... 16
ADC Voltage References ........................................................... 29
Registers 0x10 Through 0x17—Burst Parameter................... 17
Video Input ................................................................................. 29
Serial Interface for Register Control ............................................ 18
PCB Design Considerations.......................................................... 30
General Operation of the Serial Interface ............................... 18
Component Placement .............................................................. 30
Instruction Byte .......................................................................... 18
Power Planes and Decoupling .................................................. 30
Serial Interface Port Pin Descriptions ..................................... 18
Ground Planes ............................................................................ 30
MSB/LSB Transfers..................................................................... 19
Signal Routing............................................................................. 30
Notes on Serial Port Operation ................................................ 19
Outline Dimensions ....................................................................... 36
Theory of Operation ...................................................................... 20
Ordering Guide .......................................................................... 36
Transmit Path.............................................................................. 21
Data Assembler........................................................................... 21
Rev. A | Page 2 of 36
AD9878
REVISION HISTORY
3/05—Rev. 0 to Rev. A
Changed OSCOUT to REFCLK.................................................. Universal
Changes to Electrical Characteristics ........................................................4
Changes to Pin Configuration and Function Descriptions....................8
Changes to ∑-∆ Output Signals (Figure 32)............................................27
Change to ∑-∆ RC Filter (Figure 33) .......................................................27
Changes to Evaluation PCB Schematic (Figure 38 and Figure 39)......31
Updated Outline Dimensions...................................................................36
Changes to Ordering Guide......................................................................36
5/03—Revision 0: Initial Version
AD9878
ELECTRICAL CHARACTERISTICS
VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC clock derived from OSCIN,
RSET = 4.02 kΩ, maximum. Fine gain, 75 Ω DAC load.
Table 1.
PARAMETER Temp Test Level Min Typ Max Unit
OSCIN and XTAL CHARACTERISTICS
Frequency Range Full II 3 29 MHz
Duty Cycle 25°C II 35 50 65 %
Input Impedance 25°C III 100||3 MΩ||pF
MCLK Cycle-to-Cycle Jitter (fMCLK derived from PLL) 25°C III 6 ps rms
Tx DAC CHARACTERISTICS
Maximum Sample Rate Full II 232 MHz
Resolution N/A N/A 12 Bits
Full-Scale Output Current Full II 4 10 20 mA
Gain Error (Using Internal Reference) 25°C I −2.0 −1 +2.0 % FS
Offset Error 25°C I ±1.0 % FS
Reference Voltage (REFIO Level) 25°C I 1.18 1.23 1.28 V
Differential Nonlinearity (DNL) 25°C III ±2.5 LSB
Integral Nonlinearity (INL) 25°C III ±8 LSB
Output Capacitance 25°C III 5 pF
Phase Noise @ 1 kHz Offset, 42 MHz Carrier 25°C III −110 dBc/Hz
Output Voltage Compliance Range Full II −0.5 +1.5 V
Wideband SFDR
5 MHz Analog Output, IOUT = 10 mA Full II 62.4 68 dB
65 MHz Analog Output, IOUT = 10 mA Full II 50.3 53.5 dB
Narrow-Band SFDR (±1 MHz Window)
5 MHz Analog Output, IOUT = 10 mA Full II 71 74 dB
65 MHz Analog Output, IOUT = 10 mA Full II 61 64 dB
Tx MODULATOR CHARACTERISTICS
I/Q Offset Full II 50 55 dB
Pass-Band Amplitude Ripple (f < fIQCLK/8) Full II ±0.1 dB
Pass-Band Amplitude Ripple (f < fIQCLK/4) Full II ±0.5 dB
Stop-Band Response (f > fIQCLK × 3/4) Full II −63 dB
Tx GAIN CONTROL
Gain Step Size 25°C III 0.5 dB
Gain Step Error 25°C III <0.05 dB
Settling Time, 1% (Full-Scale Step) 25°C III 1.8 µs
10-BIT ADC CHARACTERISTICS
Maximum Conversion Rate Full II 29 MHz
Pipeline Delay N/A N/A 4.5 ADC cycles
Analog Input
Input Voltage Range Full II 2 VPPD
Differential Input Impedance 25°C III 4||2 kΩ||pF
Full Power Bandwidth 25°C III 90 MHz
Dynamic Performance (AIN = −0.5 dBFS, f = 5 MHz)
Signal-to-Noise and Distortion (SINAD) Full II 57.6 59.7 dB
Effective Number of Bits (ENOB) Full II 9.3 9.6 Bits
Total Harmonic Distortion (THD) Full II −71.1 −63.6 dB
Spurious-Free Dynamic Range (SFDR) Full II 65.7 72.4 dB
Reference Voltage Error, REFT10 to REFB10 (1.0 V) Full I ±4 ±100 mV
AD9878
12-BIT ADC CHARACTERISTICS
Maximum Conversion Rate Full II 29 MHz
Pipeline Delay N/A N/A 5.5 ADC cycles
Analog Input
Input Voltage Range Full III 2 VPPD
Differential Input Impedance 25°C III 4||2 kΩ||pF
Aperture Delay 25°C III 2.0 ns
Aperture Jitter 25°C III 1.2 ps rms
Full Power Bandwidth 25°C III 85 MHz
Input Referred Noise 25°C III 75 µV
Reference Voltage Error, REFT12 to REFB12 (1 V) Full I −100 ±16 +100 mV
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD) Full II 61.0 67 dB
Effective Number of Bits (ENOBs) Full II 9.8 10.8 Bits
Signal-to-Noise Ratio (SNR) Full II 64.2 66 dB
ADC Sample Clock = PLL
Signal-to-Noise Ratio (SNR) Full II 62.4 65.1 dB
Signal-to-Noise Ratio (SNR) Full II 64.2 67.4 dB
Differential Phase 25°C III <0.1 Degrees
Differential Gain 25°C III <1 LSB
VIDEO ADC PERFORMANCE (AIN = −0.5 dBFS, f = 5 MHz)
Signal-to-Noise and Distortion (SINAD) Full II 46.7 53 dB
Signal-to-Noise Ratio (SNR) Full II 54.3 63.2 Bits
Spurious-Free Dynamic Range (SFDR) Full II 45.9 50 dB
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation (5 MHz Analog Output)
Isolation Between Tx and 10-Bit ADC 25°C III >60 dB
Isolation Between Tx and 12-Bit ADCs 25°C III >80 dB
ADC-to-ADC Isolation (AIN = –0.5 dBFS, f = 5 MHz)
Isolation Between IF10 and IF12A/B 25°C III >85 dB
Isolation Between IF12A and IF12B 25°C III >85 dB
AD9878
TIMING CHARACTERISTICS (10 pF Load)
Wake-Up Time N/A N/A 200 tMCLK cycles
Minimum RESET Pulse Width Low, tRL N/A N/A 5 tMCLK cycles
Digital Output Rise/Fall Time Full II 2.8 4 ns
Tx/Rx Interface
MCLK Frequency, fMCLK Full II 58 MHz
TxSYNC/TxIQ Setup Time, tSU Full II 3 ns
TxSYNC/TxIQ Hold Time, tHU Full II 3 ns
MCLK Rising Edge to RxSYNC Valid Delay, tMD Full II 0 1.0 ns
REFCLK Rising or Falling Edge to Full II tOSCIN/ tOSCIN/ ns
RxSYNC Valid Delay, tOD 4 − 2.0 4 + 3.0
REFCLK Edge to MCLK Falling Edge, tEE Full II −1.0 +1.0 ns
SERIAL CONTROL BUS
Maximum SCLK Frequency, fSCLK Full II 15 MHz
Minimum Clock Pulse Width High, tPWH Full II 30 ns
Minimum Clock Pulse Width Low, tPWL Full II 30 ns
Maximum Clock Rise/Fall Time Full II 1 µs
Minimum Data/Chip-Select Setup Time, tDS Full II 25 ns
Minimum Data Hold Time, tDH Full II 0 ns
Maximum Data Valid Time, tDV Full II 30 ns
CMOS LOGIC INPUTS
Logic 1 Voltage 25°C II VDRVDD − 0.7 V
Logic 0 Voltage 25°C II 0.4 V
Logic 1 Current 25°C II 12 µA
Logic 0 Current 25°C II 12 µA
Input Capacitance 25°C III 3 pF
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage 25°C II VDRVDD − 0.6 V
Logic 0 Voltage 25°C II 0.4 V
POWER SUPPLY
Supply Current, IS (Full Operation) 25°C II 184 204 mA
Analog Supply Current, IAS 25°C III 105 115 mA
Digital Supply Current, IDS 25°C III 79 89 mA
Supply Current, IS
Standby (PWRDN Pin Active, IAS + IDS ) 25°C II 124 137 mA
Full Power-Down (Register 0x02 = 0xFF) 25°C II 46 52 mA
Power-Down Tx Path (Register 0x02 = 0x60) 25°C III 124 mA
Power-Down IF12 Rx Path (Register 0x02 = 0x1B) 25°C III 131 159 mA
Power Supply Rejection (Differential Signal)
Tx DAC 25°C III <0.25 % FS
10-Bit ADC 25°C III <0.0001 % FS
12-Bit ADC 25°C III <0.0004 % FS
AD9878
ABSOLUTE MAXIMUM RATINGS

Table 2.
Parameter Rating Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Power Supply (VAVDD, VDVDD, VDRVDD) 3.9 V
rating only; functional operation of the device at these or any
Digital Output Current 5 mA
other condition s above those indicated in the operational
Digital Inputs −0.3 V to VDRVDD + 0.3 V
section of this specification is not implied. Exposure to absolute
Analog Inputs −0.3 V to VAVDD + 0.3 V
maximum rating conditions for extended periods may affect
Operating Temperature −40°C to +85°C
device reliability.
Maximum Junction Temperature 150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
EXPLANATION OF TEST LEVELS
I. Devices are 100% production tested at 25°C and guaranteed
by design and characterization testing for extended industrial
operating temperature range (−40°C to +85°C).
II. Parameter is guaranteed by design and/or characterization

testing.
III. Parameter is a typical value only.
N/A. Test level definition is not applicable.
THERMAL CHARACTERISTICS
Thermal resistance of 100-lead LQFP: θJA = 40.5°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD9878
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFB12A
REFB12B
REFT12A
REFT12B
VIDEO IN
AGND10
AVDD10
IF12A+
IF12B+
IF12A–
IF12B–
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
IF10+
IF10–
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DRGND 1 75 REFT10
DRVDD 2 74 REFB10
(MSB) IF12(11) 3 73 AGND10
IF12(10) 4 72 AVDD10
IF12(9) 5 71 DRVDD
IF12(8) 6 70 DRGND
IF12(7) 7 69 REFCLK
IF12(6) 8 68 SIGDELT
IF12(5) 9 67 FLAG1
IF12(4) 10 66 FLAG2
IF12(3) 11 65 CA_EN
IF12(2) 12
AD9878 64 CA_DATA
IF12(1) 13 TOP VIEW 63 CA_CLK
IF12(0) 14 (Not to Scale) 62 DVDDOSC
(MSB) IF10(4) 15 61 OSCIN
IF10(3) 16 60 XTAL
IF10(2) 17 59 DGNDOSC
IF10(1) 18 58 AGNDPLL
IF10(0) 19 57 PLLFILT
RxSYNC 20 56 AVDDPLL
DRGND 21 55 DVDDPLL
DRVDD 22 54 DGNDPLL
MCLK 23 53 AVDDTx
DVDD 24 52 Tx+
DGND 25 51 Tx–
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TxIQ(4)
TxIQ(3)
TxIQ(2)
TxIQ(1)
TxIQ(0)
TxSYNC
RESET
PROFILE
SDIO
SDO
REFIO
FSADJ
(MSB) TxIQ(5)
DVDD
DGND
DVDD
DGND
DVDD
DGND
SCLK
PWRDN
CS
DGNDTx
DVDDTx
AGNDTx
03277-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions

Pin No. Mnemonic Descriptions
1, 21, 70 DRGND Pin Driver Digital Ground
2, 22, 71 DRVDD Pin Driver Digital 3.3 V Supply
3 (MSB) IF12(11) 12-Bit ADC Digital Ouput
4 to 14 IF12[10:0] 12-Bit ADC Digital Ouput
15 (MSB) IF10(4) 10-Bit ADC Digital Ouput
16 to 19 IF10[3:0] 10-Bit ADC Digital Ouput
20 RxSYNC Sync Output, 10-Bit and 12-Bit ADCs
23 MCLK Master Clock Output
24, 33, 35, 39 DVDD Digital 3.3 V Supply
25, 34, 36, 40 DGND Digital Ground
26 TxSYNC Sync Input for Transmit Port
27 (MSB) TxIQ(5) Digital Input for Transmit Port
28 to 32 TxIQ[4:0] Digital Input for Transmit Port
37 PROFILE Profile Selection Input
38 RESET Chip Reset Input
41 SCLK SPORT Clock
42 CS SPORT Chip Select
43 SDIO SPORT Data I/O
AD9878
Pin No. Mnemonic Descriptions
44 SDO SPORT Data Output
45 DGNDTx Tx Path Digital Ground
46 DVDDTx Tx Path Digital 3.3 V Supply
47 PWRDN Power-Down Transmit Path
48 REFIO TxDAC Decoupling (to AGND)
49 FSADJ DAC Output Adjust (External Resistor)
50 AGNDTx Tx Path Analog Ground
51, 52 Tx−, Tx+ Tx Path Complementary Outputs
53 AVDDTx Tx Path Analog 3.3 V Supply
54 DGNDPLL PLL Digital Ground
55 DVDDPLL PLL Digital 3.3 V Supply
56 AVDDPLL PLL Analog 3.3 V Supply
57 PLLFILT PLL Loop Filter Connection
58 AGNDPLL PLL Analog Ground
59 DGNDOSC Oscillator Digital Ground
60 XTAL Crystal Oscillator Inverted Output
61 OSCIN Oscillator Clock Input
62 DVDDOSC Oscillator Digital 3.3 V Supply
63 CA_CLK Serial Clock-to-Cable Driver
64 CA_DATA Serial Data-to-Cable Driver
65 CA_EN Serial Enable-to-Cable Driver
66, 67 FLAG[2:1] Programmable Flag Outputs
68 SIGDELT ∑-∆ DAC Output
69 REFCLK Reference Clock Output
72, 80 AVDD10 10-Bit ADC Analog 3.3 V Supply
73, 79 AGND10 10-Bit ADC Analog Ground
74 REFB10 10-Bit ADC Reference Decoupling Node
75 REFT10 10-Bit ADC Reference Decoupling Node
76, 81, 86, 89, 94, AGND 12-Bit ADC Analog Ground
97, 99
77, 78 IF10−, IF10+ Differential Input to 10-bit ADC
82, 85, 90, 93, 100 AVDD 12-Bit ADC Analog 3.3 V Supply
83 REFB12B ADC12B Reference Decoupling Node
84 REFT12B ADC12B Reference Decoupling Node
87, 88 IF12B−, IF12B+ Differential Input to ADC12B
91 REFB12A ADC12A Reference Decoupling Node
92 REFT12A ADC12A Reference Decoupling Node
95, 96 IF12A−, IF12A+ Differential Input to ADC12A
98 VIDEO IN Video Clamp Input
AD9878
TYPICAL PERFORMANCE CHARACTERISTICS

0 0
–10 –10
–20 –20
–30 –30
MAGNITUDE (dB)
MAGNITUDE (dB)
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
03277-025
03277-022
–90 –90
–100 –100
0 2 4 6 8 10 12 14 16 18 20 55 57 59 61 63 65 67 69 71 73 75
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 3. Dual-Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz, Figure 6. Dual-Sideband Spectral Plot, fC = 65 MHz, f = 1 MHz,
RSET = 10 kΩ (IOUT = 4 mA), RBW = 1 kHz RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz
0 0
–10 –10
–20 –20
–30 –30
MAGNITUDE (dB)
MAGNITUDE (dB)
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
03277-023
03277-026
–90 –90
–100 –100
0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100 120
Figure 4. Dual-Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz, Figure 7. Single Sideband @ 65 MHz, fC = 66 MHz,
RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz
0 0
–10 –10
–20 –20
–30 –30
MAGNITUDE (dB)
MAGNITUDE (dB)
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
03277-024
03277-027
–90 –90
–100 –100
55 57 59 61 63 65 67 69 70 73 75 0 20 40 60 80 100 120
Figure 5. Dual-Sideband Spectral Plot, fC = 65 MHz, Figure 8. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 1 kHz f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz
AD9878
0 0
–10 –10
–20 –20
–30
–30
MAGNITUDE (dB)
MAGNITUDE (dB)
–40
–40
–50
–50
–60
–60
–70
–70
–80
03277-031
03277-028
–90 –80
–100 –90
0 20 40 60 80 100 120 0 20 40 60 80 100 120
Figure 9. Single Sideband @ 42 MHz, fC = 43 MHz, Figure 12. Single Sideband @ 5 MHz, fC = 6 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz
0 0
–10 –10
–20 –20
–30 MAGNITUDE (dB) –30

MAGNITUDE (dB)
–40 –40
–50 –50
–60 –60
–70 –70
03277-032
03277-029
–80 –80
–90 –90
0 20 40 60 80 100 120 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 500 Hz
0 0
–10 –10
–20
–20
–30
–30
MAGNITUDE (dB)
MAGNITUDE (dB)
–40
–40
–50
–50
–60
–60
–70
–80 –70
03277-030
03277-033
–90 –80
–100 –90
0 20 40 60 80 100 120 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 500 Hz
AD9878
0 0
–10
–10
–20
–20
–30
MAGNITUDE (dB)
MAGNITUDE (dB)
–30
–40
–50 –40
–60
–50
–70
–60
–80
–70
03277-034
03277-036
–90
–100 –80
–50 –40 –30 –20 –10 0 10 20 30 40 50 0 5 10 15 20 25 30 35 40 45 50
Figure 15. Single Sideband @ 65 MHz, fC = 66 MHz, Figure 17. 16-QAM @ 42 MHz Spectral Plot, RBW = 1 kHz
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 50 Hz
0 0
–10
–10
–20
–20
–30
MAGNITUDE (dB)
MAGNITUDE (dB)
–30
–40
–50 –40
–60
–50
–70
–60
–80
–70
03277-037
03277-035
–90
–100 –80
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 25 30 35 40 45 50
Figure 16. Single Sideband @ 65 MHz, fC = 66 MHz, Figure 18. 16-QAM @ 5 MHz Spectral Plot, RBW = 1 kHz
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 10 Hz
AD9878
TERMINOLOGY
Differential Nonlinearity Error (DNL, No Missing Codes) Aperture Delay
An ideal converter exhibits code transitions that are exactly 1 LSB The aperture delay is a measure of the sample-and-hold amplifier
apart. DNL is the deviation from this ideal value. No missing (SHA) performance that specifies the time delay between the
codes indicates that all of the ADC codes must be present over rising edge of the sampling clock input and when the input
all operating ranges. signal is held for conversion.
Integral Nonlinearity Error (INL) Aperture Jitter

Linearity error refers to the deviation of each individual code from Aperture jitter is the variation in aperture delay for successive
a line drawn from negative full scale through positive full scale. samples and is manifested as noise on the input to the ADC.
The point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB Input Referred Noise
beyond the last code transition. The deviation is measured from The rms output noise is measured using histogram techniques.
the middle of each code to the true straight line. The standard deviation of the ADC output codes is calculated
in LSB, and converted to an equivalent voltage. This results in a
Phase Noise noise figure that can be directly referred to the input of the MxFE.
Single-sideband, phase-noise power is specified relative to the
carrier (dBc/Hz) at a given frequency offset (1 kHz) from the Signal-to-Noise and Distortion (SINAD) Ratio
carrier. Phase noise can be measured directly in single-tone SINAD is the ratio of the rms value of the measured input signal
transmit mode with a spectrum analyzer that supports noise to the rms sum of other spectral components below the Nyquist
marker measurements. It detects the relative power between frequency, including harmonics, but excluding dc. The value for
the carrier and the offset (1 kHz) sideband noise and takes SINAD is expressed in decibels.
the resolution bandwidth (RBW) into account by subtracting Effective Number of Bits (ENOB)
10 × log(RBW). It also adds a correction factor that compensates For a sine wave, SINAD can be expressed in terms of the number
for the implementation of the resolution bandwidth, log display, of bits. Using the following formula, it is possible to get a measure
and detector characteristic. of performance expressed as N, the effective number of bits:
Output Compliance Range N = (SINAD − 1.76 ) dB 6.02
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can Thus, the effective number of bits for a device for sine wave
cause either output stage saturation or breakdown, resulting in inputs at a given input frequency can be calculated directly
nonlinear performance. from its measured SINAD.
Spurious-Free Dynamic Range (SFDR) Signal-to-Noise Ratio (SNR)
The difference, in dB, between the rms amplitude of the DAC SNR is the ratio of the rms value of the measured input signal
output signal (or ADC input signal) and the peak spurious signal to the rms sum of other spectral components below the Nyquist
over the specified bandwidth (Nyquist bandwidth, unless frequency, excluding harmonics and dc. The value for SNR is
otherwise noted). expressed in decibels.
Pipeline Delay (Latency) Total Harmonic Distortion (THD)
The number of clock cycles between conversion initiation and THD is the ratio of the rms sum of the first six harmonic
the associated output data being made available. components to the rms value of the measured input signal.
It is expressed as a percentage, or in decibels.
Offset Error
The first code transition should occur at an analog value ½ LSB Power Supply Rejection
above negative full scale. Offset error is defined as the deviation Power supply rejection specifies the converter’s maximum full-
of the actual transition from that point. scale change when the supplies are varied from nominal to
minimum or maximum specified voltages.
Gain Error
The first code transition should occur at an analog value ½ LSB Channel-to-Channel Isolation (Crosstalk)
above negative full scale. The last transition should occur for an In an ideal multichannel system, the signal in one channel does
analog value 1½ LSB below the nominal full scale. Gain error not influence the signal level of another channel. The channel-
is the deviation of the actual difference between first and last to-channel isolation specification is a measure of the change
code transitions and the ideal difference between first and last that occurs in a grounded channel as a full-scale signal is
code transitions. applied to another channel.
AD9878
REGISTER BIT DEFINITIONS

Table 4. Register Map
Address Default
(Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Type
0x00 SDIO LSB Reset OSCIN multiplier M[4:0] 0x08 Read/write
bidirectional first
0x01 PLL lock MCLK divider R[5:0] 0x00 Read/write
detect
0x02 Power down Power Power Power Power down Power Power Power 0x00 Read/write
PLL down down down ADC12B down down down
DAC digital ADC12A ADC10 reference reference
Tx Tx ADC12A ADC12B
0x03 Video Flag 2 Flag 1 Flag 0 0x00 Read/write
input enable
into
ADC12B
0x04 MSB/Flag 0 ∑-∆ output control word [7:0] 0x00 Read/write
0x05 0x00 Read/write
0x06 0x00 Read only
0x07 Video input Clamp level for video input [6:0] 0x00 Read/write
enable
0x08 ADC clocked Rx port Power Power down Send Send 0x80 Read/write
directly from fast down reference ADC12A ADC12B
OSCIN edge RxSYNC ADC10 data only data only
rate generator
0x09 0x00 Read/write
0x0A 0x00 Read/write
0x0B 0x00 Read/write
0x0C Version [3:0] 0x00 Read/write
0x0D Tx frequency tuning word Tx frequency tuning 0x00 Read/write
profile 1 LSB [1:0] word profile 0 LSBs [1:0]
0x0E DAC fine gain control [3:0] 0x00 Read/write
0x0F Tx path Tx path Tx Tx path Tx path 0x00 Read/write
select AD8321/AD8323 path spectral transmit
Profile 1 gain control bypass inversion single
mode sinc–1 tone
filter
0x10 Tx Path Frequency Tuning Word Profile 0 [9:2] 0x00 Read/write
0x13 Cable-driver amplifier, Cable-driver amplifier, 0x00 Read/write
Coarse Gain Control Profile 0 [7:4] Fine Gain Control Profile 0 [3:0]
0x17 Cable-driver amplifier, Cable-driver amplifier, 0x00 Read/write
Coarse Gain Control Profile 1 [7:4] Fine Gain Control Profile 1 [3:0]
AD9878
REGISTER 0x00—INITIALIZATION Bit 1: Power Down ADC12A Voltage Reference
Bits 0 to 4: OSCIN Multiplier Active high powers down the voltage reference circuit for
This register field is used to program the on-chip clock the ADC12A.
multiplier that generates the chip’s high frequency system clock, Bit 2: Power Down ADC10
fSYSCLK. For example, to multiply the external crystal clock fOSCIN Active high powers down the 10-bit ADC.
by 16, program Register 0x00, Bits 4:0, to 0x10. The default
clock multiplier value, M, is 0x08. Valid entries range from 1 to Bit 3: Power Down ADC12B
31. When M is set to 1, the PLL is disabled and internal clocks Active high powers down the ADC12B.
are derived directly from OSCIN. The PLL requires 200 MCLK Bit 4: Power Down ADC12A
cycles to regain frequency lock after a change in M. After the
Active high powers down the ADC12A.
recapture time of the PLL, the frequency of fSYSCLK is stable.
Bit 5: Power Down Tx
Bit 5: Reset
Active high powers down the digital transmit section of the
Writing 1 to this bit resets the registers to their default values
chip, similar to the function of the PWRDN pin.
and restarts the chip. The reset bit always reads back 0. The bits
in Register 0x00 are not affected by this software reset. However, Bit 6: Power Down DAC Tx
a low level at the RESET pin forces all registers, including all Active high powers down the DAC.
bits in Register 0x00, to their default states.
Bit 7: Power Down PLL
Bit 6: LSB First Active high powers down the OSCIN multiplier.
Active high indicates SPI serial port access of instruction byte and
data registers is LSB first. Default low indicates MSB-first format. REGISTER 0x03—FLAG CONTROL
Bit 0: Flag 0 Enable
Bit 7: SDIO Bidirectional
When this bit is active high, the SIGDELT pin maintains a fixed
Active high configures the serial port as a 3-signal port with
logic level determined directly by the MSB of the ∑-∆ control
the SDIO pin used as a bidirectional input/output pin. Default word of Register 0x04.
low indicates that the serial port uses four signals with SDIO
configured as an input and SDO configured as an output. Bit 1: Flag 1
The logic level of this bit is applied at the FLAG1 pin.
REGISTER 0x01—CLOCK CONFIGURATION
Bits [5:0]: MCLK Divider Bit 4: Flag 2
This register determines the output clock on the REFCLK pin. The logic level of this bit is applied at the FLAG2 pin.
At default 0 (R = 0), REFCLK provides a buffered version of the Bit 5: Video Input into ADC12B
OSCIN clock signal for other chips. The register can also be used If the video input is enabled, setting this bit high sends the
to divide the chip’s master clock fMCLK by R, where R is an integer signal applied to the VIDEO IN pin to the ADC12B. Otherwise,
between 2 and 63. The generated reference clock on REFCLK pin the signal applied to the VIDEO IN pin is sent to the ADC12A.
can be used for external frequency controlled devices.
Bit 7: PLL Lock Detect REGISTER 0x04—∑-∆ CONTROL WORD
Bits [7:0]: ∑-∆ Control Word
When this bit is set low, the REFCLK pin functions in its
The ∑-∆ control word is 8 bits wide and controls the duty cycle
default mode and provides an output clock with frequency
of the digital output on the SIGDELT pin. Changes to the ∑-∆
fMCKL/R, as described above. If this bit is set to 1, the REFCLK pin
control word take effect immediately for every register write.
is configured to indicate whether the PLL is locked to fOSCIN. In
∑-∆ output control words have a default value of 0. The control
this mode, the REFCLK pin should be low-pass filtered with an
words are in straight binary format, with 0x00 corresponding to
RC filter of 1.0 kΩ and 0.1 µF. A low output on REFCLK indicates
the bottom of scale or 0% duty cycle, and 0xFF corresponding
that the PLL has achieved lock with fOSCIN.
to the top of scale or near 100% duty cycle.
REGISTER 0x02—POWER-DOWN Bit 7: Flag 0 (∑-∆ Control Word MSB)
Unused sections of the chip can be powered down when the When the Flag 0 enable bit (Register 0x03, Bit 0) is set, the logic
corresponding bits are set high. This register has a default value level of this bit appears on the output of the SIGDELT pin.
of 0x00, all sections active.
Bit 0: Power Down ADC12B Voltage Reference
Active high powers down the voltage reference circuit
for ADC12B.
AD9878
REGISTER 0x07—VIDEO INPUT CONFIGURATION REGISTER 0x0C—DIE REVISION
Bits [6:0]: Clamp Level Control Value Bits [3:0]: Version
The 7-bit clamp-level control value is used to set an offset to the The die version of the chip can be read from this register.
automatic clamp-level control loop. The actual ADC output has a
REGISTER 0x0D—Tx FREQUENCY TUNING WORDS
clamp-level offset equal to 16 times the clamp level control value.
LSBs
Clamp - Level Offset Clamp - Level Control Value = ( x ) 16 This register accommodates the 2 LSBs for each frequency tuning
word (FTW). See the Registers 0x10 Through 0x17—
The default value for the clamp-level control value is 0x20. This Burst Parameter section.
results in an ADC output clamp-level offset of 512 LSBs. The
valid programming range for the clamp-level control value is REGISTER 0x0E—DAC GAIN CONTROL
0x16 to 0x127. This register allows the user to program the DAC gain if the
Bit 7: Video Input Enable Tx Gain Control Select Bit 3 in Register 0x0F is set to 0.
This bit enables the video input. In default with Bit 7 = 0, both
IF12 ADCs are connected to IF inputs. If the video input is
Table 5. DAC Gain Control
enabled by setting bit 7 = 1, the video input will be connected to
Bits [3:0] DAC Gain (dB)
the IF12 ADC selected by REG 0x03, Bit 6.
0000 0.0 (default)
REGISTER 0x08—ADC CLOCK CONFIGURATION 0001 0.5
Bit 0: Send ADC12B Data Only 0010 1.0
When this bit is set high, the device enters a nonmultiplexed 0011 1.5
mode, and only the data from the ADC12B is sent to the … …
IF[11:0] digital output port. 1110 7.0
1111 7.5
Bit 1: Send ADC12A Data Only
When this bit is set high, the device enters a nonmultiplexed
mode, and only the data from the ADC12A is sent to the REGISTER 0x0F—Tx PATH CONFIGURATION
IF[11:0] digital output port. Bit 0: Single Tone Tx Mode
If both the send ADC12B data only and send ADC12A data Active high configures the AD9878 for single-tone applications
only register bits are set high, the device sends both ADC12A (e.g., FSK). The AD9878 supplies a single frequency output, as
and ADC12B data in the default multiplexed mode. determined by the FTW selected by the active profile. In this
mode, the TxIQ input data pins are ignored, but should be tied
Bit 3: Power Down ADC10 Voltage Reference
to a valid logic voltage level. Default value is 0x00 (inactive).
Active high powers down the voltage reference circuit for
Bit 1: Spectral Inversion Tx
the ADC10.
When set to 1, inverted modulation is performed:
Bit 4: Power Down RxSYNC Generator
Setting this bit to 1 powers down the 10-bit ADC’s sampling [
MODULATOR _ OUT = I cos (ωt ) + Q sin (ωt ) . ]
clock and makes the RxSYNC output pin stay low. It can be
used for additional power saving on top of the power-down Default is Logic 0, noninverted modulation:
selections in Register 0x02.
[
MODULATOR _ OUT = I cos (ωt ) − Q sin (ωt ) . ]
Bit 5: Rx PORT Fast Edge Rate
Bit 2: Bypass Inv Sinc Tx Filter
Setting this bit to 1 increases the output drive strength of all digital
output pins, except MCLK, REFCLK, SIGDELT, and Active high configures the AD9878 to bypass the sin(x)/x com-
FLAG[2:1]. These pins always have high output drive capability. pensation filter. Default value is 0x00 (inverse sinc filter enabled).
Bit 7: ADC Clocked Directly from OSCIN Bit 3: CA Interface Mode Select
When set high, the ADC sampling clock is derived directly from This bit changes the format of the AD9878 3-wire CA interface to
the input clock at OSCIN. In this mode, the clock supplied to the a format in which the AD9878 digitally interfaces to external
OSCIN pin should originate from an external crystal or low jitter variable gain amplifiers. This is accomplished by changing
crystal oscillator. When this bit is low, the ADC sampling clock the interpretation of the bits in Register 0x13, Register 0x17,
is derived from the internal PLL and the frequency of the clock Register 0x1B, and Register 0x1F. See the Cable-Driver Gain
is equal to fOSCIN × M/8. Control section for more detail.
AD9878
Setting this bit to 0 (default) configures the serial interface to be Table 6. Cable-Driver Gain Control
compatible with AD8321/AD8323/AD8328 variable cable gain Bits [7:4] CA Interface Transmit Word
amplifiers. Setting this bit to 1 configures the serial interface to be 0000 0000 0000 (default)
compatible with AD8322/AD8327 variable cable gain amplifiers. 0001 0000 0001
Bit 5: Profile Select 0010 0000 0010
0011 0000 0100
The AD9878 quadrature digital upconverter can store two
0100 0000 1000
preconfigured modulation modes, called profiles. Each profile
0101 0001 0000
defines a transmit FTW, cable-driver amplifier gain setting, and
0110 0010 0000
DAC gain setting. The profile select bit or PROFILE pin programs
0111 0100 0000
the current register profile to be used. If the PROFILE pin is used
1000 1000 0000
to switch between profiles, the profile select bit should be set to 0
and tied low.
Table 7. DAC Output Fine Gain Setting
REGISTERS 0x10 THROUGH 0x17—
Bits [3:0] DAC Fine Gain (dB)
BURST PARAMETER
Tx Frequency Tuning Words 0000 0.0 (default)
0001 0.5
The FTW determines the DDS-generated carrier frequency (fC)
0010 1.0
and is formed via a concatenation of register addresses.
0011 1.5
The 26-bit FTW is spread over four register addresses. Bit 25 is … …
the MSB, and Bit 0 is the LSB. The carrier frequency equation is 1110 7.0
as follows: 1111 7.5
f C = (FTW × f SYSCLK ) 2 26
New data is automatically sent over the 3-wire CA interface
Where f SYSCLK = M × f OSCIN , and FTW < 0 x2000 . (and DAC gain adjust) whenever the value of the active gain
control register changes or a new profile is selected. The default
Changes to FTW bytes take effect immediately. value is 0x00 (lowest gain).
Cable-Driver Gain Control The formula for the combined output-level calculation of
The AD9878 has a 3-pin interface to the AD832x family of AD9878 fine gain and AD8327 or AD8322 coarse gain is:
programmable gain cable-driver amplifiers. This allows direct
V8327 = V9878 ( 0 ) + ( fine ) 2 + (coarse ) − 19
control of the cable driver’s gain through the AD9878. In its
V8322 = V9878 ( 0 ) + ( fine ) 2 + (coarse ) − 14
default mode, the complete 8-bit register value is transmitted
over the 3-wire cable amplifier (CA) interface.
If Bit 3 of Register 0x0F is set high, Bits [7:4] of Register 0x13 where:
and Register 0x17 determine the 8-bit word sent over the CA fine is the decimal value of Bits [3:0].
interface, according to the specifications in Table 6. Bits [3:0] of coarse is the decimal value of Bits [7:4].
Register 0x13 and Register 0x17 determine the fine gain setting V9878(0) is the level at AD9878 output in dBmV for fine = 0.
of the DAC output, according to specifications in Table 7. V8327 is the level at output of AD8327 in dBmV.
V8322 is the level at output of AD8322 in dBmV.
AD9878
SERIAL INTERFACE FOR REGISTER CONTROL

The AD9878 serial port is a flexible, synchronous, serial Table 9. Bit Decodes
communications port that allows easy interface to many N1 N0 Description
industry-standard microcontrollers and microprocessors. 0 0 Transfer 1 byte
The interface allows read/write access to all registers that 0 1 Transfer 2 bytes
configure the AD9878. Single or multiple byte transfers are 1 0 Transfer 3 bytes
supported. Also, the interface can be programmed to read words 1 1 Transfer 4 bytes
either MSB first or LSB first. The AD9878 serial interface port Bits [A4:A0] determine which register is accessed during the
I/O can be configured to have one bidirectional I/O (SDIO) data transfer portion of the communication cycle. For multi-
pin, or two unidirectional I/O (SDIO/SDO) pins. byte transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD9878.
GENERAL OPERATION OF THE SERIAL INTERFACE
tDS
There are two phases of a communication cycle with the AD9878. tSCLK
Phase 1 is the instruction cycle, which is the writing of an in- CS
tPWH tPWL
struction byte into the AD9878, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9878 SCLK
tDH
serial port controller with information regarding the data transfer tDS
03277-005
cycle, which is Phase 2 of the communication cycle. SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6
Figure 19. Timing Diagram for Register Write

The Phase 1 instruction byte defines whether the upcoming data
transfer is a read or write, the number of bytes in the data transfer,
and the starting register address for the first byte of the data CS
transfer. The first eight SCLK rising edges of each communication

SCLK
cycle are used to write the instruction byte into the AD9878.
tDV
03277-006
The eight remaining SCLK edges are for Phase 2 of the commu- SDIO
SDO DATA BIT N DATA BIT N
nication cycle. Phase 2 is the actual data transfer between the
Figure 20. Timing Diagram for Register Read
AD9878 and the system controller. Phase 2 of the communication
cycle is a transfer of one to four data bytes, as determined by the SERIAL INTERFACE PORT PIN DESCRIPTIONS
instruction byte. Normally, using one multibyte transfer is the
SCLK—Serial Clock. The serial clock pin is used to synchronize
preferred method. However, single-byte data transfers are useful
data transfers from the AD9878 and to run the serial port state
to reduce CPU overhead when register access requires only one
machine. The maximum SCLK frequency is 15 MHz. Input data
byte. Registers change immediately upon writing to the last bit
to the AD9878 is sampled up on the rising edge of SCLK. Output
of each transfer byte.
data changes upon the falling edge of SCLK.
INSTRUCTION BYTE CS—Chip Select. Active low input starts and gates a commu-
The R/W bit of the instruction byte determines whether a read nication cycle. It allows multiple devices to share a common
or a write data transfer occurs after the instruction byte write. serial port bus. The SDO and SDIO pins go into a high impedance
Logic high indicates a read operation; logic low indicates a write state when CS is high. Chip select should stay low during the
operation. The [N1:N0] bits determine the number of bytes to entire communication cycle.
be transferred during the data transfer cycle. The bit decodes
are shown in Table 9. The timing diagrams are shown in Figure 19 SDIO—Serial Data I/O. Data is always written into the AD9878
and Figure 20. on this pin. However, this pin can be used as a bidirectional
data line. The configuration of this pin is controlled by Bit 7 of
Register 0x00. The default is Logic 0, which configures the SDIO
Table 8. Instruction Byte Information pin as unidirectional.
MSB 17 16 15 14 13 12 11 LSB 10
SDO—Serial Data Out. Data is read from this pin for protocols
R/W N1 N0 A4 A3 A2 A1 A0
that use separate lines for transmitting and receiving data. In
the case where the AD9878 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
AD9878
MSB/LSB TRANSFERS NOTES ON SERIAL PORT OPERATION
The AD9878 serial port can support either MSB-first or LSB-first The AD9878 serial port configuration bits reside in Bit 6 and
data formats. This functionality is controlled by the LSB-first bit Bit 7 of Register Address 0x00. Note that the configuration
in Register 0x00. changes immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register might occur
The AD9878 default serial port mode is MSB-first (see Figure 21),
during a communication cycle. Measures must be taken to
which is programmed by setting Register 0x00 low. In MSB-first
compensate for this new configuration for the remaining bytes of
mode, the instruction byte and data bytes must be written from
the current communication cycle.
the MSB to the LSB. In MSB-first mode, the serial port internal
byte address generator decrements for each byte of the multibyte The same considerations apply when setting the reset bit in
communication cycle. When decrementing from 0x00, the Register Address 0x00. All other registers are set to their default
address generator changes to 0x1F. values, but the software reset does not affect the bits in Register
Address 0x00. It is recommended to use only single-byte transfers
When the LSB-first bit in Register 0x00 is set active high, the
when changing serial port configurations or initiating a software
AD9878 serial port is in LSB-first format (Figure 22). In LSB-
reset. A write to Bit 1, Bit 2, and Bit 3 of Address 0x00 with the
first mode, the instruction byte and data bytes must be written
same logic levels as Bit 7, Bit 6, and Bit 5 (bit pattern: XY1001YX
from the LSB to the MSB. In LSB-first mode, the serial port
binary) allows the user to reprogram a lost serial port config-
internal byte address generator increments for each byte of the
uration and to reset the registers to their default values. A
multibyte communication cycle. When incrementing from
second write to Address 0x00, with the reset bit low and the
0x1F, the address generator changes to 0x00.
serial port configuration as specified above (XY), reprograms
the OSCIN multiplier setting. A changed fSYSCLK frequency is
stable after a maximum of 200 fMCLK cycles (wake-up time).
CS INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
SDIO R/W N1 N0 A4 A3 A2 A1 A0 D7n D6n D20 D10 D00

03277-003
SDO D7n D6n D20 D10 D00
Figure 21. Serial Register Interface Timing, MSB-First Mode
CS INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D6n D7n

03277-004
SDO D00 D10 D20 D6n D7n
Figure 22. Serial Register Interface Timing, LSB-First Mode
AD9878
THEORY OF OPERATION
For a general understanding of the AD9878, refer to Figure 23, a The 12-bit and 10-bit IF ADCs can convert direct IF inputs of
block diagram of the device architecture. The device consists of a up to 70 MHz and run at sample rates of up to 29 MSPS. A video
transmit path, receive path, and auxiliary functions, such as a PLL, input with an adjustable signal clamping level, along with the
a ∑-∆ DAC, a serial control port, and a cable amplifier interface. 10-bit ADC, allow the AD9878 to process an NTSC and a QAM
channel simultaneously.
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a 12-bit The programmable ∑-∆ DAC can be used to control external
current output DAC. components, such as variable gain amplifiers (VGAs) or voltage-
controlled tuners. The CA port provides an interface to the
The receive path contains a 10-bit ADC and dual 12-bit ADCs. AD832x family of programmable gain amplifier (PGA) cable
All internally required clocks and an output system clock are drivers, enabling host processor control via the MxFE serial
generated by the PLL from a single crystal or clock input. port (SPORT).
QUADRATURE
DATA MODULATOR DAC GAIN CONTROL FSADJ
ASSEMBLER FIR LPF CIC LPF
SINC–1
6 12 12 COS BYPASS
TxIQ[5:0] I 4 4 12
MUX DAC Tx OUTPUT
SINC–1
12 12
TxSYNC Q 4 4
SIN (fSYSCLK)
(fOSCIN)
(fIQCLK) DDS
PLL
÷4 ÷4 OSCIN × M
XTAL
MCLK
(fMCLK)
REFCLK ÷R OSCIN
FLAG0
8
Σ-∆ INPUT Σ-∆ Σ-∆ OUTPUT
3 CA
CA PORT
INTERFACE
÷8
PROFILE
PROFILE
SELECT FLAG[2:1]
4 SERIAL ÷2
SDIO INTERFACE
(fOSCIN) 10
ADC IF10 INPUT
5 5
IF10[4:0] IF10 MUX
RxSYNC ÷2
Rx PORT
(fOSCIN) 12
ADC MUX IF12B INPUT
12 12 VIDEO IN
IF12[11:0] IF12 MUX
12
ADC MUX IF12A INPUT
AD9878 – +
CLAMP LEVEL DAC
03277-007
Figure 23. AD9878 Block Diagram
AD9878
tSU
MCLK
tHU
TxSYNC
03277-008
TxIQ TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6] TxI[5:0]
Figure 24. Tx Timing Diagram
TRANSMIT PATH to the sample rate increase, the half-band filters provide the
low-pass filtering characteristics necessary to suppress the spectral
The transmit path contains an interpolation filter, a complete images between the original sampling frequency and the new
quadrature digital upconverter, an inverse sinc filter, and a 12-bit (16× higher) sampling frequency.
current output DAC. The maximum output current of the DAC is
set by an external resistor. The Tx output PGA provides additional HALF-BAND FILTERS (HBFs)
transmit signal level control. The transmit path interpolation HBF 1 and HBF 2 are both interpolating filters, each of which
filter provides an upsampling factor of 16 with an output signal doubles the sampling rate. Together, HBF 1 and HBF 2 have
bandwidth as high as 4.35 MHz for <1 dB droop. Carrier 26 taps and increase the sampling rate by a factor of 4
frequencies up to 65 MHz with 26 bits of frequency tuning (4 × fIQCLK or 8 × fNYQ).
resolution can be generated by the direct digital synthesizer
(DDS). The transmit DAC resolution is 12 bits, and it can run at In relation to phase response, both HBFs are linear phase filters.
sampling rates of up to 232 MSPS. Analog output scaling from As such, virtually no phase distortion is introduced within the pass
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when band of the filters. This is an important feature, because phase dis-
reduced output levels are required. tortion is generally intolerable in a data transmission system.
DATA ASSEMBLER CASCADE INTEGRATOR COMB (CIC) FILTER

The AD9878 data path operates on two 12-bit words, the I and Q The CIC filter is configured as a programmable interpolator
components, that form a complex symbol. The data assembler and provides a sample rate increase by a factor of 4. The
builds the 24-bit complex symbol from four consecutive 6-bit frequency response of the CIC filter is given by:
words read over the TxIQ [5:0] bus. These words are strobed
⎡ 1 1 − e − j (2 πf ( 4 ) ) ⎤ ⎡⎛ 1 ⎞ sin (4 πf ) ⎤
3 3
into the data assembler synchronous to the master clock (MCLK).
H ( f ) − ⎢⎛⎜ ⎞⎟ ⎥ = ⎢⎜ ⎟ ⎥
⎢⎣⎝ 4 ⎠ sin (πf ) ⎥⎦
A high level on TxSYNC signals the start of a transmit symbol.
⎢⎣⎝ 4 ⎠ 1 − e
j 2 πf
⎥⎦
The first two 6-bit words of the symbol form the I component;
the second two 6-bit words form the Q component. Symbol COMBINED FILTER RESPONSE
components are assumed to be in twos complement format. The
The combined frequency response of the HBF and CIC filters
timing of the interface is fully described in the Transmit Timing
limits the input signal bandwidth that can be propagated through
section. The I/Q sample rate fIQCLK puts a bandwidth limit on the
the AD9878.The usable bandwidth of the filter chain limits the
maximum transmit spectrum. This is the familiar Nyquist limit
maximum data rate that can be propagated through the AD9878.
(hereafter referred to as fNYQ) and is equal to half fIQCLK.
A look at the pass-band detail of the combined filter response
TRANSMIT TIMING (Figure 25) indicates that to maintain an amplitude error of
The AD9878 has a master clock and expects 6-bit, multiplexed 1 dB or less, signal bandwidth is restricted to about 60% or less
TxIQ data upon each rising edge (see Figure 24). Transmit of fNYQ.
symbols are framed with the TxSYNC input. TxSYNC high Max BW (1dB droop) = 0.60 * fMCLK/8
indicates the start of a transmit symbol. Four consecutive 6-bit
data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB). Thus, in order to keep the bandwidth of the data in the flat
portion of the filter pass band, the user must oversample the
INTERPOLATION FILTER baseband data by at least a factor of two prior to presenting it to
Once through the data assembler, the IQ data streams are fed the AD9878. Note that without oversampling, the Nyquist
through a 4× FIR low-pass filter and a 4× cascaded integrator bandwidth of the baseband data corresponds to fNYQ. As such,
comb (CIC) low-pass filter. The combination of these two filters the upper end of the data bandwidth suffers 6 dB or more of
results in the sample rate increasing by a factor of 16. In addition attenuation due to the frequency response of the digital filters.
Furthermore, if the baseband data applied to the AD9878 has
AD9878
been pulse shaped, there is an additional concern. Typically, Tx SIGNAL LEVEL CONSIDERATIONS
pulse shaping is applied to the baseband data via a filter with a The quadrature modulator itself introduces a maximum gain of
raised cosine response. In such cases, an α value is used to modify 3 dB in signal level. To visualize this, assume that both the I and
the bandwidth of the data, where the value of α is such that Q data are fixed at the maximum possible digital value, x. Then,
0 < α < 1. the output of the modulator, z, is
A value of 0 causes the data bandwidth to correspond to the

[
z = x cos (ωt ) − x sin (ωt ) ]
Nyquist bandwidth. A value of 1 causes the data bandwidth to Q
be extended to twice the Nyquist bandwidth. Thus, with 2× over-
sampling of the baseband data and α = 1, the Nyquist bandwidth X Z
I
of the data corresponds with the I/Q Nyquist bandwidth. As stated X
03277-010
earlier, this results in problems near the upper edge of the data
bandwidth due to the frequency response of the filters. The
maximum value of α that can be implemented is 0.45, because the Figure 26. 16-Quadrature Modulation
data bandwidth becomes
It can be shown that |z| assumes a maximum value of
1 2 (1 + α ) f NYQ = 0.725 f NYQ z = x 2 + x 2 = x 2 (a gain of +3 dB). However, if the
same number of bits represent |z| and x, an overflow occurs.
which puts the data bandwidth at the extreme edge of the flat
To prevent this, an effective −3 dB attenuation is internally
portion of the filter response.
implemented on the I and Q data path:
If a particular application requires an α value between 0.45 and 1,
the user must oversample the baseband data by at least a factor of z = 1 2 +1 2 = x
4. Over the frequency range of the data to be transmitted, the
combined HBF 1, HBF 2, and CIC filters introduce a worst-case The following example assumes a peak rms level of 10 dB:
droop of less than 0.2 dB. Maximum Symbol Component Input Value =
1
± 2047 LSBs − 0.2 dB = ± 2000 LSBs
0
Maximum Complex Input RMS Value =
–1 2000 LSBs ± 6 dB − Peak rms (dB ) = 1265 LSBs rms
MAGNITUDE (dB)
–2
The maximum complex input rms value calculation uses both
I and Q symbol components that add a factor of two (6 dB)
–3
to the formula. Table 10 shows typical I-Q input test signals
–4 with amplitude levels related to 12-bit full scale (FS).
–5
03277-009
Table 10. I-Q Input Test Signals

–6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Analog Modulator
FREQUENCY RELATIVE TO I/Q NYQ BW Output Digital Input Input Level Output Level
Figure 25. Cascaded Filter Pass Band Single Tone I = cos(f) FS − 0.2 dB FS − 3.0 dB
(fC − f) Q = cos(f + 90°) FS − 0.2 dB
DIGITAL UPCONVERTER = −sin(f)
The digital quadrature modulator stage following the CIC filters Single Tone I = cos(f) FS − 0.2 dB FS − 3.0 dB
is used to frequency shift (upconvert) the baseband spectrum of (fC + f) Q = cos(f + 270°) FS − 0.2 dB
the incoming data stream to the desired carrier frequency. The = +sin(f)
carrier frequency is controlled numerically by a direct digital Dual Tone I = cos(f) FS − 0.2 dB FS
synthesizer (DDS). The DDS uses the internal system clock FS − 0.2 dBFS
(fSYSCLK) to generate the desired carrier frequency with a high (fC ± f) Q = cos(f + 180°) FS − 0.2 dB
= −cos(f) or
degree of precision. The carrier is applied to the I and Q
Q = +cos(f)
multipliers in a quadrature fashion (90° phase offset) and
summed to yield a data stream that is the modulated carrier. The
modulated carrier becomes the 12-bit sample sent to the DAC.
AD9878
Tx THROUGHPUT AND LATENCY capacitance and inductance. The load can be a simple resistor to
Data inputs affect the output fairly quickly, but remain effective ground, an op amp current-to-voltage converter, or a transformer-
due to the AD9878 filter characteristics. Data transmit latency coupled circuit. It is best not to directly drive a highly reactive
through the AD9878 is easiest to describe in terms of fSYSCLK clock load, such as an LC filter. Driving an LC filter without a
cycles (4 × fMCLK). The numbers provided indicate the number of transformer requires that the filter be doubly terminated for
fSYSCLK cycles before the AD9878 output responds to a change in best performance—that is, both the filter input and output should
the input. be resistively terminated with the appropriate values. The parallel
combination of the two terminations determines the load that
Latency of I/Q data from the time it enters the data assembler the AD9878 sees for signals within the filter pass band. For
(AD9878 input) to the time of DAC output is 119 fSYSCLK clock example, a 50 Ω terminated input/output low-pass filter looks
cycles (29.75 fMCLK cycles). DC values applied to the data assembler like a 25 Ω load to the AD9878. The output compliance voltage
input take up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to of the AD9878 is −0.5 V to +1.5 V. Any signal developed at the
propagate and settle at the DAC output. DAC output should not exceed 1.5 V; otherwise, signal distortion
results. Furthermore, the signal can extend below ground as much
Frequency hopping is accomplished via changing the PROFILE as 0.5 V without damage or signal distortion. The AD9878 true
input pin. The time required to switch from one frequency to and complement outputs can be differentially combined for
another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles). common-mode rejection using a broadband 1:1 transformer.
DAC Using a grounded center tap results in signals at the AD9878 DAC
A 12-bit digital-to-analog converter (DAC) is used to convert the output pins that are symmetrical about ground. As previously
digitally processed waveform into an analog signal. The worst- mentioned, by differentially combining the two signals, the user
case spurious signals due to the DAC are the harmonics of the can provide some degree of common-mode signal rejection.
fundamental signal and their aliases (see the Analog Devices
DDS tutorial at www.analog.com/dds). The conversion process A differential combiner can consist of a transformer or an
produces aliased components of the fundamental signal at op amp. The object is to combine or amplify the difference
n × f SYSCLK ± f CARRIER (n = 1, 2, 3). These are typically filtered between only two signals and to reject any common—usually
undesirable—characteristics, such as 60 Hz hum or clock
with an external RLC filter at the DAC output. It is important
feedthrough, that is equally present on both signals.
for this analog filter to have a sufficiently flat gain and linear
phase response across the bandwidth of interest to avoid AD9878 AD832x
modulation impairments. A relatively inexpensive seventh-
order, elliptical, low-pass filter is sufficient to suppress the DAC Tx
LOW-PASS
FILTER
aliased components for HFC network applications. 75Ω
CA 3
The AD9878 provides true and complement current outputs. The CA_EN
VARIABLE GAIN
full-scale output current is set by the RSET resistor at Pin 49 and CA_DATA
03277-011
CA_CLK CABLE DRIVER
the DAC gain register. Assuming maximum DAC gain, the value AMPLIFIER
of RSET for a full-scale IOUT is determined using the equation: Figure 27. Cable Amplifier Connection
R SET = 32 V DACRSET I OUT = 39.4 I OUT Connecting the AD9878 true and complement outputs to the
differential inputs of the programmable gain cable drivers
For example, if a full-scale output current of 20 mA is desired, AD8321/AD8323 or AD8322/AD8327 (see Figure 27)
then RSET = (39.4/0.02), or approximately 2 kΩ. provides an optimized solution for the standard compliant
cable modem upstream channel. The cable driver’s gain
The following equation calculates the full-scale output current,
can be programmed through a direct 3-wire interface
including the programmable DAC gain control:
using the AD9878 profile registers.
I OUT = 39.4 R SET × 10 (−7.5 + 0.5 N GAIN ) 20 PROGRAMMING THE AD8321/AD8323 OR
AD8322/AD8327/AD8238 CABLE-DRIVER
where NGAIN is the value of DAC fine gain control [3:0].
AMPLIFIERS
The full-scale output current range of the AD9878 is 4 to Users can program the gain of the AD832x family of cable-driver
20 mA. Full-scale output currents outside this range degrade amplifiers via the AD9878 cable amplifier control interface. Two
SFDR performance. SFDR is also slightly affected by output (one per profile) 8-bit registers within the AD9878 store the gain
matching—that is, the two outputs should be terminated equally value to be written to the serial 3-wire port. Typically, either the
for best SFDR performance. The output load should be located AD8321/AD8323 or AD8322/AD8327 variable gain cable
as close as possible to the AD9878 package to minimize stray amplifiers are connected to the chip’s 3-wire cable amplifier
AD9878
interface. The Tx gain control select bit in Register 0x0F changes 30% of fSYSCLK. For a 65 MHz carrier, the system clock required is
the interpretation of the bits in Register 0x13, Register 0x17, above 216 MHz. The OSCIN multiplier function maintains
Register 0x1B, and Register 0x1F. See Figure 28 and the clock integrity, as evidenced by the part’s excellent phase noise
Cable-Driver Gain Control section. characteristics and low clock-related spur in the output spectrum.
8 tMCLK 8 tMCLK
4 tMCLK External loop filter components, consisting of a series resistor
4 tMCLK
8 tMCLK (1.3 kΩ) and capacitor (0.01 µF), provide the compensation
CA_EN
zero for the OSCIN multiplier PLL loop. The overall loop
CA_CLK
performance is optimized for these component values.
03277-012
CA_DATA MSB LSB CLOCK AND OSCILLATOR CIRCUITRY
Figure 28. Cable Amplifier Interface Timing The AD9878’s internal oscillator generates all sampling clocks
from a simple, low cost, parallel resonance, fundamental fre-
Data transfers to the programmable gain cable-driver amplifier quency quartz crystal. Figure 29 shows how the quartz crystal is
are initiated by the following conditions: connected between OSCIN (Pin 61) and XTAL (Pin 60) with
• Power-Up and Hardware Reset: Upon initial power-up and parallel resonant load capacitors, as specified by the crystal
every hardware reset, the AD9878 clears the contents of the manufacturer. The internal oscillator circuitry can also be
gain control registers to 0, which defines the lowest gain overdriven by a TTL-level clock applied to OSCIN with
setting of the AD832x. Thus, the AD9878 writes all 0s out XTAL left unconnected.
of the 3-wire cable amplifier control interface. f OSCIN = f MCLK × M
• Software Reset: Writing a 1 to Bit 5 of Address 0x00 initiates
An internal PLL generates the DAC sampling frequency, fSYSCLK,
a software reset. Upon a software reset, the AD9878 clears
by multiplying the OSCIN frequency by M. The MCLK signal
the contents of the gain control registers to 0 for the lowest
(Pin 23), fMCLK, is derived by dividing fSYSCLK by 4.
gain and sets the profile select to 0. The AD9878 writes all 0s
out of the 3-wire cable amplifier control interface if the f SYSCLK = f OSCIN × M
gain is previously on a different setting (different from 0).
f MCLK = f OSCIN × M 4
• Change in Profile Selection: The AD9878 samples the
PROFILE input pin together with the two profile select bits An external PLL loop filter (Pin 57), consisting of a series resistor
and writes to the AD832x gain control registers when a and ceramic capacitor (Figure 29: R1 = 1.3 kΩ, C12 = 0.01 µF),
change in profile and gain is determined. The data written is required for stability of the PLL. Also, a shield surrounding
to the cable-driver amplifier comes from the AD9878 gain these components is recommended to minimize external noise
control register associated with the current profile. coupling into the PLL’s voltage-controlled oscillator input (guard
trace connected to AVDDPLL).
• Write to the AD9878 Cable-Driver Amplifier Control
Registers: The AD9878 writes gain control data associated Figure 23 shows that ADCs are either sampled directly by a
with the current profile to the AD832x when the selected low jitter clock at OSCIN or by a clock that is derived from the
AD9878 cable-driver amplifier gain setting is changed. Once PLL output. Operating modes can be selected in Register 0x08.
a new, stable gain value is detected (48 to 64 MCLK cycles Sampling the ADCs directly with the OSCIN clock requires that
after initiation) a data write starts with CA_EN going low. MCLK is programmed to be twice the OSCIN frequency.
The AD9878 always finishes a write sequence to the cable-
driver amplifier once it is started. The logic controlling data PROGRAMMABLE CLOCK OUTPUT REFCLK
transfers to the cable-driver amplifier uses up to The AD9878 provides an auxiliary output clock on Pin 69,
200 MCLK cycles and is designed to prevent erroneous REFCLK. The value of the MCLK divider bit field, R, determines
write cycles from occurring. its output frequency, as shown in the following equations:
OSCIN CLOCK MULTIPLIER f REFCLK = f MCLK R , for R = 2 to 63

The AD9878 can accept either an input clock into the OSCIN
f REFCLK = f OSCIN , for R = 0
pin or a fundamental-mode crystal across the OSCIN and
XTAL pins as the device’s main clock source. The internal PLL
In its default setting (0x00 in Register 0x01), the REFCLK pin
then generates the fSYSCLK signal from which all other internal
provides a buffered output of fOSCIN.
signals are derived. The DAC uses fSYSCLK as its sampling clock.
For DDS applications, the carrier is typically limited to about
AD9878
CP2 CP1
10µF 10µF
C4 C5 C6 C1 C2 C3
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
CP1
10µF
REFB12A
REFB12B
C1 C2 C3
REFT12A
REFT12B
VIDEO IN
AGND10
AVDD10
0.1µF 0.1µF 0.1µF
IF12A+
IF12B+
IF12A–
IF12B–
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
IF10+
IF10–
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DRGND 1 75 REFT10
DRVDD 2 74 REFB10
(MSB) IF12(11) 3 73 AGND10
IF12(10) 4 72 AVDD10
IF12(9) 5 71 DRVDD
IF12(8) 6 70 DRGND
IF12(7) 7 69 REFCLK
IF12(6) 8 68 SIGDELT
IF12(5) 9 67 FLAG1
IF12(4) 10 66 FLAG2
IF12(3) 11 65 CA_EN
AD9878 C10
IF12(2) 12 64 CA_DATA 20pF
IF12(1) 13 TOP VIEW 63 CA_CLK
IF12(0) 14 (Not to Scale) 62 DVDDOSC C11
(MSB) IF10(4) 15 61 OSCIN 20pF
IF10(3) 16 60 XTAL
IF10(2) 17 59 DGNDOSC
IF10(1) 18 58 AGNDPLL GUARD TRACE
IF10(0) 19 57 PLLFILT
RxSYNC 20 56 AVDDPLL R1 C12
1.3kΩ 0.01µF
DRGND 21 55 DVDDPLL
DRVDD 22 54 DGNDPLL
MCLK 23 53 AVDDTx
DVDD 24 52 Tx+
DGND 25 51 Tx–
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TxSYNC
TxIQ(4)
TxIQ(3)
TxIQ(2)
TxIQ(1)
TxIQ(0)
RESET
PROFILE
SDIO
SDO
REFIO
(MSB) TxIQ(5)
DVDD
DGND
DVDD
DGND
DVDD
DGND
SCLK
PWRDN
CS
DGNDTx
DVDDTx
FSADJ
AGNDTx
C13
03277-013
RSET
0.1µF
4.02Ω
Figure 29. Basic Connection Diagram
AD9878
POWER-UP SEQUENCE RESET
Upon initial power-up, the RESET pin should be held low until the To initiate a hardware reset, the RESET pin should be held low
power supply is stable (see Figure 30). Once RESET is deasserted, for at least 100 ns. All internally generated clocks, except REFCLK,
the AD9878 can be programmed over the serial port. The on- stop during reset. The rising edge of RESET resets the PLL clock
chip PLL requires a maximum of 1 ms after the rising edge of multiplier and reinitializes the programmable registers to their
RESET or a change of the multiplier factor (M) to completely default values. The same sequence as described in the Power-Up
settle. It is recommended that the PWRDN pin is held low during Sequence section should be followed after a reset or change in M.
the reset and PLL settling time. Changes to ADC clock select
A software reset (writing 1 into Bit 5 of Register 0x00) is func-
(Register 0x08) or System Clock Divider N (Register 0x01) should
tionally equivalent to a hardware reset, but does not force
be programmed before the rising edge of PWRDN. Once the PLL
Register 0x00 to its default value.
is frequency locked and after the PWRDN pin is brought high,
transmit data can be sent reliably. If the PWRDN pin cannot be TRANSMIT POWER-DOWN
held low throughout the reset and PLL settling time period, A low level on the PWRDN pin stops all clocks linked to the
the power-down digital Tx bit, or the PWRDN pin, should be digital transmit data path and resets the CIC filter. Deasserting
pulsed after the PLL has settled. This ensures correct transmit PWRDN reactivates all clocks. The CIC filter is held in a reset
filter initialization. state for 80 MCLK cycles after the rising edge of PWRDN to
allow for flushing of the half-band filters with new input data.
VS
Transmit data bursts should be padded with at least 20 symbols
of null data directly before the PWRDN pin is deasserted.
RESET
Immediately after the PWRDN pin is deasserted, the transmit
1ms MIN.
burst should start with a minimum of 20 null data symbols (see
03277-014
PWRDN 5MCLK MIN. Figure 31). This avoids unintended DAC output samples caused
by the transmit path latency and filter settling time.
Figure 30. Power-Up Sequence for Tx Data Path
Software power-down digital Tx (Bit 5 in Register 0x02) is func-
tionally equivalent to the hardware PWRDN pin and takes effect
immediately after the last register bit is written over the serial port.
PWRDN 5MCLK MIN.
20 NULL SYMBOLS DATA SYMBOLS 20 NULL SYMBOLS

TxIQ 0 0 0 0 0 0 0 0
03277-015
TxSYNC
Figure 31. Timing Sequence to Flush Tx Data Path
AD9878
∑-∆ OUTPUTS RECEIVE PATH (Rx)
An on-chip ∑-∆ output provides a digital logic bit stream with The AD9878 includes three high speed, high performance ADCs.
an average duty cycle that varies between 0% and (255/256)%, The 10-bit and dual 12-bit direct-IF ADCs deliver excellent under-
depending on the programmed code, as shown in Figure 32. sampling performance with input frequencies as high as 70 MHz.
The sampling rate can be as high as 29 MSPS. The ADC sampling
8 tMCLK
256 × 8 tMCLK
frequency can be derived directly from the OSCIN signal, or from
the on-chip OSCIN multiplier. For highest dynamic performance,
00h
choose an OSCIN frequency that can be directly used as the
01h
ADC sampling clock. Digital 12-bit ADC outputs are multiplexed
02h to one 12-bit bus, clocked by a frequency (fMCLK) four times the
80h sampling rate. The IF ADCs use a multiplexer to a 12-bit interface
with an output word rate of fMCLK.
FFh
256 × 8 tMCLK
03277-016
IF10 AND IF12 ADC OPERATION
8 tMCLK The IF10 and IF12 ADCs have a common architecture and
Figure 32. ∑-∆ Output Signals share several characteristics from an applications standpoint.
Most of the information in the following section is applicable to
This bit stream can be low-pass filtered to generate a both IF ADCs; differences, where they exist, are highlighted.
programmable dc voltage of
Input Signal Range and Digital Output Codes
[
VDC = (∑ -∆ Code 256 )× VH + VL ] The IF ADCs have differential analog inputs labeled IF+ and IF−.
The signal input, VAIN, is the voltage difference between the two
where:
input pins, VAIN = VIF+ − VIF−. The full-scale input voltage range is
V H = V DRVDD − 0.6 V determined by the internal reference voltages, REFT and REFB,
V L = 0. 4 V which define the top and bottom of the scale. The peak input
voltage to the ADC is the difference between REFT and REFB,
In cable set-top box applications, the output can be used to which is 1 V p-p. This results in an ADC full-scale input voltage
control external variable gain amplifiers or RF tuners. A of 2 VPPD. The digital output codes are straight binary and are
single-pole, RC, low-pass filter provides sufficient filtering shown in Table 11.
(see Figure 33). In more demanding applications, where
additional gain, level-shift, or drive capability is required,
consider using a first- or second-order filter (see Figure 34). Table 11. Digital Output Codes
IF12[11:0] Input Signal Voltage
AD9878
8
DAC 111…111 VAIN ≥ +1.0 V
R
CONTROL
Σ-∆ DC (VL TO VH) 111…111 VAIN = +1.0 V − 1 LSB
WORD
C
111…110 VAIN = +1.0 V − 2 LSB
MCLK ÷8 … …
100…001 VAIN = 0 V + 1 LSB
TYPICAL: R = 50kΩ 100…000 VAIN = 0.0 V
03277-017
C = 0.01µF
f–3dB = 1/(2πRC) = 318Hz 011…111 VAIN = 0 V − 1 LSB
… …
Figure 33. ∑-∆ RC Filter
000…001 VAIN = −1.0 V + 2 LSB
C
000…000 VAIN = −1.0 V
AD9878
R1 R 000…000 VAIN < −1.0 V
SIGMA-DELTA
R VOUT
Σ-∆
OP250
VSD C R
VOFFSET
VOUT = (VSD + VOFFSET) (1 + R/R1)/2
TYPICAL: R = 50kΩ
03277-018
C = 0.01µF
f–3dB = 1/(2πRC) = 318Hz
Figure 34. ∑-∆ Active Filter with Gain and Offset
AD9878
Driving the Input Receive Timing
The IF ADCs have differential switched capacitor sample-and- The AD9878 sends multiplexed data to the IF10 and IF12 outputs
hold amplifier (SHA) inputs. The nominal differential input upon every rising edge of MCLK. RxSYNC frames the start of
impedance is 4.0 kΩ||3 pF. This impedance can be used as the each IF10 data symbol. The 10-bit and 12-bit ADCs are read
effective termination impedance when calculating filter transfer completely upon every second MCLK cycle. RxSYNC is high
characteristics and voltage signal attenuation from nonzero source for every second 10-bit ADC data if the 10-bit ADC is not in
impedances. For best performance, additional requirements must power-down mode. The Rx timing diagram is shown in Figure 36.
be met by the signal source. The SHA has input capacitors that
tEE
must be recharged each time the input is sampled. This results in
a dynamic input current at the device input, and demands that REFCLK M/N = 2
tMD tOD
the source has low (<50 Ω) output impedance at frequencies up
to the ADC sampling frequency. Also, the source must have MCLK
settling of better than 0.1% in less than half the ADC clock period.
IF10 DATA IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]
Another consideration for getting the best performance from the
ADC inputs is the dc biasing of the input signal. Ideally, the signal RxSYNC
should be biased to a dc level equal to the midpoint of the ADC
reference voltages, REFT12 and REFB12. Nominally, this level is IF12 DATA IF12A IF12B IF12B IF12B IF12A IF12B
1.2 V. When ac-coupled, the ADC inputs self-bias to this voltage Rx PORT TIMING (DEFAULT MODE: MUXED IF12 ADC DATA)
and require no additional input circuitry. Figure 35 illustrates a tEE
recommended circuit that eases the burden on the signal source
M/N = 2
by isolating its output from the ADC input. The 33 Ω series REFCLK
tMD tOD
termination resistors isolate the amplifier outputs from any
capacitive load, which typically improves settling time. The series MCLK
capacitors provide ac signal coupling, which ensures that the

IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]
ADC inputs operate at the optimal dc-bias voltage. The shunt IF10 DATA
capacitor sources the dynamic currents required to charge the

RxSYNC
SHA input capacitors, removing this requirement from the ADC
buffer. The values of CC and CS should be calculated to IF DATA IF12A OR IF12B IF12A OR IF12B IF12A OR IF12B
03277-020
determine the correct HPF and LPF corner frequencies.
Rx PORT TIMING (OUTPUT DATA FROM ONLY ONE IF12 ADC)
CC
33Ω Figure 36. Rx Port Timing
AIN+
VS CS
CC
33Ω
03277-019
AIN–
Figure 35. Simple ADC Drive Configuration
AD9878
ADC VOLTAGE REFERENCES VIDEO INPUT
The AD9878 has three independent internal references for its For sampling video-type waveforms, such as NTSC and PAL
10-bit and 12-bit ADCs. Both 12-bit and 10-bit ADCs are signals, the video input channel provides black-level clamping.
designed for 2 V p-p input voltages and have their own internal Figure 37 shows the circuit configuration for using the video
reference. Figure 29 shows the proper connections of the REFT channel input (Pin 98). An external blocking capacitor is used
and REFB reference pins. External references might be necessary with the on-chip video clamp circuit to level-shift the input signal
for systems that require high accuracy gain matching between to a desired reference point. The clamp circuit automatically
ADCs, or for improvements in temperature drift and noise senses the most negative portion of the input signal and adjusts
characteristics. External references REFT and REFB must be the voltage across the input capacitor. This forces the black level
centered at AVDD/2, with offset voltages as specified by the of the input signal to be equal to the value programmed in the
following equations: clamp level register (Register Address 0x07).
REFT − 10, − 12 : AVDD 2 + 0.5 V By default, the video input is disabled and disconnected from
both ADCs. By setting Register 0x07, Bit 7 = 1, the video input
REFT − 10, − 12 : AVDD 2 − 0.5 V is enabled and connected to the ADC input as determined by
the state of Reg 0x03, Bit 6 ( 0= ADC12A connected, 1 =
A differential level of 1 V between the reference pins results in a ADC12B connected.)
2 V p-p ADC input level AIN. Internal reference sources can be
powered down when external references are used (Address 0x02).
CLAMP LEVEL + FS/2
AD9878 CLAMP LEVEL

VIDEO INPUT
BUFFER 0.1µF
12
ADC
2mA
CLAMP – +
03277-021
DAC
LEVEL
LPF OFFSET
Figure 37. Video Clamp Circuit Input
AD9878
PCB DESIGN CONSIDERATIONS

Although the AD9878 is a mixed-signal device, the part should be The DVDD portion of the plane carries the current used to power
treated as an analog component. The on-chip digital circuitry is the digital portion of the MxFE to the device. This should be
designed to minimize the impact of digital switching noise on the treated similarly to the 3-VDD power plane and be kept from going
operation of the analog circuits. Following the recommendations underneath the MxFE or analog components. The MxFE should
in this section helps achieve the best performance from the MxFE. largely sit above the AVDD portion of the power plane. The
AVDD and DVDD power planes can be fed from the same low
COMPONENT PLACEMENT noise voltage source; however, they should be decoupled from
The following guidelines for component placement are each other to prevent the noise generated in the DVDD portion
recommended to achieve optimal performance: of the MxFE from corrupting the AVDD supply. This can be done
by using ferrite beads between the voltage source and DVDD, and
• Manage the path of return currents to ensure that high between the source and AVDD. Both DVDD and AVDD should
frequency switching currents from the digital circuits do not have a low ESR, bulk-decoupling capacitor on the MxFE side of
flow into the ground plane under the MxFE or analog circuits. the ferrite as well as low ESR- and ESL-decoupling capacitors on
each supply pin (for example, the AD9878 requires 17 power
• Keep noisy digital signal paths and sensitive receive signal
supply decoupling capacitors). The decoupling capacitors should
paths as short as possible.
be placed as close as possible to the MxFE supply pins. An
• Keep digital (noise-generating) and analog (noise-susceptible) example of proper decoupling is shown in the AD9878 evaluation
circuits as far apart as possible. board’s two-page schematic (Figure 38 and Figure 39).
To best manage the return currents, pure digital circuits that GROUND PLANES
generate high switching currents should be closest to the power In general, if the component placing guidelines discussed earlier
supply entry. This keeps the highest frequency return current can be implemented, it is best to have at least one continuous
paths short and prevents them from traveling over the sensitive ground plane for the entire board. All ground connections should
MxFE and analog portions of the ground plane. Also, these be as short as possible. This results in the lowest impedance return
circuits should be generously bypassed at each device to further paths and the quietest ground connections. If the components
reduce high frequency ground currents. The MxFE should be cannot be placed in a manner that keeps the high frequency
placed adjacent to the digital circuits, such that the ground return ground currents from traversing under the MxFE and analog
currents from the digital sections do not flow into the ground components, it might be necessary to put current-steering
plane under the MxFE. The analog circuits should be placed channels into the ground plane to route the high frequency
furthest from the power supply. The AD9878 has several pins that currents around these sensitive areas. These current-steering
are used to decouple sensitive internal nodes: REFIO, REFB12A, channels should be used only when and where necessary.
REFT12A, REFB12B, REFT12B, REFB10, and REFT10. The
decoupling capacitors connected to these points should have low SIGNAL ROUTING
ESR and ESL, be placed as close as possible to the MxFE, and be The digital Rx and Tx signal paths should be as short as possible.
connected directly to the analog ground plane. The resistor Also, these traces should have a controlled impedance of about
connected to the FSADJ pin and the RC network connected to 50 Ω. This prevents poor signal integrity and the high currents
the PLLFILT pin should also be placed close to the device and that can occur during undershoot or overshoot caused by ringing.
connected directly to the analog ground plane. If the signal traces cannot be kept shorter than about 1.5 inches,
then series termination resistors (33 Ω to 47 Ω) should be placed
POWER PLANES AND DECOUPLING close to all signal sources. It is a good idea to series terminate all
The AD9878 evaluation board (Figure 38 and Figure 39) clock signals at their source, regardless of trace length. The receive
demonstrates a good power supply distribution and decoupling signals are the most sensitive signals on the evaluation board.
strategy. The board has four layers: two signal layers, one ground Careful routing of these signals is essential for good receive path
plane, and one power plane. The power plane is split into a 3-VDD performance. The IF+/IF− signals form a differential pair and
section that is used for the 3 V digital logic circuits, a DVDD should be routed together. By keeping the traces adjacent to each
section that is used to supply the digital supply pins of the other, noise coupled onto the signals appears as common mode
AD9878, an AVDD section that is used to supply the analog and is largely rejected by the MxFE receive input. Keeping the
supply pins of the AD9878, and a VANLG section that supplies driving point impedance of the receive signal low and placing
the higher voltage analog components on the board. The 3-VDD any low-pass filtering of the signals close to the MxFE further
section typically has the highest frequency currents on the power reduces the possibility of noise corrupting these signals.
plane and should be kept the furthest from the MxFE and analog
sections of the board.
5V AD8328
R28 U4 5V AD8328
1kΩ AD8328
RC0603
C117 20 1
Tx_OUT GND5 GND
0.1µF 19 2
AD8328 CC0603
VCC1 VCC
C115 18 3
AGND; 3, 4, 5
R39 TxEN GND1
SMAEDGE 0.1µF 17 4
T6 RAMP GND2
1 43.3Ω 4 3 CC0603 16 5
J8 VOUT+ VIN+
RC0605 15 6
DUTY 2 VOUT– VIN–
2 14 7
CYCLE RC0805 R40 BYP GND3
5 1 C116 CC0603 13 8
86.6Ω
RC0605
V_CLK NC DATAEN CA_EN
R6 S P 0.1µF 12 9
C83 + C84 C110 SLEEP SDATA CA_DATA
500Ω 10µF 0.1µF 0.1µF TOKOB5F C72 11 10
16V CC0805 CC0805 0.1µF GND4 CLK CA_CLK
CC0603
BCASE CA_SLEEP
OSCIN_CLK
AGND; 3, 4, 5 POT1 AGND; 3 Tx_OUT Tx+
C19 R5 AGND; 3, 4, 5
SMA200UP 0.1µF 10kΩ V_CLK; 5 33Ω R11 L16 L15 R38 C114
SMAEDGE T1 2
CW RC0805 37.5Ω TRANSF 1 AD8328 220 220 75Ω 0.01µF
1 1 6 CC0603
J3 A B
2 4 J4 CC0603 3
CC0805 C23 RC0605 LC1210 LC1210 RC0805
U13 C18 EXT_CLK 2 5 JP8
R9 JP1 2 0.1µF C20 C57 C58
R7 NC7SZ04 18pF RC0605 R37
49.9Ω 3 4
RC0805
500Ω 18pF 33pF 18pF
RC0805
CC0603 59Ω
RC0805
OSCIN S P C24 Tx–

CC0805 R12
CC0805
CC0805
CC0805
1 DIP06RCUP 0.1µF L13 L14 R36 C113

3 Y1 37.5Ω 2 75Ω
TRANSF 1 AD8328 220 220 0.01µF CC0603
VAL A B
CC0805 2 3
XTAL LC1210 LC1210 RC0805
JP7
2
C17 DVDDPLL/ RC0805
VCC DRVDD
RESET 1
18pF R31 C69 C66 DVDDOSC U2 RESET
C16 R4 3
33Ω IF10+ 0.1µF 0.1µF R10 SW1 GND C1
CC0603 0.01µF 1.3kΩ AD9878LQFP
CC0603 CC0603 10kΩ 2 4 0.1µF
CC0603
C111 RC0805 AVDDTx Tx– AGNDTx ADM1818-10ART

RC0805 51 50
C21 C22
2 0.1µF CC0603 1 3 U1
AD8138 3 0.1µF 0.1µF
CC0603
CC0603
B A 52
Tx+ FSADJ 49
8138+
1 AVDDTx REFIO
JP31 TRANSF 53 48 AGND; 5
IF10 DGNDPLL PWRDN PWRDN
54 47
AGND; 3, 4, 5 DVDDPLL DVDDTx DVDDTx RESET
SMAEDGE T5 TP4 55 46
1 AVDDPLL DGNDTx SDO, SDIO, CS, SCLK
J13 WHT 56 45
1 6 JP30 C15 R3 PLLFILT SDO SDO
R33 57 44
100kΩ
CC0805
2 VCML 0.01µF 58
AGNDPLL SDIO 43
SDIO
49.9Ω 2 5
CC0603 DGNDOSC CS CS
RC0805
XTAL
C108 59 42
RC0805 3 4 XTAL SCLK SCLK DRVDD PWRDN
20pF 60 41
OSCIN
TP3 TP15 TP6 TP5 TP1 TP2 J2
DIP06RCUP WHT WHT WHT WHT WHT WHT 61
OSCIN DGND4 40
DVDDOSC DVDD4 DVDD RIBBON
R2
R3
R4
R5
R6
R7
R8
R9
JP32 TRANSF 62 39
RCOM
AD8138 1 CA_CLK CA_CLK RESET

8138– A B 63 38 R29 25 26
RP1
3 R32 CA_DATA CA_DATA PROFILE 10kΩ

RC0805
64 37 23 24
1
2 22 R1
3
4
5
6
7
8
9
2 33Ω
CC0603
10
CA_EN CA_EN DGND3 21 22

65 36
C112 RC0805 FLAG2 FLAG2 DVDD3 JP9
IF10– 66 35 19 20
0.1µF FLAG1 FLAG1 DGND2
R26 67 34 PROFILE1 17 18
IF12B+ SIGDELT0 68
SIGDELT DVDD2 33 15 16
CC0603
33Ω TxIQ0
REFCLK REFCLK TxIQ0
69 32 TxIQ1 13 14
C101 RC0805 DRGND TxIQ1
2 0.1µF 70 31 TxIQ2 11 12
AD8138 3 DRVDD DRVDD TxIQ2
8138+ B A 71 30 TxIQ3 9 10
1 AVDD10 TxIQ3
JP25 TRANSF 72 29 TxIQ4 7 8
IF12B AGND10 TxIQ4
HEADER RA RIBBON
73 28 TxIQ5 5 6
AGND; 3, 4, 5 REFB10 TxIQ5
DIGITAL TRANSMIT
SMAEDGE T3 74 27 TxSYNC 3 4
1
+ REFT10 TxSYNC
C11 C13 C14 C12 75 26 1 2
J13 1 6 JP24 AGND1 DGND1
0.1µF 0.1µF 10µF 0.1µF 76 25
BCASE
CC0603
CC0603
CC0603
R27
CC0805
2 VCML 16V 77
IF10B– DVDD1 24
2 5
Figure 38. Evaluation PCB Schematic

49.9Ω
78
IF10B+ MCLK 23
MCLK
RC0805 3 4 C98 DRVDD
20pF 79
AGND10-A DRVDD2 22
DIP06RCUP 80
AVDD10-A DRGND2 21
81
AGND2 RxSYNC 20
RxSYNC
JP26 TRANSF
AD8138 1 AVDD1 IFB0 IFB0
8138– A B 82 19
JP4 3 R25 REFB12B IFB1 IFB1
2 33Ω 83 18
CC0603 + REFT12B IFB2 IFB2
C6 C7 C8 C9 84 17
C102 RC0805 10µF AVDD2 IFB3 IFB3
IF12B– 0.1µF 0.1µF 0.1µF 85 16
BCASE
C91
CC0603
CC0603
CC0603
0.1µF 10V
RC0805
C90 86
AGND3 IFB4 15
IFB4
10µF
CC0805
16V + 0.1µF R15 C87 R16 IF12B– IF0 IF0
10kΩ 87 14
0.1µF 5.11kΩ IF12B+ IF1 IF1
BCASE
88 13
CC0805
AD8138 A_BUFF+ VCML 89
AGND4 IF2 12
IF2
RC0805
AGND; 3, 4, 5 90
AVDD3 IF3 11
IF3
SMAEDGE R18 R17 R14
499Ω 499Ω 33Ω R13 91
REFB12A IF4 10
IF4
1
J12 8138+ 33Ω IF12A+ + REFT12A IF5 IF5
RC0805 RC0805 RC0805 CC0603 C2 C3 C4 C5 92 9
10µF 93
AVDD4 IF6 8
IF6
2 C86 RC0805 0.1µF 0.1µF 0.1µF
BCASE
CC0603
CC0603
CC0603
U9 6 10V AGND5 IF7 IF7

2 0.1µF 94 7
5 AD8138 3 IF12A– IF8 IF8
VEE B A 95 6
8 1
+IN JP21 TRANSF 96
IF12A+ IF9 5
IF9
R24 VO– 2 IF12A AGND6 IF10 IF10
49.9Ω AGND; 3, 4, 5 T2 97 4 IFB[0:4]
AD8138 VOC SMAEDGE VIDEO IN IF11 IF11
DIP06RCUP 98 3
1 VO+ 1 AGND7 DRVDD1 IF[0:11]
RC0805
–IN 99 2
C88 J11 1 6 JP22 AVDD5 DRGND1
VCC 4 R20 100 1
47pF
CC0805
2 VCML AVDD
49.9Ω 2 5
R23 3 R22
CC1206
RC0805 3 4 C92
523Ω 499Ω 20pF
RC0805 RC0805 VIDEO IN
C95 AGND; 3, 4, 5
A_BUFF– 47pF C10
SMAEDGE R2
C96 C97 R21 33Ω 0.1µF
CC1206
10µF JP23 1
0.1µF 33Ω AD8138 1 TRANSF J1
16V + A B RC0805 CC0603
RC0805 3 R19
BCASE
CC0805
2 2 R1
CC0603
33Ω
75Ω
RC07CUP
C94 RC0805
8138– IF12A–
0.1µF
03277-038
AD9878
AD9878
TP20
CLR
L17 VAL
LC1210
V_CLK
C89
10µF + C93
16V 0.1µF
BCASE CC0805
TP18
CLR
L7 VAL AVDD
LC1210
C59
10µF + C62 C85 C76 C74 C71 C68 C65
16V 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
BCASE CC0805 CC0603 CC0603 CC0603 CC0603 CC0603 CC0603 P1
TP17 1 RJ45
CLR AVDDTx SCS 2
L9 VAL
LC1210 SSCLK 3
C61
10µF + C64 C67 C70 C73 C75 SSDIO 4
16V 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF SDOPC 5
BCASE CC0805 CC0603 CC0603 CC0603 CC0805
6
TP16 J5 7
CLR RIBBON 8
3.3V_ANA L8 VAL HDR040RA
LC1210
AVDDPLL
C60
10µF + C63 1 2 9 10 11 12
16V 0.1µF 3 4
BCASE CC0805
TP14 5 6
CLR 7 8
ABUFF– L11 VAL
A_BUFF– 9 10
LC1210
C78 11 12 J6
10µF +
C81 13 14 DCN2 5 RPT
0.1µF R34
3
16V CC0805
15 16
BCASE MCLK 1kΩ 1
TP12 17 18 AGND; 3, 4, 5 INVERT CLK 14
B
SMAEDGE R35 2
CLR 19 20 RC0603
ABUFF+ L10 VAL 33Ω A 15
A_BUFF+ 21 22 J7 R8 JP3 3
LC1210 1 RC0603 16
DEL_CLK
100Ω
1
C77
JP5 2
23 24 2 4
+
1
10µF C80 17
25 26 RC0603
JP2 0.1µF 5
16V 18
B
AD8328 BCASE CC0805 27 28

6
CA_SLEEP DVDD
TP13 29 30 19
DIGITAL RECEIVE
A
7
DEL_CLK
3.3V_ANA TB1 1 CLR 31 32

L12 VAL 20
3
JP6 2
5V_AD8328 33 34 8
GND TB1 2 LC1210 21
C79 35 36 9
+ C82
9
16
15
14
13
12
11
10
–5V_ANA TB1 3 10µF 37 38 22

16V 0.1µF 10
BCASE CC0805 39 40 23
GND TB1 4 11
NC7SZ04
1
2
3
4
5
6
7
8
24
RP4 22
PC PARALLEL PORT
9
9
12
10
11
12
13
14
15
16
10
11
12
13
14
15
16
+5V_ANA TB1 5 TP19 AGND; 3
25
POWER
CLR 5V_BUFF; 5 13
GND TB1 6 L1 VAL DVDD
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
5V LC1210 2 4
RP3 22
RP2 22
5V_DIG TB1 7 C25
3.3V_DIG 10µF + C28 C31 C34 C37 5V_BUFF U3
3.3V_DIG TB1 8 0.1µF 0.1µF 0.1µF 0.1µF SDO
16V CC0805 CC0603 CC0603 CC0603
BCASE
22
22
22
22
24
23
14
15
16
17
18
19
20
21
13
24
23
14
15
16
18
19
20
21
13
24
23
21
20
19
18
17
16
15
14
13
24
23
21
20
19
18
17
16
15
14
13
TP7
CLR
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B4
B3
B2
B1
B0
B0
B1
B2
B3
B4
B5
B6
B7
B0
B1
B2
B4
B5
B6
B7
L2 VAL DRVDD
NC
NC
NC
NC
OE
OE
OE
OE
LC1210
GND3
GND3
GND3
GND3
VCCB
VCCB
VCCB
VCCB
C26
10µF + C29 C32 C35 C38 C39
16V 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
U5
U6
U7
U8
TSSOP24
TSSOP24
TSSOP24
TSSOP24
TP8 DVDDPLL/
74LVXC3245
74LVXC3245 B5 17
74LVXC3245
CLR
Figure 39. Evaluation PCB Schematic (Continued)

L4 VAL DVDDOSC
LC1210
VCCA
T/R
A7
A6
A5
A4
A3
A2
A1
A0
GND1
GND2
VCCA
T/R
A7
A6
A5
A4
A3
A2
A1
A0
GND1
GND2
VCCA
T/R
A0
A1
A2
A3
A4
A5
A6
A7
GND1
GND2
VCCA
T/R
A0
A1
A2
A3
A4 74LVXC3245 B3
A5
A6
A7
GND1
GND2
C40
+
1
2
9
8
7
6
5
4
3
1
2
9
8
7
6
5
4
3
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10µF C43 C52 C49 C46
10
11
12
10
11
12
10
11
12
10
11
12
3.3V_BUFF
16V 0.1µF 0.1µF 0.1µF 0.1µF
BCASE CC0805 CC0603 CC0603 CC0605
9
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
TP9
8
7
6
5
CLR
L3 VAL DVDDTx
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
LC1210
RP6 22
RP5 22
C27
1
2
3
4
RP7 22
10µF + C30 C33 C36

16V 0.1µF 0.1µF 0.1µF
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
BCASE CC0805 CC0603 CC0603

2
IF[0:11] A B
1 3 IFB4
CS
TP10
SDIO
SCLK
CLR IF0
L6 VAL 3.3V_BUFF
SDOPC
MCLK
JP13
LC1210
RxSYNC
C42 IFB[0:4]
DEL_CLK
10µF + C45 C56 C54 C51 C48

16V 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
TP11
CLR
L5 VAL 5V_BUFF
LC1210
C41
10µF + C44 C47 C50 C55 C53 C100
16V 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
BCASE CC0805 CC0603 CC0603 CC0603 CC0603 CC0603
03277-039
AD9878
03277-040
Figure 40. Evaluation PCB—Top Assembly
03277-041
Figure 41. Evaluation PCB—Bottom Assembly
AD9878
03277-042
Figure 42. Evaluation PCB Layout—Top Layer
03277-043
Figure 43. Evaluation PCB Layout—Bottom Layer
AD9878
03277-044
Figure 44. Evaluation PCB—Power Plane
03277-045
Figure 45. Evaluation PCB—Ground Plane
AD9878
OUTLINE DIMENSIONS
16.00 BSC SQ
1.60 MAX
14.00 BSC SQ
0.75 100 76
1 75
0.60
0.45 PIN 1
TOP VIEW 12.00

(PINS DOWN) REF
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0.15 0° 25 51
SEATING 26 50
0.05 0.08 MAX
PLANE COPLANARITY VIEW A 0.27
0.50 0.22
VIEW A BSC 0.17
ROTATED 90° CCW LEAD PITCH
COMPLIANT TO JEDEC STANDARDS MS-026BED
Figure 46. 100-Lead Low Profile Quad Flat Package [LQFP]

(ST-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9878BST −40°C to +85°C 100-LQFP ST-100
AD9878BSTZ1 −40°C to +85°C 100-LQFP ST-100
AD9878-EB Evaluation Board
1
Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
C03277–0–3/05(A)

Mixed-Signal Front End For Broadband Applications AD9878: Features Functional Block Diagram

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Mixed-Signal Front End For Broadband Applications AD9878: Features Functional Block Diagram

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Formati disponibili

Mixed-Signal Front End

for Broadband Applications

232 MHz quadrature digital upconverter

8-bit ∑-∆ auxiliary DAC

Absolute Maximum Ratings............................................................ 7 Interpolation Filter..................................................................... 21

Explanation of Test Levels ........................................................... 7 Half-Band Filters (HBFs) .......................................................... 21

Thermal Characteristics .............................................................. 7 Cascade Integrator Comb (CIC) Filter.................................... 21

ESD Caution.................................................................................. 7 Combined Filter Response........................................................ 21

Pin Configuration and Function Descriptions............................. 8 Digital Upconverter ................................................................... 22

Typical Performance Characteristics ........................................... 10 Tx Signal Level Considerations ................................................ 22

Terminology .................................................................................... 13 Tx Throughput and Latency ..................................................... 23

Register Bit Definitions.................................................................. 14 DAC.............................................................................................. 23

Register 0x00—Initialization .................................................... 15 Programming the AD8321/AD8323 or

5/03—Revision 0: Initial Version

ABSOLUTE MAXIMUM RATINGS

II. Parameter is guaranteed by design and/or characterization

III. Parameter is a typical value only.

N/A. Test level definition is not applicable.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 3. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

–30 MAGNITUDE (dB) –30

Integral Nonlinearity Error (INL) Aperture Jitter

REGISTER BIT DEFINITIONS

SERIAL INTERFACE FOR REGISTER CONTROL

Figure 19. Timing Diagram for Register Write

transfer. The first eight SCLK rising edges of each communication

SDIO R/W N1 N0 A4 A3 A2 A1 A0 D7n D6n D20 D10 D00

SDO D7n D6n D20 D10 D00

Figure 21. Serial Register Interface Timing, MSB-First Mode

CS INSTRUCTION CYCLE DATA TRANSFER CYCLE

SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D6n D7n

SDO D00 D10 D20 D6n D7n

Figure 22. Serial Register Interface Timing, LSB-First Mode

Figure 23. AD9878 Block Diagram

Figure 24. Tx Timing Diagram

DATA ASSEMBLER CASCADE INTEGRATOR COMB (CIC) FILTER

A value of 0 causes the data bandwidth to correspond to the

Table 10. I-Q Input Test Signals

OSCIN CLOCK MULTIPLIER f REFCLK = f MCLK R , for R = 2 to 63

Figure 29. Basic Connection Diagram

PWRDN 5MCLK MIN.

20 NULL SYMBOLS DATA SYMBOLS 20 NULL SYMBOLS

Figure 31. Timing Sequence to Flush Tx Data Path

Figure 34. ∑-∆ Active Filter with Gain and Offset

capacitors provide ac signal coupling, which ensures that the

capacitor sources the dynamic currents required to charge the

Figure 35. Simple ADC Drive Configuration

AD9878 CLAMP LEVEL

Figure 37. Video Clamp Circuit Input

PCB DESIGN CONSIDERATIONS

OSCIN S P C24 Tx–

1 DIP06RCUP 0.1µF L13 L14 R36 C113

C111 RC0805 AVDDTx Tx– AGNDTx ADM1818-10ART

AD8138 1 CA_CLK CA_CLK RESET

3 R32 CA_DATA CA_DATA PROFILE 10kΩ

CA_EN CA_EN DGND3 21 22

Figure 38. Evaluation PCB Schematic

U9 6 10V AGND5 IF7 IF7

AD8328 BCASE CC0805 27 28

3.3V_ANA TB1 1 CLR 31 32

–5V_ANA TB1 3 10µF 37 38 22