Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Release v5.1
This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this
document may duplicate this document in whole or in part for internal business purposes only, provided that this entire
notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable
effort to prevent the unauthorized use and distribution of the proprietary information.
Note - Viewing PDF files within a web browser causes some links not to function (see MG595892).
Use HTML for full navigation.
This document is for information and instruction purposes. Mentor Graphics reserves the right to make
changes in specifications and other information contained in this publication without prior notice, and the
reader should, in all cases, consult Mentor Graphics to determine whether any changes have been
made.
The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in
written agreements between Mentor Graphics and its customers. No representation or other affirmation
of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor
Graphics whatsoever.
MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.
MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR
CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)
ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT,
EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at
private expense and are commercial computer software and commercial computer software
documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to
FAR 48 CFR 12.212 and DFARS 48 CFR 227.7202, use, duplication and disclosure by or for the U.S.
Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in
the license agreement provided with the software, except for provisions which are contrary to applicable
mandatory federal laws.
TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of
Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior
written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a third-
party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to
indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics’
trademarks may be viewed at: mentor.com/trademarks.
The registered trademark Linux® is used pursuant to a sublicense from LMI, the exclusive licensee of
Linus Torvalds, owner of the mark on a world-wide basis.
End-User License Agreement: You can print a copy of the End-User License Agreement from:
mentor.com/eula.
Chapter 1
Register Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register Assistant Abstract Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Using Register Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Overview on Register Data Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Blocks, Blocks Maps, and Registers/Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 2
Starting the Register Assistant Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 3
Register Assistant Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Importing Data From CSV Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CSV Import Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Importing Data From IP-XACT XML Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IP-XACT Import Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Importing Data from Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Import Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Setting Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Importing From CSV Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Importing From Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Auto-Instancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 4
Checking Imported Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Default Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Custom Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Checks Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Running Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Running Default Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Running Custom Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Chapter 5
Register Assistant Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
UVM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Generated UVM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Supporting Coverage Models for Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Chapter 6
Customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Custom Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Defining Properties for Register Assistant Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Custom Properties Definition Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Using Custom Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Handling Custom Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Appendix A
Command Line Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Running Register Assistant in Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Appendix B
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
JavaScript/Tcl Import File Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
UVM Output Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
OVM Output Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
RTL Pipelining Output Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
UVM Word Addressable Output Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Appendix C
Migrating to Register Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Mapping Command Line Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
End-User License Agreement
Register Assistant is a register management tool that allows you to make changes to register
specifications in a single place and automatically generate/update a number of derived outputs.
A typical modern device contains a rich mix of hardware, firmware and software.
Communication between these domains is provided by software-addressable registers whose
locations are specified along with memories in a block. Communication between the members
of the different design teams may not be quite so structured.
Specifying registers and managing changes is typically a manual, laborious and error prone
task. What is required is a single repository to describe registers and memories for each
component, sub-system and system from which the output for all downstream activities
(hardware design, software/firmware development, verification and documentation) can be
generated.
This is not a new problem, project teams have been finding creative ways to address this
challenge for many years and therefore use a variety of formats for describing register and
memory information. With this in mind, Register Assistant can import register and memory
specifications from a variety of sources including IP-XACT, XML and spreadsheet (CSV)
formats into a cohesive, extensible data model describing a hierarchy of blocks, sub-blocks,
maps, registers, fields and memories.
Customizable DRC checks ensures consistency of the data and a full API allows custom input
translators and output generators to be added. The current release of Register Assistant
generates OVM and UVM register package SystemVerilog code for verification, HTML hyper-
linked documentation for communication and record keeping, synthesizable VHDL and Verilog
RTL code, plus C Header files.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Register Assistant Abstract Flow
The main stages that comprise the Register Assistant flow are as follows:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Using Register Assistant
(default and/or custom), and the output type required (such as UVM, OVM, RTL or HTML).
Refer to “Control File” on page 23 for more information.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Overview on Register Data Hierarchy
A register block may contain instances of registers, memories, or sub-blocks. Each register
contains any number of fields, which mirror the values of the corresponding elements in
hardware.
A register block can have more than one block map, but there should be at least one map.
It is important to note that Register Assistant checks the structure of the imported register data
to make sure that at least one top register block is available, and if not found, a failure occurs.
Note
The structure relying on register files (instead of blocks) and memory maps (instead of
block maps) is also valid. However, if you are generating UVM or RTL, Register Assistant
internally translates register files to sub-blocks and memory maps to block maps.
Blocks
Blocks are optional. If you have a “flat” description for your registers/memories, you can
simply use the Auto-Instance feature (see “Auto-Instancing” on page 50). This feature
automatically creates a top-level block based on your register/memory descriptions provided
that the address information is supplied for each register/memory definition.
Alternatively you can explicitly instantiate one or more registers or memories in a named Block.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Blocks, Blocks Maps, and Registers/Memories
It is common to define registers/memories in one CSV file and to specify blocks and block maps
in separate CSV files. Figure 1-1 shows the relationship between block maps, blocks, and
register/memory descriptions.
Each block description requires three columns to be defined in your CSV input:
• Block Name — a name for the block. For each row of the block description, this name
repeats.
• Block Component Name — the name of the register, memory, or sub-block that is
instanced in this block. This name must match the register/memory/sub-block name that
you defined in your register/memory description columns. For example, if you define a
register called status_reg, the entry in the Block Component Name column is
status_reg.
• Block Instance Name — a unique identifier for the register/memory/sub-block in the
context of this block. Similar to instancing a component on a schematic, each register/
memory/sub-block instance within a block must have a name. For example, if you want
to add the status_reg to the block definition, you can name this register status_reg_h.
You can instance the same register/memory/sub-block multiple times using different
block instance names.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Blocks, Blocks Maps, and Registers/Memories
In this example, there are three registers and one memory grouped in a block named reg_block:
You can define as many blocks as you require. However, when you define more than one block,
Register Assistant requires you to specify which block is considered the top block. When you
run the tool interactively, you will see a list of blocks that the tool has determined from your
input files. Select the block that you want to designate as the top block from the dropdown list.
In the following example, there are two blocks available and sw_top_block is the top block:
Block Maps
To use a block description, you need to define a block map. The block map defines a starting
address for each register/memory within the block. Block maps require four columns:
• Block Name — the name of the block that you have defined. This name repeats for each
register/memory/sub-block instance within the block that is accessible via this block
map.
• BlockMap Name — a name for the block map that you are defining. This name repeats
for each register/memory/sub-block entry in the block map.
• BlockMap Instance Name — the instance name that you defined for the register/
memory/sub-block instance (using the Block Instance Name column).
• BlockMap Instance Address — the starting address for the register/memory/sub-block
instance.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Blocks, Blocks Maps, and Registers/Memories
In this example, we define the address space for the reg_block block:
Block Hierarchy
You can specify levels of block hierarchy, or sub-blocks, within your block specification. In this
example block description there is a top-level block called sw_top_block that contains two
instances of a block called sw_sub_block:
The example shows the use of the Block Instance Type of value block to indicate the two sub-
blocks whose instance names are sw1 and sw2. Those two instances reference a block called
sw_sub_block which is defined to contain six registers (that are defined in a separate CSV file),
starting on line 10.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Blocks, Blocks Maps, and Registers/Memories
In this example, we define the top-level block map in SW_MAP2 and the instance addresses for
each item in the block. Notice that in this case we explicitly reference the block map SW_MAP
for both instances of the sub-block using the path sw1.SW_MAP for the BlockMap Instance
Name. As each block can have any number of associated Block Maps, if you specify the
instance name alone (e.g. sw1) it will reference the default map for that sub-block. If you wish
to reference a specific map, you simply add the map name to the instance name (e.g.
sw1.SW_MAP).
The full CSV files for the preceding example can be found in <install_location>/examples/
uvm/CSV.
Relationship to Generation
Each generator utilizes the block and block map information that you provide:
• UVM — creates a UVM block class for each Block, with instances for each register/
memory instance. Declares the associated maps with the appropriate address
information from the Block Map.
• OVM — creates an OVM register map class for each Block with instances for each
register/memory instance.
• C Header — creates a struct for each block.
• RTL — generates a Verilog module or VHDL Entity/Architecture for each block.
• HTML — generates a hierarchical website based on the block hierarchy. The overall
address map is also generated.
Additional Block and Block Map CSV Columns
You can specify several optional CSV columns relating to blocks (please refer to CSV
Columns). Commonly used optional columns include:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Blocks, Blocks Maps, and Registers/Memories
Note
When you explicitly set the Block Instance Dimension as “1”, Register Assistant
generates this instance as an array of single element. Yet, when a value is not
specified for this column, Register Assistant generates one regular instance by
default (not an array).
o Block Instance Type — specifies the kind of instance in the block: register,
memory, or another block (sub-block). The default value is register.
o Block Replication Offset — if sub-block instances are not contiguous and you want
each instance of a sub-block to start on a specific boundary, you can specify a
Replication Offset. This allows you to specify the overall width of the block instance
(that is, the actual block size plus padding).
(This column also applies to the C Header generator.)
o Parameters — allows you to specify your own parameters to use in your own
generator or custom check. You can specify a block level parameter and value or an
instance-level parameter for each instance within a block.
• RTL — you can specify additional signals and information about those signals for the
RTL generator.
You can specify several optional CSV columns relating to block maps. Commonly used
optional columns include:
• BlockMap Description — allows you to add comments and documentation about the
block map.
• BlockMap is Default — indicates whether a particular block map is the default address
map for a block. If you only have a single block map, you do not need this column.
• BlockMap Address Offset — the address offset for the map (default is 0x0).
• BlockMap Instance Access — the software access mode for each register/memory
instance in the block map.
• Parameters — allows you to specify your own parameter to use in your own generator
or check.
Relationships Between Registers, Blocks, and Block Maps
This section summarizes the relationship between registers, blocks and block maps using a
simple example.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Blocks, Blocks Maps, and Registers/Memories
The address information is required if we use the auto-instance mechanism, but for this example
we will explicitly instance these registers in a block so we add an instance of each register in a
block called sub_block:
We have now described the contents of a block called sub_block but we have not defined how a
bus interface can access these register instances or which of these instances are visible to that
specific interface. This address map information is specified using a Block Map.
In this simple case, we define a single map called SUB_MAP with corresponding address values
for each instance in the block:
Since we have associated the map SUB_MAP with the block sub_block, the addresses specified
in the map will be used rather than those specified in the register definitions. The generated
documentation for the address map looks like this:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Blocks, Blocks Maps, and Registers/Memories
If we want to create hierarchy in our address map (perhaps to reuse the block multiple times) we
simply instance it in another block:
Here we have instanced block sub_block in a new parent block called top_block and specified
the instance type as block. We also need to make a corresponding map for the new block:
In the instance name we have explicitly stated that the instance of sub_block in the block
top_block is to use the SUB_MAP map and have specified the instance of the block starts at
address 100 hex. Therefore, when we generate from the perspective of the TOP_MAP we get the
following overall address map:
The offset addresses of the instances within SUB_MAP have been added to the address of the
parent map TOP_MAP to show the absolute addresses for the overall design.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant
Blocks, Blocks Maps, and Registers/Memories
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Chapter 2
Starting the Register Assistant Flow
The main elements of the Register Assistant flow—importing the register data, checking the
correctness of the data, and producing output—are communicated to Register Assistant through
a control file. The control file contains the commands related to each stage that Register
Assistant should implement.
Control File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control File
The Control File is a text file containing all the information needed by the Register Assistant to
process the input (imported registers) and produce the output (such as UVM, OVM, RTL, and
HTML files).
When using the Register Assistant in batch mode, you have to write this file manually. When
using the Register Assistant via an interface such as HDL Designer Series, then this file can be
auto-generated based on user-defined settings. In the second case, you would still be able to edit
the auto-generated control file if necessary and re-use it.
Format
The control file is a simple text file in which each line represents either a generator to run (with
comma-separated information) or a comment as follows:
# <comment>
<generator_language>, <generator_name>[, <parameter>]*
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Starting the Register Assistant Flow
Control File
The control file is usually divided into three main sections as shown in the following figure:
• Import Section — Contains the files names and locations from which the register data
shall be imported. Registers can be imported from several input sources such as CSV
files, IP-XACT XML format, or JavaScript and Tcl files. Your register data can be
distributed in files using more than one format.
Note
Note that you can write JavaScript and Tcl files using Register Assistant’s APIs to
import register data from any format you want, and also generate any type of output.
• Checks Section — Contains the command which instructs the Register Assistant to
validate the imported register data.
This section shows whether you want to run the default built-in checks of the Register
Assistant, and also whether you want to run your own custom checks (which you have
written in a JavaScript or Tcl file). Refer to “Checking Imported Registers” on page 55
for more information.
• Output Section — Shows the type of output required to be generated by the Register
Assistant, such as OVM, UVM, RTL or HTML.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Starting the Register Assistant Flow
Control File
Syntax
The control file consists of either generators or comments. Generators are written in the syntax
explained in Table 2-1.
Table 2-1. Control File Syntax
Keyword Description Value
<generator_language> Specifies the language of js
the generator that will be tcl
used.
java
<generator_name> Specifies the name of the ovm
generator in case of using uvm
java. In case of using
JavaScript or Tcl, rtl
specifies the location of c_header
the script file.
check
addDefaultChecks
addScriptChecks
file_location/file_name.js
file_location/file_name.tcl
<parameter> Specifies additional For example, you may have a CSV
parameters required by JavaScript file which requires parameters
the generator. This is for the CSV files that will be imported. The
optional. example below shows the CSV files added
as parameters for the JavaScript file:
js, examples/csv.js, sw_top_block,
examples/uvm/csv/sw_regs.csv,
examples/uvm/csv/sw_blocks.csv
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Starting the Register Assistant Flow
Control File
Note
* Any blank lines or white spaces in the control file are ignored.
* The control file accepts absolute paths, relative paths or environment variables. If a path is
relative, Register Assistant will resolve it relative to the control file’s location, then the project’s
location, then the current working directory.
* Register Assistant also understands two internal variables that can be used to refer to files
(either generators or arguments) in the control file: RA_HOME which indicates the path
<installation_folder>\registerassistant and RA_EXAMPLES which indicates the path
<installation_folder>\registerassistant\examples.
* You can add the following command when you want to auto-instance registers or memories in
a block: java, autoInstance, <block name>
Refer to “Auto-Instancing” on page 50.
* Generally, in the control file, when you specify optional parameters, you can use an empty
placeholder to signify that you want the default value used. For example:
java, ovm, myFile, , D:/projects/ovm
Usage
The syntax above can be applied in the control file as follows:
Import Section:
• The following command is used when you want to import register data from CSV files:
# Import registers using CSV Import
js, file_location/script_file_name.js, top block name,
file_location/register_data_file_name.csv, file_location/
block_data_file_name.csv
• The following command is used when you want to import register data from JavaScript
files:
# Import registers using programmatic creation by JS script
js, file_location/file_name.js
• The following command is used when you want to import register data from Tcl files:
# Import registers using TCL script
tcl, file_location/file_name.tcl
• The following command is used when you want to import register data from IP-XACT
XML:
# Import registers using IPXACTImport
js, file_location/file_name.js, top block name, file_location/
file_name.xml
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Starting the Register Assistant Flow
Control File
When importing from IP-XACT, you can use the script provided in Register Assistant’s
examples folder on the path <installation_folder>\registerassistant\examples\ipxact.js.
Note
When importing from CSV or IP-XACT XML, make sure you specify the name of
the top block if you are using a hierarchy of blocks.
Note that you do not need to specify the top block’s name when you are using only a
single block as it will be automatically detected. For example:
js, file_location/script_file_name.js, , file_location/register_data_file_name.csv,
file_location/block_data_file_name.csv
Checks Section:
• The following command must be used in order to run any checks in general (whether
default or custom):
# Run checks
java, check
When an error is found during the check, the flow stops. You can add the “dontStop”
option in order to continue the flow:
# Run checks
java, check, dontStop
The above command must be used in order for Register Assistant to run the “check”
generator. Subsequently, you will have to specify whether you want to run the default
and/or custom checks.
• The following command is used to add Register Assistant’s default checks:
# Add default checks
java, addDefaultChecks
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Starting the Register Assistant Flow
Control File
Output Section:
Register Assistant supports UVM register package version 1.0 and 1.1. If you do not
specify the version in the control file, Register Assistant uses 1.1 by default.
Note
You have the ability to define a specific path for the generated UVM output. If not
specified, the default Register Assistant project location will be used. The default
project location is the path specified by the -project command if you are using Register
Assistant in batch mode, or the project path of the host application if you are using
Register Assistant through an interface tool (such as HDL Designer Series). This applies
to all the following output generators as well.
If you do not specify the generated file’s name, the file is given the default name
<project’s name>_pkg.sv.
Also, Register Assistant supports OVM register package version 1.0, 2.0 and 2.2. You
can specify which version you want to use. If the version number is not specified,
Register Assistant uses 2.2 by default. If you want to use version 1.0 or 2.0, you will
have to manually set it in your control file.
Examples:
The following example specifies the file name, the version, in addition to the output
directory of the generated OVM.
java, ovm, myFile, 1.0, D:/Projects/Project_Temp_lib/ovm_files
The following example specifies the file name and the output directory of the generated
OVM, but does not specify the version number, and hence the default version 2.2 will be
used in generation.
java, ovm, myFile, , D:/Projects/Project_Temp_lib/ovm_files
The following example specifies the version but does not specify the file name, and
therefore the default file name <project’s name>_pkg.sv will be used.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Starting the Register Assistant Flow
Control File
The following example neither specifies the file name nor the version nor the output
directory, and therefore the default file name <project’s name>_pkg.sv, default version
2.2, and default project location will be used.
java, ovm
When generating HTML, you can use the script provided in Register Assistant’s
examples folder on the path <installation_folder>\registerassistant\examples\html.js.
• The following command is used to generate C Header files:
# Generate C Header
java, c_header, generated_file_name, C_Header_Output_Directory
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Starting the Register Assistant Flow
Control File
Examples
# Run checks
#java, check, dontStop
java, check
Import Section: The above control file imports register data from CSV files. The name of the
top block is “sw_top_block”.
Checks Section: This control file requires the validation of the register data by running the
default checks and also running custom checks referenced in the file examples/checks.js. If any
error is reported during validation, the flow will stop (since the “dontStop” option is commented
as shown above).
Output Section: The Register Assistant should produce two types of output: UVM register
package and HTML documentation. The generated UVM file’s name will be my_uvm_file.sv.
The generated output should be placed on the following paths D:/Projects/Project_Temp_lib/
uvm_files and D:/Projects/Project_Temp_lib/html_files.
Related Topics
Register Assistant Inputs
Register Assistant Output
Checking Imported Registers
Auto-Instancing
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Chapter 3
Register Assistant Inputs
Register Assistant receives certain inputs (register definitions), runs a number of checks to
verify that the input is correct, and then produces the required output (such as HTML, RTL or
OVM output).
This chapter details the register definition input types supported by Register Assistant.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Importing Data From CSV Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CSV Import Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Importing Data From IP-XACT XML Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IP-XACT Import Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Importing Data from Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Import Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Setting Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Importing From CSV Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Importing From Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Auto-Instancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Introduction
The register definitions can be delivered to Register Assistant in the following formats: CSV,
IP-XACT XML format, or JavaScript/Tcl.
• First of all, you have to identify which format to use.
• Depending on the format you choose, you must write an intermediary script file that
communicates with Register Assistant and delivers the register data. You have to make
sure that your register data is ready and available as described in your script.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Introduction
• You need to pass the script and the data files to the Register Assistant via a control file.
Tip
: Before generation, make sure that any instance of any object in the input files has a
definition. Otherwise, an error is raised during generation if the definition is missing.
Note
When defining register input, be informed that Register Assistant defaults the addressable
width to 8 bits. So for a 32 bit register width, the addresses increment by 4 Hex. e.g. 00, 04,
08, 0C etc.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Importing Data From CSV Files
# <comment>
<generator_language>, <generator_name>, <top block/main memory map name>,
<parameter>
For example:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
CSV Import Script File
Note
If you are using Register Assistant in batch mode, then you have to write the above
command manually in the control file. If you are using Register Assistant through an
interface tool such as HDL Designer Series, you will be able to enter your import, checks and
output settings through the interface and then the control file will be auto-generated. Refer to
“Control File” on page 23for further information.
After preparing your CSV files, you create a script to basically map the columns in your CSV
files to the columns of Register Assistant. That is to say, this script helps Register Assistant
recognize the columns in your CSV file. An example script is available with Register Assistant
on the path <installation_folder>\registerassistant\examples\csv.js. You can simply create a
copy of this script and modify the column mapping section to fit your standards (using Register
Assistant’s API commands which you can find on the path <installation_folder>\
registerassistant\api\index.html).
For example, you may need to change the default column name “Register Name” to “Register
Title”, in that case you can change the following line of code.
From:
To:
This means that “Register Title” is the new column name corresponding to the Register
Assistant object name “regName”.
Finally, you have to reference the script along with your CSV files in the control file.
See “CSV Import Script File” on page 34for more details on the script and its content.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
CSV Import Script File
Format
The file is basically composed of several sections as shown in the following figure:
• Imports — Contains the imports required for the script. The below imports can be used:
o The following import is used to support any calls made to Register Assistant’s data
model. This import is mandatory.
importPackage(com.mentor.regassist.dm);
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
CSV Import Script File
o The following import is required to be able to run the CSV import utility in Register
Assistant. This import is mandatory.
importClass(com.mentor.regassist.generator.CSVImport);
o The following import is used to be able to print log messages, whether status or error
messages. This import is optional.
importClass(com.mentor.svassist.common.util.EcLog);
Note that any messages will appear in the console of Register Assistant. If you are
using Register Assistant through an interface tool such as HDL Designer Series, then
the messages will appear in a log tab for that tool.
o The following import is used to support the definition of column formats, that is the
column name mapping, of the imported CSV files. This import is optional.
importClass(java.util.HashMap);
If you are using the default column names (see the example script on
<installation_folder>\registerassistant\examples\csv.js), then you do not have to
define any column mappings in this file.
• Generate Method — The Generate method is obligatory in the script. It encases the
entire code in the script as follows:
function generate(project, object, params) {
<code>
...
return 0;
}
This method enables you to detect any errors and stop the flow at an early stage. This
can be done within the script by returning a negative integer at any time to indicate that
an error has occurred, and consequently the flow will stop. See the following example:
if (params == null || params.size() < 2) {
EcLog.error("CsvImporter : Missing required parameter 'csvFile'" +
params);
return -1;
}
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
CSV Import Script File
If the Generate method is missing in the script, an error is raised as in the following
example:
# Error: Error executing javascript generator 'D:\RA\examples\
csv.js', missing generate method.
You can also refer to the CSV Columns table which contains a list of Register Assistant’s
default column names. It shows a description for each column, whether it is mandatory
or optional, and so on.
Note that when Register Assistant parses the csv.js file you supply, a message is raised
in the following cases: when a mandatory column is not found, or when any column is
not matched to the objects in Register Assistant’s data model.
You can also refer to the APIs’ documentation on the path <installation_folder>\
registerassistant\api\index.html.
Notes:
o Column names are case insensitive and also white space insensitive. For example,
“register name”, “RegisterName”, “REGISTER NAME” will all match the column
“Register Name”.
o When using the Block Instance Backdoor column in the CSV input files, if you want
to set a backdoor path for an array with a different path for each instance in the array,
you can use the %(DIM) variable.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
CSV Import Script File
If used, the following code is generated (in this example the backdoor path is set as
“data_small_mem_h_array_%(DIM)_local”):
foreach ( small_mem_h[i] ) begin
small_mem_h[i] =
small_mem::type_id::create($psprintf("small_mem_h[%0d]", i));
small_mem_h[i].configure(this, null,
($psprintf("data_small_mem_h_array_%0d_local", i)));
small_mem_h[i].build();
end
If not used, the following code is generated (in this example the backdoor path is set
as “data_small_mem_h_array_local”):
foreach ( small_mem_h[i] ) begin
small_mem_h[i] =
small_mem::type_id::create($psprintf("small_mem_h[%0d]", i));
small_mem_h[i].configure(this, null,
“data_small_mem_h_array_local");
small_mem_h[i].build();
end
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
CSV Import Script File
// READ-WRITE
case "READ-WRITE":
case "RW":
return RAAccessType.READ_WRITE;
// READ-WRITE-Queued
case "READ-WRITE-QUEUED":
case "RWQ":
return RAAccessType.READ_WRITE_QUEUED;
...
...
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
CSV Import Script File
o If you do not explicitly define fields within the register in the input files, Register
Assistant creates a single field by default in the generated output covering the entire
register. This default field takes the same software and hardware access modes of the
register.
• Verifying Parameters — In this section, a check is performed to ensure that the
parameters exist (that is, the CSV files containing the register data which are specified in
the control file).
• Initializing Variables — In this section, a variable is initialized with the top block/main
memory map. (This is needed when identifying the top block/main memory map later.)
• Actual Import from CSV Files — This section contains the call to the CSV Import
API; this is where you run the actual import of data from the CSV files. For example:
var result = CSVImport.importAllRegistersFromCSV(project,
colMapping, params, match, true);
• Identifying the Top Block/Main Memory Map— This section specifies the top block/
main memory map. This is required in order for the output to generate correctly.
Tip
: If there is a row in a CSV file that does not have a Register Name or that is
completely empty, then the whole row will be ignored by Register Assistant. If only
the Register Name is available in the row, then it will be added to the project.
Example
To view an example CSV import script file, refer to the example available with Register
Assistant on <installation_folder>\registerassistant\examples\csv.js.
You can also refer to the documentation of Register Assistant’s APIs on the path:
<installation_folder>\registerassistant\api\index.html.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Importing Data From IP-XACT XML Files
# <comment>
<generator_language>, <generator_name>, <top block/main memory map name>,
<parameter>
For example:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
IP-XACT Import Script File
Note
Note that if you are using Register Assistant in batch mode, then you have to write the above
command manually in the control file. If you are using Register Assistant through an
interface tool such as HDL Designer Series, you will be able to enter your import, checks and
output settings through the interface and then the control file will be auto-generated. Refer to
“Control File” on page 23for further information.
Format
The script is basically composed of several sections as shown in the following figure:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
IP-XACT Import Script File
• Imports — Contains the imports required for the script. The below imports can be used:
o The following import is used to support any calls made to Register Assistant’s data
model. This import is mandatory.
importPackage(com.mentor.regassist.dm);
o The following import is required to be able to run the IP-XACT import utility in
Register Assistant. This import is mandatory.
importClass(com.mentor.regassist.generator.IPXACTImport);
o The following import is used to be able to print log messages, whether status or error
messages. This import is optional.
importClass(com.mentor.svassist.common.util.EcLog);
Note that any messages will appear in the console of Register Assistant. If you are
using Register Assistant through an interface tool such as HDL Designer Series, then
the messages will appear in a log tab for that tool.
• Generate Method — The Generate method is obligatory in the script. It encases the
entire code in the script as follows:
function generate(project, object, params) {
<code>
...
return 0;
}
This method enables you to detect any errors and stop the flow at an early stage. This
can be done within the script by returning a negative integer at any time to indicate that
an error has occurred, and consequently the flow will stop. See the following example:
if (params == null || params.size() < 2) {
EcLog.error("IPXACTImporter : Missing required parameters 'js,
ipxact.js, memMapName, xmlFile'" + params);
return -1;
}
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
IP-XACT Import Script File
If the Generate method is missing in the script, an error is raised as in the following
example:
# Error: Error executing javascript generator 'D:\RA\examples\
ipxact.js', missing generate method.
Example
To view an example IP-XACT import script file, refer to the example available with Register
Assistant on <installation_folder>\registerassistant\examples\ipxact.js.
You can also refer to the documentation of Register Assistant’s APIs on the path:
<installation_folder>\registerassistant\api\index.html.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Importing Data from Scripts
Subsequently, you have to write the following command in the control file to pass the script file
to Register Assistant:
# <comment>
<generator_language>, <generator_name>
For example:
Or:
Note
Note that if you are using Register Assistant in batch mode, then you have to write the above
command manually in the control file. If you are using Register Assistant through an
interface tool such as HDL Designer Series, you will be able to enter your import, checks and
output settings through the interface and then the control file will be auto-generated. Refer to
“Control File” on page 23for further information.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Import Script File
You can find information on Register Assistant’s APIs on the path <installation_folder>\
registerassistant\api\index.html.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Import Script File
Format
The below file is basically composed of several sections as shown in the following figure:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Import Script File
• Imports — Contains the imports required for the script. The below import can be used:
o The following import is used to support any calls made to Register Assistant’s data
model. This import is mandatory.
importPackage(com.mentor.regassist.dm);
• Generate Method — The Generate method is obligatory in the script. It encases the
entire code in the script as follows:
function generate(project, object, params) {
<code>
...
return 0;
}
This method enables you to detect any errors and stop the flow at an early stage. This
can be done within the script by returning a negative integer at any time to indicate that
an error has occurred, and consequently the flow will stop.
If the Generate method is missing in the script, an error is raised as in the following
example:
# Error: Error executing javascript generator 'D:\RA\examples\
sw.js', missing generate method.
In case of Tcl scripts, you can just include a return statement returning a negative
number, for example:
if {$result == false} {
return -1
• Creation of Register Objects — In this section, you create objects within your project
for registers, memories, blocks.
You can also create objects for fields within their corresponding registers.
• Instantiation of Register Objects — In this section, you create instances from your
objects according to the hierarchy of register data. For example, you may need to
instantiate registers in sub-blocks or instantiate sub-blocks in the top block. (Refer to
“Overview on Register Data Hierarchy” on page 14).
Refer to “JavaScript/Tcl Import File Example” on page 221 to view sample JavaScript and Tcl
files. You can also refer to the documentation of Register Assistant’s APIs on the path:
<installation_folder>\registerassistant\api\index.html.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Setting Constraints
Setting Constraints
You can set constraints on your imported register definitions. For example, you may need to
ensure that value X related to object Y is not greater than 10. These constraints are
SystemVerilog constraints.
Any added constraints will be inserted in the generated output, such as OVM, UVM or HTML.
Later when running simulation, the simulator will take the constraints in the generated OVM/
UVM file into consideration to make sure they are fulfilled.
3. If you are using a column name different from the default, make sure you map the
column name in your csv.js import file as follows:
For registers:
colMapping.put("Your Column Name",
CSVImport.COLUMNS.regConstraints); //Constraints for the register.
For fields:
colMapping.put("Your Column Name", CSVImport.COLUMNS.fConstraints);
//Constraints for the field.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Importing From Scripts
For memories:
colMapping.put("Your Column Name",
CSVImport.COLUMNS.memConstraints); //Constraints for the memory.
importPackage(com.mentor.regassist.dm);
project.getBlocks("block").setConstraints("constraint c_block1
{dummy1} \n constraint c_block2 {dummy2}");
return 0;
}
For information on the supported APIs, refer to the APIs’ documentation on the path
<installation_folder>\registerassistant\api\index.html.
Auto-Instancing
Auto-Instancing automatically instances registers/memories in a new or existing top-level block
and creates a corresponding block map. This provides a rapid way to create the required block
structure from a “flat” list of registers and memories. Auto-instancing requires register
addresses to be specified with the register/memory definitions.
The auto-instancing feature can be used with any import method, such as CSV, JavaScript or
IP-XACT, and can be used when generating UVM, OVM, RTL and/or HTML output.
Note
This feature is automatically enabled for IP-XACT.
To automatically create instances, you have to add the following command in the control file:
It is important to make sure that you add this command within the control file after the import
commands and before the generation commands.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Auto-Instancing
The last argument following the <block name> enables you to use register definition names for
instances. It takes a value of 1or 0. If set to 1, which is the default value, register declaration
names are used for instances and declarations are renamed to “<reg_decl_name>_reg” in the
generated code. If set to 0, register instances are generated using the following convention
ins_<reg_name>.
In the auto-instancing command, in case you provide the name of a block that does not exist in
the imported definitions, Register Assistant will automatically create a block with the same
name in the generated output and make it the top block, and then create instances of the register
definitions within that block.
Example
The following example shows a control file which adds instances for imported registers in a
block titled “my_top_Block”.
# Run checks
java, check
Below is an excerpt of UVM output generated for CSV input that only contained the definitions
of registers. As shown below, a new top block titled “my_top_Block” is automatically created
(this block was not defined in the input files) and it contains instances of the imported registers.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Auto-Instancing
/* BLOCKS */
//--------------------------------------------------------------------
// Class: my_top_Block
//--------------------------------------------------------------------
uvm_reg_map my_top_Block_map;
// Function: new
//
function new(string name = "my_top_Block");
super.new(name, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
inst_stopwatch_value =
stopwatch_value::type_id::create("inst_stopwatch_value");
inst_stopwatch_value.configure(this);
inst_stopwatch_value.build();
inst_stopwatch_reset_value =
stopwatch_reset_value::type_id::create("inst_stopwatch_reset_value");
inst_stopwatch_reset_value.configure(this);
inst_stopwatch_reset_value.build();
inst_stopwatch_upper_limit =
stopwatch_upper_limit::type_id::create("inst_stopwatch_upper_limit");
inst_stopwatch_upper_limit.configure(this);
inst_stopwatch_upper_limit.build();
inst_stopwatch_lower_limit =
stopwatch_lower_limit::type_id::create("inst_stopwatch_lower_limit");
inst_stopwatch_lower_limit.configure(this);
inst_stopwatch_lower_limit.build();
inst_stopwatch_memory =
stopwatch_memory::type_id::create("inst_stopwatch_memory");
inst_stopwatch_memory.configure(this);
inst_stopwatch_memory.build();
inst_stopwatch_csr =
stopwatch_csr::type_id::create("inst_stopwatch_csr");
inst_stopwatch_csr.configure(this);
inst_stopwatch_csr.build();
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Auto-Instancing
inst_stopwatch_counter =
stopwatch_counter::type_id::create("inst_stopwatch_counter");
inst_stopwatch_counter.configure(this);
inst_stopwatch_counter.build();
lock_model();
endfunction
endclass
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Inputs
Auto-Instancing
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Chapter 4
Checking Imported Registers
After importing the register definition files, the Register Assistant performs a number of
coherency checks on registers to identify any incorrect data. This chapter explains how Register
Assistant can apply coherency checks to imported register definitions.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Default Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Custom Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Checks Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Running Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Running Default Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Running Custom Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Introduction
After importing the register definition files, the Register Assistant performs a number of
coherency checks on registers to identify any incorrect data. These checks are used to validate
different aspects, such as ensuring that mandatory information on each register is provided,
ensuring that each interrupt has a corresponding mask, and so on.
Register Assistant provides a set of default checks, yet you have the ability to apply your own
custom checks if necessary.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Default Checks
Register Assistant identifies whether coherency checks (default or custom) should be applied or
not through the control file. So, you have to provide the necessary instructions in the control file
in order for Register Assistant to run the checks on the imported registers.
Default Checks
The Register Assistant includes a number of built-in checks by default. The following are
examples of checks that Register Assistant supplies.
• Important Attributes — Checks that mandatory data is provided correctly for the
registers such as the Register Name, Register Address Offset and Field Name. This also
applies to the Memory Name, Address Offset and Range.
• Address Overlap — Checks that no registers in the top level map overlap in addresses.
This also applies to memories.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Default Checks
Note that if you choose to generate C Header files, this check ensures that the block
replication offset is not smaller than the actual size of the block.
• Reset Values — Checks that all registers have valid reset values defined, whether on the
registers or fields, and that the reset values completely fill the registers. This also applies
to memories. If a violation for this check occurs, the flow will stop; but in case the
register is write-only, a warning will be raised instead (since a write-only register is not
required to have a reset value).
Note
You do not have to specify register reset values if all the fields have reset values and
vice-versa.
• Top Block Availability — Checks that at least one top register block is available, and if
not found, a failure occurs.
• Unique Names — All definition names should be unique: registers, memories, sub-
blocks, and blocks. Within a block or a sub-block, all instance names should be unique.
Within a Register, all field names should be unique. Within a register block, all map
names should be unique.
• Object Names — Checks that instances have valid definitions and that object names are
valid strings and valid identifiers.
• Field Value Width — Verifies that field values can fit within their defining fields.
• Register Field Access Mismatch — Checks that the register access and its field access
are compatible. This check fails in the following conditions:
o Register RO, field RW or WO
o Register WO, field RW or RO
Note
The checks operate on instances, so if there is a violation in the definition and it
is instantiated more than once, the same error can be reported many times. If a
definition is not instantiated, no violations will be reported.
The generator runs the checks, but if a violation occurs, the flow stops by default. You can
choose to continue the flow even if a check reports errors by setting the “dontStop” option. See
“Running Checks” on page 62.
Related Topics
Running Default Checks
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Custom Checks
Custom Checks
You can define your own custom checks using the JavaScript or Tcl language. Later, you can
refer to your script file in the control file, so that the Register Assistant would run your custom
checks.
Checks Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Checks Script File
Format
The file is composed of three sections as shown in the following figure:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Checks Script File
• Imports — Contains the imports required for the script. The below imports can be used:
o The following import is used to support any calls made to Register Assistant to
obtain certain register information (that is, the information that will be used by the
check function). This import is usually required.
importPackage(com.mentor.regassist.dm);
o The following import is required to be able to add the check function to the list of
checks that Register Assistant should run. This import is mandatory.
importClass(com.mentor.regassist.generator.RACheckerManager);
o The following import is used to be able to print log messages related to the applied
checks, whether status or error messages. This import is optional.
importClass(com.mentor.svassist.common.util.EcLog);
Note that such messages will appear in the console of Register Assistant. If you are
using Register Assistant through an interface tool such as HDL Designer Series, then
the messages will appear in a log tab for that tool.
• Check Function — Contains all the custom checks that should be applied to the
imported registers. This is the core of the file.
In this section, the function name must be “check” and it takes the “project” instance as
an argument. The “project” instance refers to the current project you are working on.
function check(project) {
...
...
}
If this function returns a negative number, this signifies that the check failed, otherwise
it means that the check passed.
Note
If a failure occurs, the check will stop. To prevent this, you have to set the
“dontStop” option in the control file. Refer to “Running Checks” on page 62.
• Adding the Check Function — In this section, you should add the check function to
the “RACheckerManager” class, so that it would be added to the set of checks that
Register Assistant applies to the imported registers.
function generate(project, object, params) {
RACheckerManager.addCheck(check);
return 0;
}
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Checks Script File
Note how the check function is written inside a “generate” function. The generate
function enables you to detect any errors and stop the flow at any point. This can be
done within the script by returning a negative integer at any time to indicate that an error
has occurred, and consequently the flow will stop.
Note
In case of Tcl scripts, you can just include a return statement returning a negative
number, for example:
if {$result == false} {
return -1
Refer to “Examples” on page 64 to view samples of checks JavaScript files and also Tcl files.
You can also refer to the documentation of Register Assistant’s APIs on the path:
<installation_folder>\registerassistant\api\index.html.
Related Topics
Running Custom Checks
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Running Checks
Running Checks
To run checks as part of the register import-generate flow, the check operation must be forced
through the control file. This takes place by adding the “check” generator in the control file as
follows.
# Run checks
java, check
The generator runs the checks, but if a violation occurs, the generator stops by default. You can
choose to continue the flow even if a check reports errors by setting the “dontStop” option as
follows:
# Run checks
java, check, dontStop
Subsequently, you have to specify in the control file whether you will run default checks and/or
custom checks. Refer to “Running Default Checks” on page 62 and “Running Custom Checks”
on page 63.
Batch Mode
If you are using the Register Assistant in batch mode, then you have to manually force the
default checks in the control file. You have to add the following lines in the control file:
# Run checks
java, check
GUI Mode
If you are using any interface to the Register Assistant (such as HDL Designer Series), then you
have to set the run built-in checks option in the import register settings. By that, the auto-
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Running Custom Checks
generated control file will automatically contain the necessary instructions to run the default
checks.
# Run checks
java, check
Tip
: This example file applies the “full field definition” check which checks that the fields
within a register fully cover the register width. That is to say, this check ensures that if a
register has fields, then the fields cover all the register bits, and that all the bits are assigned to
fields.
# tcl checks
java, addScriptChecks, examples/checkMap.tcl
# Run checks
java, check
Tip
: When you run Register Assistant through an interface tool such as HDL Designer Series,
setting the run built-in checks option in the import register settings will run the default
checks mentioned in the section “Default Checks” on page 56 in addition to the example
checks.js and CheckMap.tcl files mentioned above. If you are writing the control file manually,
then you can manually reference these files if needed.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Examples
# tcl checks
java, addScriptChecks, examples/checkMap.tcl
# Run checks
java, check, dontStop
As shown in the above underlined lines, this control file runs checks as part of the flow. It runs
the default built-in checks of the Register Assistant and it also runs custom checks defined in the
JavaScript file examples/checks.js and the Tcl checks defined in the file examples/checkMap.tcl.
Also, the control file stipulates that any errors found will not stop the flow.
Examples
The following examples show various usages of the checks file. Example JavaScript and Tcl
files are available on <installation_folder>\registerassistant\examples\checks.js and
<installation_folder>\registerassistant\examples\checkMap.tcl.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Examples
importPackage(com.mentor.regassist.dm);
importClass(com.mentor.regassist.generator.RACheckerManager);
importClass(com.mentor.svassist.common.util.EcLog);
/* Check that registers with fields are fully defined with fields */
function check(project) {
return result;
}
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Examples
Example Notes:
importPackage(com.mentor.regassist.dm);
importClass(com.mentor.regassist.generator.RACheckerManager);
importClass(com.mentor.svassist.common.util.EcLog);
function check(project) {
EcLog.log("Checking the Reset Mask value is not Null...");
return 1;
}
RACheckerManager.addCheck(check);
return 0;
}
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Examples
if { $defName == "" } {
# Invalid instance, couldn't locate definition
set msg "Couldn't locate definition '$defName' for the memory map
instance '$instName'. Invalid Memory map instance.\n"
set msg "$msg Please make sure that the definition name is set
correctly on the memory map instance."
::raLogMessage $msg
return -1;
return 1;
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Checking Imported Registers
Examples
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Chapter 5
Register Assistant Output
Register Assistant contains a number of generators that use the imported register data to create
different output types. According to the output type you choose, Register Assistant uses the
corresponding generator. Among the generators available in Register Assistant, for example,
are the UVM, OVM, RTL, and HTML generators.
This chapter details the different output types generated by Register Assistant.
UVM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Generated UVM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Supporting Coverage Models for Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Supporting Coverage Models for Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Supporting Simple “Quirky” Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
How to Use Quirky Register With CSV Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Supporting Back Door Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
OVM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Generated OVM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
HTML Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
HTML Output Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
RTL Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Specifying RTL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Specifying Software and Hardware Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Specifying the Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Generic Bus and Bus Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Preparing the Control File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Understanding RTL Intrinsic Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Examining the Generated RTL File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Customizing Generated Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Entering Data to Register Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
What to Specify in the Control File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
RTL Alternative Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
RTL Software Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
RTL Byte Enable Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Understanding RTL Field Signal Naming and Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
RTL Write/Read Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
C Header Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Specifying the Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Preparing the Control File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Understanding C Header Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
UVM Output
UVM Output
The UVM verification environment is composed of several components, among which is the
UVM register package. This package can be automatically generated using Register Assistant.
The generated UVM file should contain the description of the imported registers.
To generate the UVM register package, you have to write the following command in the control
file:
# <comment>
<generator_language>, <generator_name>, <file_name>, <UVM Register Package
Version>, <UVM Output Directory/Location>
For example:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generated UVM File
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generated UVM File
Format
The UVM file is basically composed of several sections as shown in the following figure:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generated UVM File
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Coverage Models for Blocks
• Defining the Register Package — Contains the definition of the register package and
the required imports.
• Defining Register Objects — Contains the definitions of registers.
Registers are defined by extending the class uvm_reg or the alternative base class
specified using the Register Custom Type CSV column.
class stopwatch_csr extends uvm_reg;
Subsequently, fields are defined within the register, constructors are created determining
the name and size of the register and whether it has coverage or not, a build method is
implemented to actually create the instances in the class, and then each field is
configured using a configure method.
This is repeated for each register.
• Defining Register Blocks and Register Hierarchy — Contains the definitions of
register blocks. It also contains the register hierarchy and the block maps.
This section defines register files or sub-blocks by extending from the uvm_reg_block
class. In this section, an instance is created for each register or memory in the register
file/block.
Note
Mentor Graphics recommends defining blocks and sub-blocks instead of register
files. If your input files contain register files, then they will be automatically
translated as blocks in the UVM output. See “Overview on Register Data Hierarchy” on
page 14.
Example
Refer to “UVM Output Example” on page 229 to view an example UVM register package
generated by Register Assistant.
To generate coverage models, you have to set the coverage type in your input files. This is
achieved by doing the following:
• CSV — If you are using CSV files to provide your register definitions, then make sure
you have a column in your blocks file titled “Block Coverage”.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Coverage Models for Blocks
Use this column to specify the coverage type identifier. The only supported identifier is
“UVM_CVR_ADDR_MAP”. This identifier checks the addresses read or written in a
block map. If you use any other value, then this is interpreted as no coverage required,
that is, it will be interpreted as “UVM_NO_COVERAGE”.
• JavaScript files — If you are using JavaScript files to provide your register definitions,
then make sure you set the coverage option using the following API:
<block_name>.setCoverage(RABlock.COVERAGE.<uvm_coverage_identifier>
);
Like CSV, you need to specify the coverage type identifier. The only supported
identifier is “UVM_CVR_ADDR_MAP”. This identifier checks the addresses read or
written in an address map.
See the following example excerpt:
// Create Top Block
var sw_top_block = project.addBlock("sw_top_block");
sw_top_block.setDescription("Top block for the stopwatch design");
sw_top_block.setCoverage(RABlock.COVERAGE.UVM_CVR_ADDR_MAP);
project.setTopBlock(sw_top_block);
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Coverage Models for Blocks
By setting the coverage option in your input files, the generated UVM register package will
include a new defined class called <block name_coverage>. This class will be instantiated
within the class of the block itself, and the instance will be called within the sample and build
methods. See the following generated UVM register package example.
Example
The following generated code excerpt shows an example of a block and its corresponding
coverage class.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Coverage Models for Blocks
//--------------------------------------------------------------------
// Class: stopwatch_block_SW_MAP_coverage
//
// Coverage for the 'SW_MAP' in 'stopwatch_block'
//--------------------------------------------------------------------
option.per_instance = 1;
option.name = name;
endgroup: ra_cov
endclass: stopwatch_block_SW_MAP_coverage
//--------------------------------------------------------------------
// Class: stopwatch_block
//
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Coverage Models for Blocks
// Function: new
//
function new(string name = "stopwatch_block");
super.new(name, build_coverage(UVM_CVR_ADDR_MAP));
endfunction
// Function: build
//
virtual function void build();
if(has_coverage(UVM_CVR_ADDR_MAP)) begin
SW_MAP_cg =
stopwatch_block_SW_MAP_coverage::type_id::create("SW_MAP_cg");
set_coverage(UVM_CVR_ADDR_MAP);
end
stopwatch_value_reg =
stopwatch_value::type_id::create("stopwatch_value_reg");
stopwatch_value_reg.build();
stopwatch_value_reg.configure(this);
stopwatch_reset_value_reg =
stopwatch_reset_value::type_id::create("stopwatch_reset_value_reg");
stopwatch_reset_value_reg.build();
stopwatch_reset_value_reg.configure(this);
stopwatch_upper_limit_reg =
stopwatch_upper_limit::type_id::create("stopwatch_upper_limit_reg");
stopwatch_upper_limit_reg.build();
stopwatch_upper_limit_reg.configure(this);
stopwatch_lower_limit_reg =
stopwatch_lower_limit::type_id::create("stopwatch_lower_limit_reg");
stopwatch_lower_limit_reg.build();
stopwatch_lower_limit_reg.configure(this);
stopwatch_csr_reg =
stopwatch_csr::type_id::create("stopwatch_csr_reg");
stopwatch_csr_reg.build();
stopwatch_csr_reg.configure(this);
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Coverage Models for Fields
lock_model();
endfunction
// Function: sample
//
function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map
map);
if(get_coverage(UVM_CVR_ADDR_MAP)) begin
if(map.get_name() == "SW_MAP") begin
SW_MAP_cg.sample(offset, is_read);
end
end
endfunction: sample
endclass
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Coverage Models for Fields
Note
If you set the “Field is Covered” column value to TRUE for a reserved field,
Register Assistant will issue a warning message during generation.
The default value for the “Field is Covered” column is FALSE. This indicates that the
default Register Assistant behavior is not to generate coverage information for register
fields.
Example
In this example, register stopwatch_csr fields stride, updown, upper_limit_reached and
lower_limit reached are to be covered. We therefore, set the “Field is Covered” flag value to
TRUE for each of these fields in the CSV input file.
Let us examine the generated code for the Control Status Register and note the field coverage
code added.
// Class: stopwatch_csr
//
// Control Status Register
//--------------------------------------------------------------------
uvm_reg_field padding
rand uvm_reg_field stride;
rand uvm_reg_field updown;
uvm_reg_field upper_limit_reached;
uvm_reg_field lower_limit_reached;
By setting the field coverage option in your input files, the generated UVM register package
will create a single covergroup called “cg_vals”. For each non-reserved field whose “Field is
Covered” flag is TRUE, a coverpoint with the name of the field is created.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Coverage Models for Fields
// Function: coverage
//
covergroup cg_vals;
stride : coverpoint stride.value[3:0];
updown : coverpoint updown.value[0];
upper_limit_reached : coverpoint upper_limit_reached.value[0];
lower_limit_reached : coverpoint lower_limit_reached.value[0];
endgroup
In the function new the coverage is set to UVM_CVR_FIELD_VALS and the covergroup is
constructed.
// Function: new
//
function new(string name = "stopwatch_csr");
super.new(name, 32, build_coverage(UVM_CVR_FIELD_VALS));
add_coverage(build_coverage(UVM_CVR_FIELD_VALS)
if(has_coverage(UVM_CVR_FIELD_VALS)) begin
cg_vals = new();
endfunction
// Function: sample_values
//
virtual function void sample_values();
super.sample_values();
if (get_coverage(UVM_CVR_FIELD_VALS))
cg_vals.sample();
endfunction
// Function: build
//
virtual function void build();
padding = uvm_reg_field::type_id::create("padding");
stride = uvm_reg_field::type_id::create("stride");
updown = uvm_reg_field::type_id::create("updown");
upper_limit_reached =
uvm_reg_field::type_id::create("upper_limit_reached");
lower_limit_reached =
uvm_reg_field::type_id::create("lower_limit_reached");
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Simple “Quirky” Registers
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
How to Use Quirky Register With CSV Input
import mypkg::*;
import pkg2::*;
At the same time, the column titled “Register Custom Type” is added in the CSV input file and
given the value my_custom_reg, specifically on the row of the register titled stopwatch_counter.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
How to Use Quirky Register With CSV Input
Hence, Register Assistant extends from the class my_custom_reg for the register
stopwatch_counter only (instead of extending from uvm_reg) as follows:
//----------------------------------------------------------------
// Class: stopwatch_counter
//
// Stop Watch Counter
//-------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_counter");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
Through Parameters
As mentioned before, first make sure that you have written the definition of your quirky register
class in a package, and then add the following parameter columns in your CSV file:
Procedure
1. Add a parameter on the project level for the import statement. This includes adding the
following columns:
• Project Parameter Name: The value of this parameter should be
uvmgen.EXTRA_IMPORTS.
• Project Parameter Value: Specify the name of your user-defined package. Note that
you can specify more than one package name separated by spaces.
• Project Parameter Description: Specify any description for reference.
See the following example:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
How to Use Quirky Register With CSV Input
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
How to Use Quirky Register With CSV Input
The example above signifies that in the generated output, Register Assistant will extend
from the class my_custom_reg for the register stopwatch_counter (instead of extending
from uvm_reg) as follows:
//----------------------------------------------------------------
// Class: stopwatch_counter
//
// Stop Watch Counter
//-------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_counter");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
3. Make sure the columns above are mapped correctly in your csv.js file. Refer to
“Importing Data From CSV Files” on page 33. You can also refer to CSV Columns.
4. For more information on parameters, refer to “Parameters” on page 213.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
How to Use Quirky Register With CSV Input
The example above signifies that you will add extra imports to the generated UVM
register package as follows:
// Extra imports
import mypkg::*;
import pkg2::*;
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Back Door Access
The example above signifies that in the generated output, Register Assistant will extend
from the class my_custom_reg for the register stopwatch_counter (instead of extending
from uvm_reg) as follows:
//----------------------------------------------------------------
// Class: stopwatch_counter
//
// Stop Watch Counter
//-------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_counter");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
For maximum reuse, it is recommended to specify just the path segment for each level in the
design hierarchy although you can specify multiple levels of the path to a given object if
required.
Register Assistant allows you to specify backdoor paths for blocks, instances within blocks
(registers, memories or other blocks), and fields within registers.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Back Door Access
You can specify backdoor paths through your CSV input files by doing the following:
• If you have multiple fields within your registers, you can add the “Field Backdoor”
column in the CSV file describing your registers. You can use this column to specify the
backdoor path for each field.
• In the CSV file describing your blocks, add the “Block Backdoor” and “Block Instance
Backdoor” columns. These columns allow you to specify the simulation backdoor path
for the block and for a given instance (register, memory or sub-block) within a block
respectively.
Refer to Example, below for further details.
Example
Consider the following example CSV input files and the resulting UVM generated output.
Input:
In this file, note the added column titled “Field Backdoor”. It contains the backdoor path on the
level of each field.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Back Door Access
In this file, note the “Block Backdoor” and “Block Instance Backdoor” columns. The “Block
Backdoor” column indicates the simulator path for a specific block. The “Block Instance
Backdoor” column indicates the path or path segment for a given instance (register, memory or
sub-block) within a block.
• You can leave a cell empty which indicates that no backdoor path is required.
• You can directly specify a backdoor path.
• You can use the %(FIELDS) variable which indicates that a backdoor path is required
and that the tool can use the field paths specified for the field in the “Field Backdoor”
column (see Figure 5-2 and Figure 5-3).
• If the block instance has an array, you can use the variable %(DIM) to refer to each
instance of the expanded array. For example, you can enter the following value in the
cell: %(FIELDS)_array_%(DIM)_local
The overall backdoor path to a given instance (sub-block, register or memory) is
determined during simulation by concatenating the paths for each level. In the above
example, the path to the last register in the instance array would be:
top.dut.field1_small_mem_h_array_7_local
Note
For arrays of instances, the %(DIM) variable can be combined with the %(FIELDS)
in order to create the appropriate backdoor path expression.
Refer to the OVM/UVM Variables table for information on the %(DIM) and %(FIELDS)
variables.
Output:
The UVM output generated by Register Assistant will be affected by your backdoor access
definitions as follows:
• For the “Field Backdoor”, the generated UVM output requires a “slice” to be specified
for each register field along with its bit offset and width, which are provided through the
field definition. By adding the “Field Backdoor” path, the information can be used for
any instance of that register simply by adding the %(FIELDS) variable for the “Block
Instance Backdoor”.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Back Door Access
In the generated UVM, the HDL path argument in the configure method is left blank and
add_hdl_path_slice statements are added for each field as follows:
<reg_inst>.add_hdl_path_slice(“<field_path”, offset, width, 0,
<kind>);
• The “Block Backdoor” is typically used for the top-level block (see the example in
Figure 5-3) and would contain the hierarchy path from the simulator root down to the
top-level block, for example top.dut. Depending on the hierarchical structure of the
design, “Block Backdoor” may be left blank for lower-level blocks.
In the example, reg_block is the top-level block. Therefore, the “Block Backdoor” path
is specified as top.dut.
The path is added for the block instance as follows:
• For the “Block Instance Backdoor”, there are several cases according to which the
output will be affected:
a. Register Instance without Fields:
In case of a register without fields (or when there is only one field spanning the
register width), the path is the name of the register signal being assigned within the
flip-flop always block, not the label of the always block which may be shown in the
simulator hierarchy window.
The path is added into the configure statement for the block instance as follows:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Supporting Back Door Access
c. Array of Registers:
For an array of register instances, the system variable %(DIM) can be used in the
path name. For example: data_small_mem_h_array_%(DIM)_local
This will be automatically expanded in the generated UVM as follows:
d. Sub-block Instance:
The path for a sub-block instance (if required) is the instance name in the block, in the
current example it is called sub_block. In the generated UVM output, this would appear
in the configure statement as follows:
• Following the above example, the resulting UVM backdoor paths used in the simulator
would be as follows:
/top.dut.other_field_status_reg_h_local
/top.dut.ctrl_bit_status_reg_h_local
/top.dut.myField_RegB_h_local
/top.dut.field2_small_mem_h_array_0_local
/top.dut.field1_small_mem_h_array_0_local
/top.dut.field2_small_mem_h_array_1_local
/top.dut.field1_small_mem_h_array_1_local
/top.dut.field2_small_mem_h_array_2_local
/top.dut.field1_small_mem_h_array_2_local
/top.dut.field2_small_mem_h_array_3_local
/top.dut.field1_small_mem_h_array_3_local
/top.dut.field2_small_mem_h_array_4_local
/top.dut.field1_small_mem_h_array_4_local
/top.dut.field2_small_mem_h_array_5_local
/top.dut.field1_small_mem_h_array_5_local
/top.dut.field2_small_mem_h_array_6_local
/top.dut.field1_small_mem_h_array_6_local
/top.dut.field2_small_mem_h_array_7_local
/top.dut.field1_small_mem_h_array_7_local
/top.dut.sub_block_inst.regAfield2_RegA_h_local
/top.dut.sub_block_inst.regAfield1_RegA_h_local
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
OVM Output
OVM Output
The OVM verification environment is composed of several components, among which is the
OVM register package. For example, you may have the top level, the RTL, a SystemVerilog
interface wrapper around the RTL, and the actual register definitions. This last file can be either
written manually or generated automatically using Register Assistant. The generated OVM file
should contain the description of your imported registers.
Register Assistant’s OVM generator supports the usage of both the 1.0 and 2.0 OVM register
packages. For the 2.0 OVM register package, two levels of support are provided and are labeled
as 2.0 and 2.2. The OVM 2.2 provides extended support which covers additional features
provided through the OVM 2.0 register package, for example using macros instead of methods
to add fields, using ovm_report_info for logging reasons.
To generate the OVM register package, you have to write the following command in the control
file:
# <comment>
<generator_language>, <generator_name>, <file_name>, <OVM Register Package
Version>, <OVM Output Directory/Location>
For example:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generated OVM File
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generated OVM File
Format
The OVM file is basically composed of several sections as shown in the following figure:
• Defining the Register Package — Contains the definition of the register package and
the required imports.
• Defining Register Objects — Contains the definitions of registers. It should be noted
that there are two types of registers: registers in which data is a whole bit vector and
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generated OVM File
registers in which data is partitioned into fields. So, before defining registers, the type of
registers has to be defined first as in the following example:
Registers are defined by extending the class ovm_register and passing the register type
as a parameter as in the following example:
class stopwatch_csr extends ovm_register #(stopwatch_csr_t);
• Defining Register Files — Contains the definitions of register files with instances of the
registers that constitute each file. See the following example:
• Defining Register Maps — Contains the definitions of the register map with instances
of the register files in it. The address offset of each register file is specified as shown in
the below example. Finally, the register map is loaded.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generated OVM File
Note
Note that Register Assistant calculates the addresses in the generated OVM file
using certain inputs in your register definitions. These inputs are provided as
arguments for the “add register” method in the OVM file: add_register(<Register
name>, <Offset_address>, <ovm_register_base >. For example:
add_register(VALUE.get_fullname(), 'h4, VALUE);
So the register address is taken directly from the offset address of the register instances.
In case of multiple instances of the same register (having the dimension greater than 1),
the offset address is calculated as follows: register instance’s offset + register definition
size.
Example
Refer to “OVM Output Example” on page 239 to view an example OVM register package
generated by Register Assistant.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
HTML Output
HTML Output
Register Assistant allows you to generate HTML files containing description of your imported
register definitions, thus automating the creation of documentation.
To generate HTML files, you have to write the following command in the control file:
# <comment>
<generator_language>, <generator_name>, <HTML Output Directory/Location>
For example:
Note that if you are using Register Assistant in batch mode, then you have to write the above
command manually in the control file. If you are using Register Assistant through an interface
tool such as HDL Designer Series, you will be able to enter your import, checks and output
settings through the interface and then the control file will be auto-generated. Refer to “Control
File” on page 23 for further information.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
HTML Output
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
HTML Output
• Index files that offer different ways to view the register documentation:
o Index.html:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
HTML Output Script File
o Index2.html: uses two frames to provide a register tree down the left hand side which
can be expanded to show the fields within each register in addition to the
corresponding register details on the right hand side.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
HTML Output Script File
The default templates (.ftl) and cascading style sheet (.css), and also the images used in the
generated HTML files are available on the following path: <installation_folder>\
registerassistant\resources\templates\html
You have the ability to customize the above mentioned files to affect your HTML output. For
example, you can control which register information to show, the heading types, the font types.
Alternatively, you can use the environment variable RA_TEMPLATE_DIR to point to other
templates (.ftl and .css files) outside Register Assistant’s install tree. Make sure to save your
template files in a directory called html and to point to its parent directory when setting the
environment variable. By default, this environment variable points to the parent directory of the
html directory shipped with Register Assistant: <installation_folder>\registerassistant\
resources\templates\
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
HTML Output Script File
Format
The script file that affects the generated HTML files is basically composed of several sections
as shown in the following figure:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
HTML Output Script File
• Imports — Contains the imports required for the script. The below imports can be used:
o The following import is used to support any calls made to Register Assistant’s data
model. This import is mandatory.
importPackage(com.mentor.regassist.dm);
o The following import is used to support any calls made to the template utility. This
import is mandatory.
importClass(com.mentor.regassist.generator.TemplateUtil);
The template utility enables you to generate files based on the available .ftl
templates. It obtains the required data from the current project, for example the block
data, and passes it to the corresponding HTML template. These templates define
how the data will be organized in the HTML file.
o The following import is used to support any calls made to the generator utility. This
import is mandatory.
importClass(com.mentor.regassist.generator.GeneratorUtil);
The generator utility enables you to prepare the location in which the generated
output will be placed.
o The following import is used to pass information to the template. This import is
optional.
importClass(java.util.HashMap);
o The following import is used to be able to print log messages, whether status or error
messages. This import is optional.
importClass(com.mentor.svassist.common.util.EcLog);
Note that any messages will appear in the console of Register Assistant. If you are
using Register Assistant through an interface tool such as HDL Designer Series, then
the messages will appear in a log tab for that tool.
• Generate Method — The Generate method is obligatory in the script. It encases the
entire code in the script as follows:
function generate(project, object, params) {
<code>
...
return 0;
}
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
HTML Output Script File
This method enables you to detect any errors and stop the flow at an early stage. This
can be done within the script by returning a negative integer at any time to indicate that
an error has occurred, and consequently the flow will stop.
If the Generate method is missing in the script, an error is raised as in the following
example:
# Error: Error executing javascript generator 'D:\RA\examples\
html.js', missing generate method.
• Verifying Top Block is Defined — In this section, the script verifies that the top block
is available, and if it is not available, the generation stops
• Preparing Output’s Destination — In this section, the script prepares the destination
folder in which the generated HTML files will be placed. This section mainly defines
the path of the destination folder, deletes old content in this folder and then copies the
necessary images and the cascading style sheet (which the HTML files will use).
• Passing Register Data to HTML — In this section, the script gets the register data
from the current project and passes it to the HTML templates for generation. It contains
sub sections for blocks, sub-blocks, registers and memories, and each one uses a
different template. For example, the script gets data on memories from the current
project and uses the memoryDef.ftl template to generate HTML output in a specific
destination. This is where the actual generation occurs using the calls made to
TemplateUtil.generate.
Refer to Example, below. You can also refer to the documentation of Register Assistant’s APIs
on the path: <installation_folder>\registerassistant\api\index.html.
Example
To view an example script, refer to the default script available with Register Assistant on
<installation_folder>\registerassistant\examples\html.js.
You can also refer to the documentation of Register Assistant’s APIs on the path:
<installation_folder>\registerassistant\api\index.html.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Output
RTL Output
In a typical register-based design flow, the hardware development team needs to write Verilog/
VHDL RTL to define and access design registers. This can be a tedious job, especially if the
design contains thousands of registers each of which has different register fields of different
access modes.
Register Assistant provides a mechanism by which you can generate synthesizable VHDL/
Verilog RTL code from register definition files. Any change in any of the register definitions
will only require a simple run through Register Assistant to get the updated RTL code.
• Register blocks having read, write and reset logic corresponding to all registers inside
the block.
You can instantiate these blocks inside your design to access the registers in a front door
fashion.
• A bus bridge which will map a Register Assistant generated generic bus to the used
system bus.
Figure 5-6. RTL Generator Output
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Specifying RTL Input
Tip
To specify input for the RTL generator:
The input files of a stopwatch example along with an example control file can be found
on the following path:
<installation_folder>\registerassistant\examples\rtl
Procedure
1. Decide on your Input Files Format
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Specifying RTL Input
The RTL generator accepts register description files in CSV or JavaScript format. For
more information on Register Assistant input formats refer to “Register Assistant
Inputs” on page 31.
2. Fill in your Input files with Register/Block Descriptions
Upon deciding on the input format you wish to use, you would then have to make sure
that you provide a complete description of your hardware register objects in a fashion
that is correctly translated by Register Assistant. The following steps outline the objects
you need to define for ensuring correct and complete RTL code:
a. Register Objects — Each register is defined by a set of basic properties outlined in
Table 5-6.
b. Register Field Object — Each register may consist of one or more fields. Each field
is defined by a set of properties outlined in Table 5-7.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Specifying RTL Input
Note
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Specifying RTL Input
Note
Caution
If you define the optional CSV column “Block Instance Type” as being of type
“memory”, Register Assistant will not instantiate memories in the generated
RTL output. You should manually instantiate memories in the generated RTL output
and decode their corresponding bus signals. Refer to the CSV Columns list for
information on the available block properties.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Specifying Software and Hardware Access Modes
c. Token cases
d. Naming conventions
e. Other miscellaneous properties
Procedure
1. The software access mode describes how the processor can write and/or read register
values using the bus protocol. Addressing is at the register level.
2. Specify an access mode for the field “Field Access”.
Refer to Figure 5-8 on page 121 with supported SW access modes. You can also refer to
SW Access Modes table to view a list of the supported access modes.
3. The hardware access mode describes how hardware can provide inputs and/or outputs to
the register. Connections are at the field level.
4. Specify an access mode for the field “Field HW Access”. Select from one of the
supported HW access modes in the H/W Access Modes table.
Or:
5. Enter defined conditions and actions to explicitly define the HW access mode in the
“Field Condition” and “Field Action”.
Note
The Field Condition and Field Action properties accept system variables. Refer to
the Variables table for a list of the supported variables.
Examples
Examine the code for a field with a Read Write 1 to Clear software access and a Read Write 0 to
Clear hardware access.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Specifying the Bus Protocol
//------------------------------------------------------------
// Field: fld_rw0c_l
// Width: 1 , Offset: 0
// SW Access: RW-Write-1-to-Clear , HW Access: RW-Write-0-to-Clear
//------------------------------------------------------------
always @ (posedge clock or negedge reset)
begin : reg_reg_rw0c_l_fld_rw0c_l_ireg_rw0c_l_local
// Reset
// The field reset action.
if ( !reset )
fld_rw0c_l_ireg_rw0c_l_local <= 1'b0;
// SW:RW-Write-1-to-Clear
// If the write enable signal is asserted, the field is cleared when
the corresponding bits in the write data bus equals 1, otherwise the
value is unchanged.
else if (register_we_ireg_rw0c_l)
fld_rw0c_l_ireg_rw0c_l_local <= (fld_rw0c_l_ireg_rw0c_l_local &
~wdata[0]);
// HW:RW-Write-0-to-Clear
// Clear the field when the signal fld_rw0c_l_ireg_rw0c_l_clr_n is
asserted.
else
fld_rw0c_l_ireg_rw0c_l_local <= fld_rw0c_l_ireg_rw0c_l_local &
fld_rw0c_l_ireg_rw0c_l_clr_n;
end
Note
* Constant value fields, that is, fields that have a single constant value with no reset, require
the following: First, the Field Access and Field HW Access should be set either as RO
(read-only) or as None. Second, the field should have one default action which is the constant
itself, and the condition should be left empty in this case.
* If the Field Access is not available, the RTL generator will use the value of the Register
Access. Similarly, if the Field HW Access is not available, the RTL generator will use the value
of the Register HW Access.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generic Bus and Bus Bridge
Procedure
1. Specify a value for the parameter “rtl.BUS_TYPE”.
2. Currently, there is only one bus type supported: AMBA_APB. The values for this
parameter can be “AMBA_APB” to generate AMBA_APB bus bridge, or “None” and
in that case the bus bridge will not be generated. The default value is “None”.
3. No more than one bus bridge file is generated for each project. The bus bridge file is
generated in Verilog if all the AMBA_APB blocks' language is Verilog and the bus
bridge file is generated in VHDL if all the AMBA_APB blocks' language is VHDL. If
the AMBA_APB blocks' language is mixed (VHDL and Verilog), then an arbitrary
language is used for the bus bridge file.
Note
The default name of the generated bus bridge file is "apb_bridge.v" or
"apb_bridge.vhd". You can control the name of the file through the parameter
“rtl.APB_BRIDGE_FILE_NAME”. Refer to “Parameters” on page 213 for general
information on parameters and to RTL Parameters table for a list the supported bus
settings parameters.
Tip
: The generated bus bridge is based on the template located on the path
<installation_folder>\registerassistant\resources\templates\rtl.
The Generic Bus is split into separate READ and WRITE signals to support the interfacing to
more advanced protocols that allow read and write operations from/to different addresses at the
same time if required. To facilitate this, separate READ and WRITE strobes are also provided.
Figure 5-7 shows the interfacing between the generic bus signals and the AMBA_APB system
bus via the bus bridge.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generic Bus and Bus Bridge
The following table describes the signals within the generic bus.
Table 5-10. Generic Bus Signal Descriptions
Signal Mode Description
Common
clock Master Clock. Optionally rising (default) or falling edge.
reset Master Reset. Optionally active low (default) or active high.
Read Bus
rstrobe Master Read Strobe. Activates a register read access when HIGH.
raddr Master Read Address. Address of the register whose content is to be read.
rdata Slave Read Data. The content of the addressed register is placed on this
bus when RSTROBE is HIGH.
rack Slave Read Acknowledge. Asserted HIGH when RDATA is valid. This
can be on the current clock edge if “Read Data Mux Logic Type”
is set to ASYNC or the next clock edge if set to SYNC.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generic Bus and Bus Bridge
The following tables show how the signals in the generic bus and the system bus are mapped to
one another.
Table 5-11. Common Connections
From To Special Conditions (if any)
PCLK clock
PRESETn reset
rdata PRDATA Only if the PSEL signal is high
PWDATA wdata
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generic Bus and Bus Bridge
Note
The APB PSTRB signal is not supported in the registers generated by Register Assistant and
hence the PSTRB signal is not supported on the bus bridge as well. It will be connected as a
stub.
Note that the register write enables, Write Acknowledge (wack) and Write Address Error
(waddrerr) signals will be asserted when the Write Strobe (wstrobe) is asserted.
Likewise, the Read Data (rdata), Read Acknowledge (rack) and Read Address Error (raddrerr)
signals will be asserted when the Read Strobe (rstrobe) is asserted.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Preparing the Control File
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Understanding RTL Intrinsic Checks
See the following note and error examples resulting from this check:
Instance Addresses
Checks that each block's instances addresses fall within the block address range.
See the following note and error examples resulting from this check:
See the following note and error examples resulting from this check:
Block Names
Checks that block names are not VHDL or Verilog keywords.
See the following note and error examples resulting from this check:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Understanding RTL Intrinsic Checks
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated RTL File
File Content
The generated file typically contains a declarations section and register read/write logic
sections.
Declarations Section
The Declarations section contains the Module/Entity port list and various local signals.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated RTL File
2. Local Signals
Local signals are those that are not part of the interface. They can be listed as follows:
a. Write enables for each register with SW write access:
"reg register_we_reg_<regName>
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated RTL File
c. Auxiliary Signals:
i. Internal for those not required in the interface
ii. Local for pre-flipflop signals
iii. Local for queued fields
Contains the write logic on both the register and field levels. Refer to Figure 5-8 on page 121.
1. Write Address Decode Logic — Contains the write address decode and write enable
logic at the register level and is common to all field access modes.
The block’s code starts by initializing a set of local signals: “write enable signals” for all
fields apart from those who have a true read-only access mode, the write acknowledge
“wack” and the write address error “waddrerr” signals.
register_we_CHn_CSR_reg = 1'b0;
register_we_CHn_SZ_reg = 1'b0;
register_we_CHn_A0 = 1'b0;
register_we_CHn_AM0 = 1'b0;
register_we_CHn_A1 = 1'b0;
register_we_CHn_AM1 = 1'b0;
register_we_CHn_DESC_reg = 1'b0;
register_we_CHn_SWPTR_reg = 1'b0;
waddrerr = 1'b0;
wack = 1'b0;
This is followed by checking whether the block is in write mode (wstrobe), in which
case the appropriate writable register is asserted write enable and write acknowledge is
set. Otherwise, all write enables for writable registers are cleared as well as the write
acknowledge.
If the write address is not found, assert the write address error flag (waddrerr)
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated RTL File
if (wstrobe)
begin
case (waddr)
CHn_CSR_reg_addr :
begin
register_we_CHn_CSR_reg = 1'b1;
end
CHn_SZ_reg_addr :
begin
register_we_CHn_SZ_reg = 1'b1;
end
CHn_A0_addr :
begin
register_we_CHn_A0 = 1'b1;
end
..........................
..........................
default :
begin
waddrerr = 1'b1;
end
endcase
wack = 1'b1;
end
end
Note
Fields inside registers with Access value = “Read-Only” have no SW write logic.
2. Register Field Logic — Contains the write logic related to register fields.
Fields within the same register may have different access modes and accordingly
different write logic. For fields with defined HW and SW access modes, SW access
takes precedence over HW access.
The generated code block contains an always block/proc with a common reset portion
for all field access modes and a write logic portion that follows the defined access mode.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated RTL File
// Field logic
always @ (posedge clock)
begin
// Reset
if ( !reset )
<field> <= 'b0;
// SW Access
else if (<SW write enable>)
.. SW access logic goes here
// HW Access (supplied)
else if (<HW condition(s)>)
.. HW access logic goes here
// HW Access (user)
else if (<HW condition(s)>)
<field> <= <field>_hw_next;
end
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated RTL File
//--------------------------------------------------------------
// FIELD: STOP
// WIDTH: 1 , OFFSET: 9
// SW_ACCESS: write-only , HW_ACCESS : read-write
//--------------------------------------------------------------
Read logic within a block works on the register level and not the field level. Fields are assigned
to the appropriate locations within the overall register and the register value is assigned to the
read data bus. Register field values are read by the CPU via the read data bus.
1. Defining Read Bus Multiplexer — Contains the logic where readable field values are
loaded into the appropriate locations in the corresponding register.
assign MY_READ_MUX_INPUT_CHN_A0[31:2] = ADDRESS_CHN_A0;
assign MY_READ_MUX_INPUT_CHN_A0[1:0] = DEFAULT_RDATA[1:0];
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Customizing Generated Output
2. Assigning Read Register value to the Read Data Bus — Contains the logic that
assigns the register value on the read data bus after checking that the block is in read
mode (rstrobe).
begin : read_bus_mux
// PUT REGISTER VALUE ON READ DATA BUS
MY_REGISTER_RE_CHN_CSR_REG = 1'b0;
MY_READ_ACK = 1'b0;
RADDRERR = 1'b0;
if (MY_RSTROBE )
begin
case (MY_RADDR )
CHN_CSR_REG_ADDR :
begin
MY_RDATA = MY_READ_MUX_INPUT_CHN_CSR_REG;
MY_REGISTER_RE_CHN_CSR_REG = 1'b1;
endbegin
MY_RDATA = MY_READ_MUX_INPUT_CHN_SWPTR_REG;
end
default :
begin
MY_RDATA = DEFAULT_RDATA;
RADDRERR = 1'b1;
end
endcase
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Customizing Generated Output
Note
1. Condition and actions string parsing is limited so not all cases can be handled.
2. No inference for the width of the signal. Always assumed to be of size 1.
Nonetheless, Register Assistant allows you to optionally have those local signals defined as
pulses for output ports instead in the generated RTL code. You can choose to generate pulses
that are read-write, read only, or write only.
This is done by setting the following parameter in the CSV input file. On the level of the
register(s), add two columns for the “Register Parameter Name” and “Register Parameter
Value”.
Table 5-15. Read/Write Output Pulse Parameter
Register Parameter Register De Sc
Name Parameter Value fau op
lt e
rtl.PULSE_OUTPUT RW, R, W or No Re
None. ne gis
ter
An alias “Register Output Pulse” is defined for the “rtl.PULSE_OUTPUT” parameter in the
csv.js file. You can use this alias by adding a single column titled “Register Output Pulse” on
the register level and directly give this column the value RW, R, W or None. Refer to
“Parameters” on page 213 for more information on using parameters.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Customizing Generated Output
According to the parameter value you set, Register Assistant will define an output pulse in the
generated code instead of the local signals as follows:
In this example, there are two registers each with a single 1-bit field:
• REG1 is designed to show a write pulse (Register Output Pulse set to “W”) and has the
software access mode as RW and the hardware access mode as RO.
• REG2 is designed to show a read pulse (Register Output Pulse set to “R”) and has the
software access mode as R (read-only, no flip-flop) and the hardware access mode as
WO.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Customizing Generated Output
module top
#(
parameter ADDR_WIDTH=4,
parameter DATA_WIDTH=32
)
(
// FIELD OUTPUT PORTS
output reg pulse_field_REG1_inst,
// INPUT PORTS
input wire clear_field_REG2_inst_ip,
// ADDRESS PARAMETERS
localparam REG1_INST_ADDR = 4'h0;
localparam REG2_INST_ADDR = 4'h4;
//---------------------------------------------------------------------
// WRITE ADDRESS DECODE
//---------------------------------------------------------------------
always @ ( * )
begin : write_enable
wen_REG1_inst = 1'b0;
waddrerr = 1'b0;
wack = 1'b0;
if (wstrobe)
begin
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Customizing Generated Output
case (waddr)
REG1_INST_ADDR:
begin
wen_REG1_inst = 1'b1;
end
default:
begin
waddrerr = 1'b1;
end
endcase
wack = 1'b1;
end
end
//------------------------------------------------------------
// Register: REG1
// Pulse test
// SW Access : read-write
// Address Offset: 0x0
// HW Access : read-write
// Output Pulse : W (when written)
//
// Instance: REG1_inst
// Pulse test
// Address Offset: 0x0
// Reset Value :
//
// Fields:
// 0 pulse_field (SW:read-write, HW:read-only)
//------------------------------------------------------------
// Field: pulse_field
// Width: 1 , Offset: 0
// SW Access: read-write , HW Access: read-only
//------------------------------------------------------------
always @ (posedge clock)
begin : reg_reg1_pulse_field_reg1_inst
// Reset
if ( !reset )
pulse_field_REG1_inst <= 1'b0;
// SW:read-write
else if (wen_REG1_inst)
pulse_field_REG1_inst <= wdata[0];
end
//------------------------------------------------------------
// Register: REG2
// Clear test
// SW Access : read-write
// Address Offset: 0x0
// HW Access : read-write
// Output Pulse : R (when read)
//
// Instance: REG2_inst
// Clear test
// Address Offset: 0x4
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Customizing Generated Output
// Reset Value :
//
// Fields:
// 0 clear_field (SW:RO-No-Field, HW:write-only)
//------------------------------------------------------------
// Field: clear_field
// Width: 1 , Offset: 0
// SW Access: RO-No-Field , HW Access: write-only
//------------------------------------------------------------
//---------------------------------------------------------------------
// READ BUS MULTIPLEXER
//---------------------------------------------------------------------
assign mux_REG1_inst[31:1] = DEFAULT_RDATA[31:1]; // Default read value
for un-assigned portion
assign mux_REG1_inst[0] = pulse_field_REG1_inst;
always @ ( * )
begin : read_bus_mux
// PUT REGISTER VALUE ON READ DATA BUS
ren_REG2_inst = 1'b0;
rack = 1'b0;
raddrerr = 1'b0;
if (rstrobe )
begin
case (raddr )
REG1_INST_ADDR:
begin
rdata = mux_REG1_inst;
end
REG2_INST_ADDR:
begin
rdata = mux_REG2_inst;
ren_REG2_inst = 1'b1;
end
default:
begin
rdata = DEFAULT_RDATA;
raddrerr = 1'b1;
end
endcase
rack = 1'b1;
end
else
begin
rdata = DEFAULT_RDATA;
end
end
endmodule
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Entering Data to Register Assistant
Let us imagine a simple case where a system consists of a processor communicating with
several H/W devices through the system bus. Each device is assigned some address range in the
address space (that is, when the processor needs to communicate with one device, it needs to set
the address to a value in that range). The processor and the H/W devices communicate with one
another through CSR (Control Status Registers).
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Entering Data to Register Assistant
Table 5-16. Register Definition CSV File for the Simple Design Example
Register Register Register Register Register Field Field Field Field Field Field
Name Width Access HW Reset Name Offset Width Access HW Reset
Access Value Access Value
reg1 32 rw rw 0x0 fld1_reg1 0 12 rw ro 0x0
reg1 fld2_reg1 12 20 rw rw 0x0
reg2 32 rw rw 0x0 fld1_reg2 0 4 rw1c rw 0x0
reg2 fld2_reg2 4 12 rw wo 0x0
reg2 fld3_reg2 16 16 ro wo 0x0
Table 5-17. Block Definition CSV File for the Simple Design Example
Block Name Block Block BlockMap BlockMap BlockMap
Component Instance Name Instance Instance
Name Name Name Address
deviceX reg1 i1_reg1 Default i1_reg1 0x00
deviceX reg2 i2_reg2 Default i2_reg2 0x04
deviceX reg1 i3_reg1 Default i3_reg1 0x08
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
4. In a design with multiple blocks, add all our design blocks in a top block giving each
block an address offset with respect to the address space. (In the example, the device
needs to be put in address Offset 0x10.)
# Run checks
java, check, dontStop
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
module deviceX
#(
parameter ADDR_WIDTH=4,
parameter DATA_WIDTH=32
)
(
// FIELD OUTPUT PORTS
output reg [19:0] fld2_reg1_i1_reg1,
output reg [11:0] fld1_reg1_i1_reg1,
output reg [3:0] fld1_reg2_i2_reg2,
output reg [19:0] fld2_reg1_i3_reg1,
output reg [11:0] fld1_reg1_i3_reg1,
// INPUT PORTS
input wire [19:0] fld2_reg1_i1_reg1_ip,
input wire [15:0] fld3_reg2_i2_reg2_ip,
input wire [11:0] fld2_reg2_i2_reg2_ip,
input wire [3:0] fld1_reg2_i2_reg2_ip,
input wire [19:0] fld2_reg1_i3_reg1_ip,
// FLIP-FLOP SIGNALS
reg [15:0] fld3_reg2_i2_reg2_local;
reg [11:0] fld2_reg2_i2_reg2_local;
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
// ADDRESS PARAMETERS
localparam I1_REG1_ADDR = 4'h0;
localparam I2_REG2_ADDR = 4'h4;
localparam I3_REG1_ADDR = 4'h8;
//----------------------------------------------------------------------
// WRITE ADDRESS DECODE
//--------------------------------------------------------------------
always @ ( * )
begin : write_enable
register_we_i1_reg1 = 1'b0;
register_we_i2_reg2 = 1'b0;
register_we_i3_reg1 = 1'b0;
waddrerr = 1'b0;
wack = 1'b0;
if (wstrobe)
begin
case (waddr)
I1_REG1_ADDR:
begin
register_we_i1_reg1 = 1'b1;
end
I2_REG2_ADDR:
begin
register_we_i2_reg2 = 1'b1;
end
I3_REG1_ADDR:
begin
register_we_i3_reg1 = 1'b1;
end
default:
begin
waddrerr = 1'b1;
end
endcase
wack = 1'b1;
end
end
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
//------------------------------------------------------------
// Register: reg1
// SW Access : read-write
// Address Offset:
// HW Access : read-write
//
// Instance: i1_reg1
// Address Offset: 0x00
// Reset Value :
//
// Fields:
// 31:12 fld2_reg1 (SW:read-write, HW:read-write)
// 11:0 fld1_reg1 (SW:read-write, HW:read-only)
//------------------------------------------------------------
// Field: fld2_reg1
// Width: 20 , Offset: 12
// SW Access: read-write , HW Access: read-write
//------------------------------------------------------------
always @ (posedge clock or negedge reset)
begin : reg_reg1_fld2_reg1_i1_reg1
// Reset
if ( !reset )
fld2_reg1_i1_reg1 <= 20'h00000;
// SW:read-write
else if (register_we_i1_reg1)
fld2_reg1_i1_reg1 <= (wdata[31:12]);
// HW:read-write
else
fld2_reg1_i1_reg1 <= fld2_reg1_i1_reg1_ip;
end
//------------------------------------------------------------
// Field: fld1_reg1
// Width: 12 , Offset: 0
// SW Access: read-write , HW Access: read-only
//------------------------------------------------------------
always @ (posedge clock or negedge reset)
begin : reg_reg1_fld1_reg1_i1_reg1
// Reset
if ( !reset )
fld1_reg1_i1_reg1 <= 12'h000;
// SW:read-write
else if (register_we_i1_reg1)
fld1_reg1_i1_reg1 <= (wdata[11:0]);
end
//------------------------------------------------------------
// Register: reg2
// SW Access : read-write
// Address Offset:
// HW Access : read-write
//
// Instance: i2_reg2
// Address Offset: 0x04
// Reset Value :
//
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
// Fields:
// 31:16 fld3_reg2 (SW:read-only, HW:write-only)
// 15:4 fld2_reg2 (SW:read-write, HW:write-only)
// 3:0 fld1_reg2 (SW:RW-Write-1-to-Clear, HW:read-write)
//------------------------------------------------------------
// Field: fld3_reg2
// Width: 16 , Offset: 16
// SW Access: read-only , HW Access: write-only
//------------------------------------------------------------
always @ (posedge clock or negedge reset)
begin : reg_reg2_fld3_reg2_i2_reg2_local
// Reset
if ( !reset )
fld3_reg2_i2_reg2_local <= 16'h0000;
// HW:write-only
else
fld3_reg2_i2_reg2_local <= fld3_reg2_i2_reg2_ip;
end
//------------------------------------------------------------
// Field: fld2_reg2
// Width: 12 , Offset: 4
// SW Access: read-write , HW Access: write-only
//------------------------------------------------------------
always @ (posedge clock or negedge reset)
begin : reg_reg2_fld2_reg2_i2_reg2_local
// Reset
if ( !reset )
fld2_reg2_i2_reg2_local <= 12'h000;
// SW:read-write
else if (register_we_i2_reg2)
fld2_reg2_i2_reg2_local <= (wdata[15:4]);
// HW:write-only
else
fld2_reg2_i2_reg2_local <= fld2_reg2_i2_reg2_ip;
end
//------------------------------------------------------------
// Field: fld1_reg2
// Width: 4 , Offset: 0
// SW Access: RW-Write-1-to-Clear , HW Access: read-write
//------------------------------------------------------------
always @ (posedge clock or negedge reset)
begin : reg_reg2_fld1_reg2_i2_reg2
// Reset
if ( !reset )
fld1_reg2_i2_reg2 <= 4'h0;
// SW:RW-Write-1-to-Clear
else if (register_we_i2_reg2)
fld1_reg2_i2_reg2 <= (fld1_reg2_i2_reg2 & ~wdata[3:0]);
// HW:read-write
else
fld1_reg2_i2_reg2 <= fld1_reg2_i2_reg2_ip;
end
//------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
// Register: reg1
// SW Access : read-write
// Address Offset:
// HW Access : read-write
//
// Instance: i3_reg1
// Address Offset: 0x08
// Reset Value :
//
// Fields:
// 31:12 fld2_reg1 (SW:read-write, HW:read-write)
// 11:0 fld1_reg1 (SW:read-write, HW:read-only)
//------------------------------------------------------------
// Field: fld2_reg1
// Width: 20 , Offset: 12
// SW Access: read-write , HW Access: read-write
//------------------------------------------------------------
always @ (posedge clock or negedge reset)
begin : reg_reg1_fld2_reg1_i3_reg1
// Reset
if ( !reset )
fld2_reg1_i3_reg1 <= 20'h00000;
// SW:read-write
else if (register_we_i3_reg1)
fld2_reg1_i3_reg1 <= (wdata[31:12]);
// HW:read-write
else
fld2_reg1_i3_reg1 <= fld2_reg1_i3_reg1_ip;
end
//------------------------------------------------------------
// Field: fld1_reg1
// Width: 12 , Offset: 0
// SW Access: read-write , HW Access: read-only
//------------------------------------------------------------
always @ (posedge clock or negedge reset)
begin : reg_reg1_fld1_reg1_i3_reg1
// Reset
if ( !reset )
fld1_reg1_i3_reg1 <= 12'h000;
// SW:read-write
else if (register_we_i3_reg1)
fld1_reg1_i3_reg1 <= (wdata[11:0]);
end
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
always @ ( * )
begin : read_bus_mux
// PUT REGISTER VALUE ON READ DATA BUS
rack = 1'b0;
raddrerr = 1'b0;
if (rstrobe )
begin
case (raddr )
I1_REG1_ADDR:
begin
rdata = read_mux_input_i1_reg1;
end
I2_REG2_ADDR:
begin
rdata = read_mux_input_i2_reg2;
end
I3_REG1_ADDR:
begin
rdata = read_mux_input_i3_reg1;
end
default:
begin
rdata = DEF_RDATA_VAL;
raddrerr = 1'b1;
end
endcase
rack = 1'b1;
end
else
begin
rdata = DEF_RDATA_VAL;
end
end
endmodule
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
-- INPUT PORTS
fld2_reg1_i1_reg1_ip : IN wire (19 DOWNTO 0);
fld3_reg2_i2_reg2_ip : IN wire (15 DOWNTO 0);
fld2_reg2_i2_reg2_ip : IN wire (11 DOWNTO 0);
fld1_reg2_i2_reg2_ip : IN wire (3 DOWNTO 0) ;
fld2_reg1_i3_reg1_ip : IN wire (19 DOWNTO 0);
------------------------------------------------------------------------
ARCHITECTURE deviceX_arch OF deviceX IS
------------------------------------------------------------------------
-- READ/WRITE ENABLE SIGNALS
SIGNAL my_wei1_reg1 : std_logic ;
SIGNAL my_wei2_reg2 : std_logic ;
SIGNAL my_wei3_reg1 : std_logic ;
-- AUXILIARY SIGNALS
SIGNAL fld2_reg1_i1_reg1_buf : wire (19 DOWNTO 0);
SIGNAL fld1_reg1_i1_reg1_buf : wire (11 DOWNTO 0);
SIGNAL fld3_reg2_i2_reg2_local : wire (15 DOWNTO 0);
SIGNAL fld2_reg2_i2_reg2_local : wire (11 DOWNTO 0);
SIGNAL fld1_reg2_i2_reg2_buf : wire (3 DOWNTO 0) ;
SIGNAL fld2_reg1_i3_reg1_buf : wire (19 DOWNTO 0);
SIGNAL fld1_reg1_i3_reg1_buf : wire (11 DOWNTO 0);
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
-- ADDRESS PARAMETERS
CONSTANT I1_REG1_ADDR : wire := "0000"; -- 'h00
CONSTANT I2_REG2_ADDR : wire := "0100"; -- 'h04
CONSTANT I3_REG1_ADDR : wire := "1000"; -- 'h08
BEGIN
-----------------------------------------------------------------------
-- WRITE ADDRESS DECODE
-----------------------------------------------------------------------
write_enable : PROCESS (waddr , wstrobe)
BEGIN
my_wei1_reg1 <= '0';
my_wei2_reg2 <= '0';
my_wei3_reg1 <= '0';
waddrerr <= '0';
--------------------------------------------------------------
-- Register: reg1
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: i1_reg1
-- Address Offset: 0x00
-- Reset Value :
--
-- Fields:
-- 31:12 fld2_reg1 (SW:read-write, HW:read-write)
-- 11:0 fld1_reg1 (SW:read-write, HW:read-only)
--------------------------------------------------------------
-- Field: fld2_reg1
-- Width: 20 , Offset: 12
-- SW Access: read-write , HW Access: read-write
--------------------------------------------------------------
reg_reg1_fld2_reg1_i1_reg1 : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
--------------------------------------------------------------
-- Field: fld1_reg1
-- Width: 12 , Offset: 0
-- SW Access: read-write , HW Access: read-only
--------------------------------------------------------------
reg_reg1_fld1_reg1_i1_reg1 : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
fld1_reg1_i1_reg1_buf <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (my_wei1_reg1 = '1') THEN
fld1_reg1_i1_reg1_buf <= wdata(11 DOWNTO 0);
END IF;
END IF;
END PROCESS reg_reg1_fld1_reg1_i1_reg1;
--------------------------------------------------------------
-- Register: reg2
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: i2_reg2
-- Address Offset: 0x04
-- Reset Value :
--
-- Fields:
-- 31:16 fld3_reg2 (SW:read-only, HW:write-only)
-- 15:4 fld2_reg2 (SW:read-write, HW:write-only)
-- 3:0 fld1_reg2 (SW:RW-Write-1-to-Clear, HW:read-write)
--------------------------------------------------------------
-- Field: fld3_reg2
-- Width: 16 , Offset: 16
-- SW Access: read-only , HW Access: write-only
--------------------------------------------------------------
reg_reg2_fld3_reg2_i2_reg2_local : PROCESS (clock, reset)
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
BEGIN
-- Reset
IF (reset = '0') THEN
fld3_reg2_i2_reg2_local <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- HW:write-only
fld3_reg2_i2_reg2_local <= fld3_reg2_i2_reg2_ip;
END IF;
END PROCESS reg_reg2_fld3_reg2_i2_reg2_local;
--------------------------------------------------------------
-- Field: fld2_reg2
-- Width: 12 , Offset: 4
-- SW Access: read-write , HW Access: write-only
--------------------------------------------------------------
reg_reg2_fld2_reg2_i2_reg2_local : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
fld2_reg2_i2_reg2_local <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (my_wei2_reg2 = '1') THEN
fld2_reg2_i2_reg2_local <= wdata(15 DOWNTO 4);
-- HW:write-only
ELSE
fld2_reg2_i2_reg2_local <= fld2_reg2_i2_reg2_ip;
END IF;
END IF;
END PROCESS reg_reg2_fld2_reg2_i2_reg2_local;
--------------------------------------------------------------
-- Field: fld1_reg2
-- Width: 4 , Offset: 0
-- SW Access: RW-Write-1-to-Clear , HW Access: read-write
--------------------------------------------------------------
reg_reg2_fld1_reg2_i2_reg2 : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
fld1_reg2_i2_reg2_buf <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:RW-Write-1-to-Clear
IF (my_wei2_reg2 = '1') THEN
fld1_reg2_i2_reg2_buf <= (fld1_reg2_i2_reg2_buf AND (NOT wdata(3
DOWNTO 0)));
-- HW:read-write
ELSE
fld1_reg2_i2_reg2_buf <= fld1_reg2_i2_reg2_ip;
END IF;
END IF;
END PROCESS reg_reg2_fld1_reg2_i2_reg2;
--------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
What to Specify in the Control File
-- Register: reg1
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: i3_reg1
-- Address Offset: 0x08
-- Reset Value :
--
-- Fields:
-- 31:12 fld2_reg1 (SW:read-write, HW:read-write)
-- 11:0 fld1_reg1 (SW:read-write, HW:read-only)
--------------------------------------------------------------
-- Field: fld2_reg1
-- Width: 20 , Offset: 12
-- SW Access: read-write , HW Access: read-write
--------------------------------------------------------------
reg_reg1_fld2_reg1_i3_reg1 : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
fld2_reg1_i3_reg1_buf <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (my_wei3_reg1 = '1') THEN
fld2_reg1_i3_reg1_buf <= wdata(31 DOWNTO 12);
-- HW:read-write
ELSE
fld2_reg1_i3_reg1_buf <= fld2_reg1_i3_reg1_ip;
END IF;
END IF;
END PROCESS reg_reg1_fld2_reg1_i3_reg1;
--------------------------------------------------------------
-- Field: fld1_reg1
-- Width: 12 , Offset: 0
-- SW Access: read-write , HW Access: read-only
--------------------------------------------------------------
reg_reg1_fld1_reg1_i3_reg1 : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
fld1_reg1_i3_reg1_buf <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (my_wei3_reg1 = '1') THEN
fld1_reg1_i3_reg1_buf <= wdata(11 DOWNTO 0);
END IF;
END IF;
END PROCESS reg_reg1_fld1_reg1_i3_reg1;
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Alternative Resets
-----------------------------------------------------------------------
-- READ BUS MULTIPLEXER
-----------------------------------------------------------------------
read_mux_input_i1_reg1(31 DOWNTO 12) <= fld2_reg1_i1_reg1_buf;
read_mux_input_i1_reg1(11 DOWNTO 0) <= fld1_reg1_i1_reg1_buf;
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Alternative Resets
When importing register definitions from CSV files, you need to do the following:
Procedure
1. Specify that the register requires an alternative reset. This is done through adding the
following parameter columns on the register level:
Note
Once you indicate the use of an alternative reset signal for a specific register (as
explained in step1), this alternative register will be used in the block containing the
register with the default attributes. If you need to specify attributes different from the
default, you have to explicitly set them on the block level (as explained in step 2).
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Alternative Resets
3. When importing register definitions from JavaScript files, you can specify that the
register requires an alternative reset using the following API:
register_name.addParameter ("rtl.USE_ALT_RESET", "True", "Using an
alternative reset.");
4. Similarly, you can specify the following attributes for the alternative reset signal on the
level of the block as follows:
block_name.addParameter ("rtl.ALT_RESET_NAME", "my_alt_reset", "The
name of the alternative reset signal.");
block_name.addParameter ("rtl.ALT_RESET_STYLE", "SYNC", "The style
of the alternative reset.");
block_name.addParameter ("rtl.ALT_RESET_ACTIVE_LEVEL", "HIGH", "The
active level of the alternative reset.");
block_name.addParameter ("rtl.ALT_RESET_BLOCK_LABEL_PREFIX",
"my_reten_", "The label for always blocks using the alternative
reset.");
Examples
This is an example of RTL code generated by Register Assistant. Note the use of alternative
resets in the example.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Alternative Resets
module block_reten_custom
#(
parameter ADDR_WIDTH=2,
parameter DATA_WIDTH=10
)
(
// FIELD OUTPUT PORTS
output reg fld_reten_ireg_reten,
// INPUT PORTS
input wire my_alt_reset , // Alternative Reset
input wire fld_reten_ireg_reten_ip,
// ADDRESS PARAMETERS
localparam IREG_RETEN_ADDR = 2'b00;
//------------------------------------------------------------
// Register: reg_reten
// SW Access : read-write
// Address Offset: 0x0
// HW Access : read-write
// Alt Reset : my_alt_reset (SYNC)
//
// Instance: ireg_reten
// Address Offset: 0x0
// Reset Value :
//
// Fields:
// 0 fld_reten (SW:read-only, HW:read-write)
//------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Software Resets
// Field: fld_reten
// Width: 1 , Offset: 0
// SW Access: read-only , HW Access: read-write
//------------------------------------------------------------
// Note that the prefix determined in Table 5-20 is used below in the
always block.
//--------------------------------------------------------------------
// READ BUS MULTIPLEXER
//--------------------------------------------------------------------
assign read_mux_input_ireg_reten[9:1] = DEF_RDATA_VAL[9:1]; // Default
read value for un-assigned portion
assign read_mux_input_ireg_reten[0] = fld_reten_ireg_reten;
always @ ( * )
begin : read_bus_mux
// PUT REGISTER VALUE ON READ DATA BUS
rack = 1'b0;
raddrerr = 1'b0;
if (rstrobe )
begin
case (raddr )
IREG_RETEN_ADDR:
begin
rdata = read_mux_input_ireg_reten;
end
default:
begin
rdata = DEF_RDATA_VAL;
raddrerr = 1'b1;
end
endcase
rack = 1'b1;
end
else
begin
rdata = DEF_RDATA_VAL;
end
end
endmodule
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Software Resets
A software reset enables you to change register values based on the occurrence of certain
triggers. It is specified on the field level. If a register has no declared fields, it can be specified
for the default field and thus affect the whole register. Moreover, one or more soft reset can be
specified for a single field.
In the Register assistant generated code a hard reset takes precedence over any of the optionally
defined software resets.
When importing register definitions from CSV files, you need to specify the soft reset signal,
the reset action and an optional comment to describe it. This is done through adding the
following CSV columns:
Table 5-21. Software Reset Input Example— CSV Columns
Soft Reset Column Name Soft Reset Column Value
Field Soft Reset Condition soft_reset
Field Soft Reset Action 16'h0000
Field Soft Reset Comment Soft reset for field1
When importing register definitions from JavaScript files, you can specify register software
resets using the following API:
addSoftResetConditionalLogic
Example
This is an example to show how field soft reset conditions are defined in Register Assistant and
how they appear in the generated code. In this example, we have two registers: Reg1 and Reg2.
Reg1 is a register with two fields and Reg2 is a register with no fields. Examine the CSV input
file and notice the field soft reset condition, field soft reset action and field soft reset comment
columns.
The code starts by automatically declaring signals found in the soft reset conditions/actions
columns that have not been declared elsewhere. These declarations can be enabled/disabled by
the parameter “rtl.DECLARE_INFERRED_SIGNALS”.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Software Resets
In the Register Field logic part of the code the soft reset will always be the first tested after the
hardware reset. The general order is:
else if (soft_reset)
field1_reg1_reg <= 0;
and not
else if (soft_reset)
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Software Resets
//------------------------------------------------------------
// Field: field1
// Width: 16 , Offset: 16
// SW Access: read-write , HW Access: read-write
//------------------------------------------------------------
// field1
//
always @ (posedge clock or negedge reset)
begin : reg_reg1_field1_reg1_reg
// Reset
if ( !reset )
field1_reg1_reg <= 16'h0000;
// Soft Reset
else if (soft_reset)
field1_reg1_reg <= 16'h0000; // Soft reset for field1
// SW:read-write
else if (wen_reg1_reg)
field1_reg1_reg <= wdata[31:16];
// HW:read-write
else
field1_reg1_reg <= field1_reg1_reg_ip;
end
//------------------------------------------------------------
// Field: field2
// Width: 16 , Offset: 0
// SW Access: read-write , HW Access: read-write
//------------------------------------------------------------
// field2
//
always @ (posedge clock or negedge reset)
begin : reg_reg1_field2_reg1_reg
// Reset
if ( !reset )
field2_reg1_reg <= 16'h0000;
// Soft Reset
else if (srst)
field1_reg1_reg <= 16'h1111; // Soft reset for field2
// SW:read-write
else if (wen_reg1_reg)
field2_reg1_reg <= wdata[15:0];
// HW:read-write
else
field2_reg1_reg <= field2_reg1_reg_ip;
end
For reg2 no fields are specified, Register assistant declares a default field and applies the
defined soft reset condition/action to it.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Byte Enable Support
//------------------------------------------------------------
// Register: reg2
// Reg with no fields
// SW Access : read-write
// Address Offset: 0xc
// HW Access : read-write
//
// Instance: reg2_reg
// inst2
// Address Offset: 0x0008
// Reset Value :
//
// Fields:
// 31:0 def_fld (SW:read-write, HW:read-write)
//------------------------------------------------------------
// Field: def_fld
// Width: 32 , Offset: 0
// SW Access: read-write , HW Access: read-write
//------------------------------------------------------------
// Default field for entire register - reg2
//
always @ (posedge clock or negedge reset)
begin : reg_reg2_def_fld_reg2_reg
// Reset
if ( !reset )
def_fld_reg2_reg <= 32'h00000000;
// Soft Reset
else if (sample && rcv_bit_cnt_cld == 7)
def_fld_reg2_reg <= 32'hFC; // Soft reset for reg2
// SW:read-write
else if (wen_reg2_reg)
def_fld_reg2_reg <= wdata;
// HW:read-write
else
def_fld_reg2_reg <= def_fld_reg2_reg_ip;
end
Note
For WO-WRITE-ONCE and RW-WRITE-ONCE access modes you will not be able to reset
the write once flag.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Byte Enable Support
The width of the byte_en signal depends on the size of largest register within a block using byte
enables. For a 64 bit register, Register Assistant will declare a byte enable signal of width 8 and
will generate the necessary write logic for the register fields.
When importing register definitions from CSV files, you need to do the following:
Procedure
1. Specify the register byte enable mode. Register Enable Mode can be “BYTE” or
“NONE” (or blank). This is done through the following parameter:
An alias “Register Enable Mode” is defined for the “rtl.Enable_Mode” parameter in the
csv.js file.You can use this alias if you want to use a single column to define the register
enable mode. Refer to “Parameters” on page 213 for more information on using
parameters.
2. Optionally specify the byte_enable signal name and level or use the default values using
the parameters in Table 5-23
Examples
This is an example to show how we can direct Register Assistant to use byte enable signals for
specific registers and how they appear in the generated code. Examine the CSV input file and
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Byte Enable Support
notice that we have used the Register Enable Mode alias for the “rtl.Enable_Mode” parameter.
reg2 is a byte enabled register which has a single 32 bits size default field.
Using the input in the example CSV file, Register Assistant declares a byte enable signal of
width 4 and gives it the default name “byte_en” as no other name value has been declared.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Byte Enable Support
// Instance: reg2_reg
// inst2
// Address Offset: 0x0008
// Reset Value : 0
//
// Fields:
// 31:0 def_fld (SW:read-write, HW:read-write)
//------------------------------------------------------------
// Field: def_fld
// Width: 32 , Offset: 0
// SW Access: read-write , HW Access: read-write
//------------------------------------------------------------
always @ (posedge clock or negedge reset)
begin : reg_reg2_def_fld_reg2_reg
// Reset
if ( !reset )
def_fld_reg2_reg <= 32'h00000000;
Write logic generated is based on the register size and the field SW access mode defined. The
access mode logic within each enabled byte is the same as if the register had a single field but
split into byte-sized sections.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Understanding RTL Field Signal Naming and Scope
// SW:read-write
else if (wen_reg2_reg)
begin
if (byte_en[0])
def_fld_reg2_reg[31:24]<= wdata[31:24];
if (byte_en[1])
def_fld_reg2_reg[23:16]<= wdata[23:16];
if (byte_en[2])
def_fld_reg2_reg[15:8]<= wdata[15:8];
if (byte_en[3])
def_fld_reg2_reg[7:0] <= wdata[7:0];
end
// HW (customized)
else if (eop)
def_fld_reg2_reg <= 0; // Clear if eop
else if (sop)
def_fld_reg2_reg <= 1; // Set if sop
else
def_fld_reg2_reg <= def_fld_reg2_reg_ip; // Otherwise assign value
of input
end
Refer to the RTL Parameters and RTL Variables reference tables. You can also refer to
“Parameters” on page 213.
%(FIELD_NAME)_%(REGISTER_INSTANCE_NAME)
Note that this naming convention should include the use of both the %(FIELD_NAME) and
%(REGISTER_ INSTANCE _NAME) variables somewhere within the expression.
This is the name that will be used for the field signal if it can be a port, otherwise, a “_local”
suffix will be added to indicate it is a local signal. Refer to Field Scope, below.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Understanding RTL Field Signal Naming and Scope
Which field input signals are generated depends on the HW access type for the field. The signal
will be of the form:
where:
Field Scope
Two additional field parameters can be used to control whether the generated input signals
(rtl.INPUT_SCOPE) and field signals (rtl.OUTPUT_SCOPE) are defined as ports or local
signals. Note that these parameters must be associated with individual fields and cannot be set
for the block or project.
The default value for these two parameters is “PORT”, however, there are a number of
conditions when the field signal in particular will always be a local signal rather than a port.
This is summarized in Table 5-24.
Table 5-24. RTL Field Signal Naming and Scope
Access Ports
SW HW IN PORT OUT PORT or Notes
LOCAL FIELD
All except RO N Specified by No input since HW
“R” rtl.OUTPUT_SCOPE access is read-only.
All except RW Specified by Specified by
“R” rtl.INPUT_SCOPE rtl.OUTPUT_SCOPE
All except RW0C Specified by Specified by
“R” rtl.INPUT_SCOPE rtl.OUTPUT_SCOPE
All except RW1C Specified by Specified by
“R” rtl.INPUT_SCOPE rtl.OUTPUT_SCOPE
All except RW0S Specified by Specified by
“R” rtl.INPUT_SCOPE rtl.OUTPUT_SCOPE
All except RW1S Specified by Specified by
“R” rtl.INPUT_SCOPE rtl.OUTPUT_SCOPE
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Understanding RTL Field Signal Naming and Scope
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Pipelining Overview
Generating RTL output for a large input of register definitions may result in a large decoder for
write decoding and a large multiplexer for read decoding. These conditions may lead to critical
mux paths. Register Assistant’s pipelining feature helps you overcome critical mux paths and
avoid synthesis problems.
By default, Register Assistant generates an RTL file containing the description of registers,
register blocks, block maps, and the definition of core and optional signals. The content of the
generated output depends on the register definitions you provide in the input file and on the
configuration of RTL parameters. The default architecture of Register Assistant’s RTL
generated output file comprises a separate VHDL architecture or Verilog block for each register
block, in addition to the core signals and optional signals.
• Write enable (demux) that asserts the appropriate register enable signal
• Read mux that assigns appropriate register content to RDATA
• Data, address, and control signals for both read and write “generic” buses
As part of the core signals, the generated file contains write address decode and write enable
logic on both the register and field level. The generated file also contains read logic where the
read bus multiplexer is defined.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Tip
The default behavior of Register Assistant, when the pipelining feature is not used, is
referred to as zero-stage pipelining.
The following figure shows an abstract illustration of the two-stage pipelining concept.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
You can choose the number of pipelining stages. If you generate one pipelining stage, the RTL
generator creates one level of flip-flops and two levels of muxes. If you generate two pipelining
stages, the RTL generator creates two levels of flip-flops and two levels of muxes.
Table 5-25. Pipelining Stages and Corresponding Flip-Flop and Mux Levels
Number of Stages Maximum Number of Flip- Maximum Number of Mux
Flop Levels Levels
0 0 1
1 1 2
2 2 2
The following figure shows an illustration of an overall flow of a one-stage read and one-stage
write pipelining as an example.
The register input file should contain at least three writable/readable registers for each block
you pipeline. If you apply write pipelining to a block, it should contain at least three writable
registers. Similarly, if you apply read pipelining to a block, it should contain at least three
readable registers.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Related Topics
Pipelining Parameters
Pipelining Checks
Pipelining RTL Output
Examining the Generated RTL File
Pipelining Parameters
For Register Assistant to apply pipelining to the generated code, you have to use the
corresponding parameters in your register definition input files.
The maximum number of pipelining stages is 2. You can specify a different number of write
and read stages. For example, you can set the write stages as 1 and the read stages as 0.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
For intermediate signals, Register Assistant substitutes the %(SIGNAL_NAME) variable with
“RD” for READ and “WEN” for WRITE. In the following figure, there are several levels of
muxes, and each mux level is addressed by a group of addresses. The intermediate signal uses
%(MUX_LEVEL_GROUP) to select a specific group of decoders or multiplexers.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Related Topics
Parameters
Pipelining Overview
Pipelining Checks
Pipelining RTL Output
Pipelining Checks
The RTL generator runs certain checks when you set the pipelining feature. Register Assistant
raises a warning or error message if a check fails and stops completely for errors.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
• rtl.PIPELINE_WRITE_STAGES
• rtl.PIPELINE_READ_STAGES
If these parameters have values that are greater than 0, then Register Assistant checks that the
values of the following parameters are valid.
• rtl.PIPELINE_WRITE_MUX_SIZES
• rtl.PIPELINE_READ_MUX_SIZES
To validate parameter values, Register Assistant runs a series of checks in the following
sequence. If your input violates any of these checks, Register Assistant raises an error, the
remaining checks do not run, and generation stops.
1. If the value of the number of pipelining stages is invalid, Register Assistant raises an
error.
# Error: Block 'top' has parameter 'rtl.PIPELINE_READ_STAGES' set to
invalid value 'xyz'.
2. If the value of the number of stages parameters is 0, Register Assistant proceeds with
non-pipelined generation.
3. If the value of the number of stages parameters is greater than the allowed maximum (2),
Register Assistant raises an error.
# Error: Block 'top' has parameter 'rtl.PIPELINE_READ_STAGES' set to
unsupported value '5'. Supported values: 0 - 2.
4. If you do not specify the mux size parameters, Register Assistant raises an error.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
5. If the number of mux sizes does not match the number of mux levels, Register Assistant
raises an error.
# Error: Block 'top' has parameter 'rtl.PIPELINE_READ_STAGES' set to
invalid value '1'. Value should be 2 numbers separated by spaces.
Please make sure of the following: Each size should be greater than
1 and should be a power of 2. MUX size should be less than the number
of readable instances in any level. Multiplication product of
individual sizes should be at least the number of readable
registers.
6. If the mux sizes have any invalid value (a non-integer value), Register Assistant raises
an error.
# Error: Block 'top' has parameter 'rtl.PIPELINE_READ_STAGES' set to
invalid value 'x 3'. Value should be valid numbers separated by
spaces. Please make sure of the following: Each size should be
greater than 1 and should be a power of 2. MUX size should be less
than the number of readable instances in any level. Multiplication
product of individual sizes should be at least the number of
readable registers.
7. If any of the mux sizes is less than or equal to 1, or is not a power of 2, Register
Assistant raises an error.
# Error: Block 'top' has parameter 'rtl.PIPELINE_READ_MUX_SIZES' set
to invalid value '1 1'. Each size should be greater than 1 and
should be a power of 2. Please make sure of the following: MUX size
should be less than the number of readable instances in any level.
Multiplication product of individual sizes should be at least the
number of readable registers.
8. If the number of registers is less than or equal to the mux size of any level, Register
Assistant raises an error.
# Error: Block 'top' has parameter 'rtl.PIPELINE_READ_MUX_SIZES' set
to invalid value '8 2'. MUX size '8' is invalid. MUX sizes should be
less than the number of readable instances '7' in any level. Please
make sure of the following: Multiplication product of individual
sizes should be at least the number of readable registers.
9. If the multiplication of mux sizes is less than the number of registers, Register Assistant
raises an error.
# Error: Block 'top' has parameter 'rtl.PIPELINE_READ_MUX_SIZES' set
to invalid value '2 2'. Multiplication product of individual sizes
should be at least '7'.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
10. If mux sizes have an invalid value, that is, if a value does not pass any of checks 5 to 9,
then Register Assistant raises a note to suggest a list of valid sizes from which you can
choose. For example:
# Note: Valid value(s) of 'rtl.PIPELINE_READ_MUX_SIZES' for block
'top' are: 2 512, 4 256, 8 128, 16 64, 32 32, 64 16, 128 8, 256 4 or
512 2.
• rtl.PIPELINE_MUX_SIGNALS
• rtl.PIPELINE_DELAYED_SIGNALS
• rtl.PIPELINE_INTERMEDIATE_SIGNALS
If the parameters do not use variables, Register Assistant raises an error as shown in the
following example:
The following table shows the parameters and the mandatory variables to use in their definition.
Related Topics
Pipelining Overview
Pipelining Parameters
Pipelining RTL Output
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
This example creates two stages of write pipeline and two stages of read pipeline as indicated in
the following figure. The multiplexer sizes of the write pipeline are “2” for the first level and
“4” for the second level, and the sizes for the read pipeline are “4” for the first level and “2” for
the second level.
After running Register Assistant, the generated RTL file includes the following write pipeline.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
In addition, the generated RTL file includes the following read pipeline.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
RTL Write/Read Pipelining
Note
If you are using optional signals, they are delayed in the generated output. Register Assistant
adds the corresponding number of flip-flops in the path of the signals to ensure that the
signals are asserted in the corresponding time slot.
Related Topics
Pipelining Overview
Pipelining Parameters
Pipelining Checks
RTL Pipelining Output Example
Parameters
Control File
Running Register Assistant in Batch Mode
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
C Header Generator
C Header Generator
Register Assistant allows you to generate C Header files reflecting the register structure defined
in the input. Based on the register definitions used in the input, Register Assistant generates
header files which can be useful for software/firmware teams to develop drivers and application
code.
Through the generation of C Header files, C programmers will be able to easily access registers
by their names rather than hard-coded numeric addresses.
Generated C Header files include, for example, macro definitions for basic access rights, macro
definitions for generic read/write macros, and so forth. The following sections provide more
details on the generation of C Header files through Register Assistant.
Additionally, the C Header generator allows you to generate utility code. For further
information, refer to the section “Generating C Utility Files” on page 196.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Preparing the Control File
Note
* To view a full list of Register Assistant’s CSV columns, whether mandatory or
optional, you can refer to the CSV Columns list.
* If you are using register files in your input data, Register Assistant internally
translates them to sub-blocks (refer to “Overview on Register Data Hierarchy” on
page 14). It should be noted that any settings defined for parent blocks, such as
interface signals or parameters, will also be used for child register files.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Understanding C Header Checks
# Generate C Headers
java, c_header, reg.h, D:/projects/cheader
• The referenced C Header (c.*) parameters are among the list of supported parameters.
Refer to C Header Parameters sheet to view a full list of the supported parameters.
• Parameters have valid values. For example, this check validates that the parameter
c.DEFINE_NAMES_CASE has one of the following values: UPPER, LOWER or
AS_IS).
• Parameters are referenced by valid scopes. For example, this check validates that the
parameter c.BLOCK_BASE_ADDRESS is defined on the level of the project.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Understanding C Header Checks
• Parameters reference variables that must be referenced (if any). For example, the
parameter c.FIELD_NAMING should reference at least the variable
%(FIELD_NAME), otherwise the naming will not be unique across all fields.
• Referenced variables are among the list of supported variables. Refer to C Header
Variables sheet to view a full list of the supported parameters.
• Parameters do not reference variables that cannot be referenced (if any). For example,
the parameter c.FIELD_NAMING cannot reference the %(BLOCK_NAME) variable.
See the following error examples resulting from this check:
Instances Definitions
Checks that all instances have definitions.
Register Widths
Checks that all registers have supported widths. A supported width should match any of the
built-in or user-specified widths defined through the c.INSTANCE_VARIABLE_TYPES
parameter.
Padding Sizes
Checks that any padding between component instances has a size as multiples of any of the
built-in or user specified widths defined through the c.INSTANCE_VARIABLE_TYPES
parameter.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
Note
Note that all these checks take place in the same order as they are listed above. Also, it
should be noted that if any check fails, the other checks are not executed, and hence the
generation stops.
File Header
Register Assistant adds a header at the beginning of the generated file to provide general
information such as the name of the project, the name of the generated file, the name of the user
who generated the file, and so forth. This section specifically relies on a separate template
available on %(RA_HOME)/resources/templates/c_header_file_header.h.
Note that this section is equivalent to the following macro in Register Assistant’s default
c_header.h template:
@FILE_HEADER@
Include Files
Register Assistant deduces include files from the register definition input files as follows:
• The include file stdint.h is always added in the generated output as it is needed for the
supported built-in struct item types: uint8_t, unit16_t, uint32_t or unit64_t. Example:
#include ‘stdint.h‘
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
• Extra include files are also added in the generated output based on the following
parameters:
You can define extra include files if you are using types other than the built-in types supported
by Register Assistant using the c.EXTRA_INCLUDES parameter. In that case, you will also
need to use the c.INSTANCE_VARIABLE_TYPES in order to define the types associated to
the extra include files.
Refer to C Header Parameters sheet for more information on the above parameters.
Note that the include files section is equivalent to the following macro in Register Assistant’s
default c_header.h template:
@GENERATED_INCLUDES@
The generated access right macros are “__RO”, “__WO” or “__RW”. Any register access right
is resolved to one of these three macros.
For example, if there are a number of registers in the input files having the software access
modes RC and RW1C, the following defines will be generated:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
The following table shows the macros generated for different software access modes:
Table 5-32. Macros Generated for Software Access Modes
Software Access Modes Macro Name Macro Value
Read-Write access modes. __RW volatile
Note that the access right macro definitions section is equivalent to the following macro in
Register Assistant’s default c_header.h template:
@GENERATED_SW_ACCESS_RIGHT_DEFINES@
Likewise, if one or more registers contain fields with write software access modes such as RW,
WO, WOQ and so on, then a macro for write method is defined.
You have the ability to control the name of the macros through the following parameters:
Table 5-33. Parameters for Read/Write Macro Names
c.READ_MACRO_NAME Indicates the name of the read macro. The default is
%(PROJECT_NAME)_READ.
c.WRITE_MACRO_NAME Indicates the name of the write macro. The default is
the %(PROJECT_NAME)_WRITE.
Refer to C Header Parameters sheet for more information on the above parameters.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
The following example shows macro definitions for read and write macros in the generated
code:
Note that the read/write macro definitions section is equivalent to the following macro in
Register Assistant’s default c_header.h template:
@GENERATED_READ_WRITE_DEFINES@
You have the ability to specify the struct names as well as the names of the pointers to each
struct by defining the following parameters in the input files:
Table 5-34. Parameters for Block Struct Names and Pointer Names
c.BLOCK_STRUCT_NAME Indicates the name of the block struct to define in
the generated output. The default is
%(BLOCK_NAME)_s.
c.BLOCK_STRUCT_POINTER_NAME Indicates the name of the struct pointer name to
define in the generated output. The default is
%(BLOCK_NAME)_ptr.
Refer to C Header Parameters sheet for more information on the above parameters.
The following example shows how block structs and their pointers are defined in the generated
output:
Note how the block size is defined in the comment preceding the struct definition.
Component Instances
Within the block struct definition, a data member is defined for each component instance
(whether register, memory, sub-block and so on). The data members are ordered by the position
of their component instances inside the block.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
For each register and memory instance, Register Assistant creates a data member having the
type specified through the parameter c.INSTANCE_VARIABLE_TYPE.
Note that if the parameter is not specified in the input files, or if it does not have a specified or a
suitable value, Register Assistant will use one of the following built-in types: uint8_t, unit16_t,
uint32_t, unit64_t.
Padding
A padding data member is defined for each part of the block address space with no assigned
instances.
Note that if the padding size is not a multiple of any of the user-specified types (if any), then the
built-in types are used.
Example
This example illustrates the block struct definitions along with the component instances and
padding in the generated output:
Note that the block struct definitions section in the generated file is equivalent to the following
macro in Register Assistant’s default c_header.h template:
@GENERATED_BLOCKS_STRUCTS@
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
The following example shows how top blocks are defined in the generated output:
Note that the top block macro definitions section is equivalent to the following macro in
Register Assistant’s default c_header.h template:
@GENERATED_TOP_BLOCK_BASE_ADDRESS@
@GENERATED_TOP_BLOCK_DECLARATION@
You can specify a naming convention for field macro names using the parameter
c.FIELD_NAMING. The default is %(REGISTER_NAME)_%(FIELD_NAME). Refer to C
Header Parameters sheet for information on the parameters that can be used for the generation
of C Header files, and also refer to C Header Variables sheet for information on the C Header
variables that can be used in the definition of C Header parameters.
• A macro is defined for the field’s mask value. The mask value is calculated as follows:
2^(offset + width) – 2^(offset).
Register Assistant uses the following format in code generation:
#define <name specified by c.FIELD_NAMING parameter>__<postfix
specified by c.FIELD_MASK_POSTFIX parameter> <mask in hex format>
The field’s mask macro name postfix can be defined through the variable
c.FIELD_MASK_POSTFIX.
• A macro is defined for the field’s offset value.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
The field’s offset macro name postfix can be defined through the variable
c.FIELD_OFFSET_POSTFIX.
• A macro is defined for a “get” method. It will be defined for all fields except reserved
fields and write-only fields.
Register Assistant uses the following format in code generation:
#define <name specified by c.FIELD_NAMING parameter>__<postfix
specified by c.FIELD_GET_POSTFIX parameter>(field) \
<read macro>(field, <field mask macro>, <field offset macro>)
The field’s get method macro name postfix can be defined through the variable
c.FIELD_GET_POSTFIX.
• A macro is defined for a “set” method. It will be defined for all fields except reserved
fields and read-only fields.
Register Assistant uses the following format in code generation:
#define <name specified by c.FIELD_NAMING parameter>__<postfix
specified by c.FIELD_SET_POSTFIX parameter>(field, data) \
<write macro>(field, <field mask macro>, <field offset macro>, data)
The field’s set method macro name postfix can be defined through the variable
c.FIELD_SET_POSTFIX.
You can refer to C Header Parameters to view the parameters that can be used with the
generation of C Header files and their default values. You can also see the C Header Variables
that can be used in the definition of parameter values. For a general overview on parameters, see
“Parameters” on page 213.
Tip
: The case of any macro names used in the generated output can be controlled through the
parameter c.DEFINE_NAMES_CASE. The values of this parameter can be: UPPER (which
is the default), LOWER, or AS_IS.
Note that the field macro definitions section is equivalent to the following macro in Register
Assistant’s default c_header.h template:
@GENERATED_FIELDS_DEFINES@
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
Example
The following example shows a full C Header file generated by Register Assistant.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
/*----------------------------------------------------------------------
* THIS IS AUTOMATICALLY GENERATED CODE
* Generated by Mentor Graphics' Register Assistant V4.6 (Build 4)
*----------------------------------------------------------------------
* Project : output
* File : sw.h
*----------------------------------------------------------------------
* Created by : user
* Creation Date : 14/09/14 09:50
*----------------------------------------------------------------------
* Title : output
*
* Description :
*
*----------------------------------------------------------------------
*/
#ifndef _SW_H
#define _SW_H
#include <stdint.h>
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
{
/* Padding */
uint32_t pad0[1024]; /* 0xFFF:0x0 */
/* Block1 instance 1 */
sw_sub_block_s sw1; /* 0x1053:0x1000 */
/* Padding */
uint32_t pad1[1003]; /* 0x1FFF:0x1054 */
/* Block1 instance 2 */
sw_sub_block_s sw2; /* 0x2053:0x2000 */
/* Padding */
uint32_t pad2[1003]; /* 0x2FFF:0x2054 */
/* Counter instance 1 */
__RW uint32_t vreg1; /* 0x3003:0x3000 */
/* Counter instance 2 */
__RW uint32_t vreg2; /* 0x3007:0x3004 */
/* Counter instance 3 */
__RW uint32_t vreg3; /* 0x300B:0x3008 */
/* Padding */
uint32_t pad3[1021]; /* 0x3FFF:0x300C */
/* Memory instance */
__RW uint32_t mem1[1024]; /* 0x4FFF:0x4000 */
} __RW sw_top_block_s, *sw_top_block_ptr;
/*--------------------------------------------------------------------
* Register: stopwatch_csr
* Control Status Register
* (reset from fields is 0x0000007C)
* SW Access : read-write
* HW Access : read-write
*
* Fields:
* 0 lower_limit_reached (SW:read-only, HW:read-write)
* 1 upper_limit_reached (SW:read-only, HW:read-write)
* 2 updown (SW:read-write, HW:read-write)
* 6:3 stride (SW:read-write, HW:read-write)
* 31:7 padding (SW:read-write, HW:read-write) (RESERVED)
*/
/*--------------------------------------------------------------------
* Field: lower_limit_reached
* Width: 1, Offset: 0
* SW Access: read-only, HW Access: read-write
*--------------------------------------------------------------------
* Indicates that the lower limit has been reached
*/
#define STOPWATCH_CSR__LOWER_LIMIT_REACHED__MASK 0x00000001
#define STOPWATCH_CSR__LOWER_LIMIT_REACHED__OFFSET 0
#define STOPWATCH_CSR__LOWER_LIMIT_REACHED__GET(reg)\
OUTPUT_READ32(reg, STOPWATCH_CSR__LOWER_LIMIT_REACHED__MASK,
STOPWATCH_CSR__LOWER_LIMIT_REACHED__OFFSET)
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
/*--------------------------------------------------------------------
* Field: upper_limit_reached
* Width: 1, Offset: 1
* SW Access: read-only, HW Access: read-write
*--------------------------------------------------------------------
* Indicates that the upper limit has been reached
*/
#define STOPWATCH_CSR__UPPER_LIMIT_REACHED__MASK 0x00000002
#define STOPWATCH_CSR__UPPER_LIMIT_REACHED__OFFSET 1
#define STOPWATCH_CSR__UPPER_LIMIT_REACHED__GET(reg)\
OUTPUT_READ32(reg, STOPWATCH_CSR__UPPER_LIMIT_REACHED__MASK,
STOPWATCH_CSR__UPPER_LIMIT_REACHED__OFFSET)
/*--------------------------------------------------------------------
* Field: updown
* Width: 1, Offset: 2
* SW Access: read-write, HW Access: read-write
*--------------------------------------------------------------------
* Indicates whether counting up or down
*/
#define STOPWATCH_CSR__UPDOWN__MASK 0x00000004
#define STOPWATCH_CSR__UPDOWN__OFFSET 2
#define STOPWATCH_CSR__UPDOWN__GET(reg)\
OUTPUT_READ32(reg, STOPWATCH_CSR__UPDOWN__MASK,
STOPWATCH_CSR__UPDOWN__OFFSET)
#define STOPWATCH_CSR__UPDOWN__SET(reg, data)\
OUTPUT_WRITE32(reg, STOPWATCH_CSR__UPDOWN__MASK,
STOPWATCH_CSR__UPDOWN__OFFSET, data)
/*--------------------------------------------------------------------
* Field: stride
* Width: 4, Offset: 3
* SW Access: read-write, HW Access: read-write
*--------------------------------------------------------------------
* Stride length
*/
#define STOPWATCH_CSR__STRIDE__MASK 0x00000078
#define STOPWATCH_CSR__STRIDE__OFFSET 3
#define STOPWATCH_CSR__STRIDE__GET(reg)\
OUTPUT_READ32(reg, STOPWATCH_CSR__STRIDE__MASK,
STOPWATCH_CSR__STRIDE__OFFSET)
#define STOPWATCH_CSR__STRIDE__SET(reg, data)\
OUTPUT_WRITE32(reg, STOPWATCH_CSR__STRIDE__MASK,
STOPWATCH_CSR__STRIDE__OFFSET, data)
/*--------------------------------------------------------------------
* Field: padding (RESERVED)
* Width: 25, Offset: 7
* SW Access: read-write, HW Access: read-write
*--------------------------------------------------------------------
* Reserved
*/
#define STOPWATCH_CSR__PADDING__MASK 0xFFFFFF80
#define STOPWATCH_CSR__PADDING__OFFSET 7
#endif
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
In this example, a generated C Header file titled “c_header_main.h” is included at the beginning
of the code.
• The write macro of a field takes the register of the field and the value to be written as
arguments. It writes the passed value to this specific field in the register.
• The read macro of a field takes the register of the field, and returns the value of this
specific field from the register.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Examining the Generated C Header File
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include "c_header_main.h"
int main()
{
/* Declarations */
int value;
/* Hello */
printf("Testing register/field read/write operations...\n");
/* Allocation */
top_block = malloc(sizeof(top_srt));
/****************************/
/* Test REGISTER read/write */
/****************************/
/* Write to register */
value = 220;
top_block->imy_counter = value;
printf("Value: %d written to register 'top_block->imy_counter'\n",
top_block->imy_counter);
/* Read from register */
value = top_block->imy_counter;
printf("Register 'top_block->imy_counter' has a value: %d\n\n", value);
/****************************/
/* Test FIELD read/write */
/****************************/
/* Write to field */
top_block->imy_register = 0; /* reset the whole register (could be
skipped) */
value = 10; /* CAUTION: value should not exceed 4 bits (the field
width) */
top_block->imy_register = my_register__fld_2__my_set(top_block-
>imy_register, value)
printf("Value: %d written to field 'fld_2' in register 'top_block-
>imy_register'\n", value);
/* Read from field */
value = my_register__fld_2__my_get(top_block->imy_register);
printf("Field 'fld_2' in register 'top_block->imy_register' has a
value: %d\n", value);
/* Free */
free(top_block);
return 0;
}
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generating C Utility Files
Procedure
1. Prepare your register definition files and configure the C Header generator through
defining parameters. For more information, refer to “Specifying the Input” on page 179.
Make sure you define the parameters specific to the generation of utility files:
For more information on the list of parameters that can be used with C Header
generation and their usages, refer to C Header Parameters. You can also see C Header
Variables, to view a list of the variables supported for use within C Header parameters.
2. Prepare your control file. For more information, refer to “Preparing the Control File” on
page 180.
3. Run Register Assistant. For more information, refer to “Command Line Switches” on
page 219.
Results
On running Register Assistant, a series of checks are run on the provided input and if no errors
are raised, the output is generated successfully. Refer to “Understanding C Header Checks” on
page 181, for more information on the checks that apply to the C Header generator.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generating C Utility Files
As mentioned earlier, in addition to the main C header .h file, two utility files will be generated
as follows:
• <C Header File Name>_utils.h
By default, Register Assistant generates this file based on the template found on the path
%(RA_HOME)/resources/templates/c_utils.h. You have the ability to change the
template through the parameter c.UTILS_H_TEMPLATE_PATH.
The default template constitutes of macros which are substituted in the generated output
with the following sections based on the register definitions provided. The main sections
in the file include:
o File Header — Register Assistant adds a header at the beginning of the file to
provide general information such as the name of the project, the name of the
generated file, and so forth. This section specifically relies on a separate template
available on %(RA_HOME)/resources/templates/c_header_file_header.h.
Note that this section is equivalent to the following macro in Register Assistant’s
default c_utils.h template:
@FILE_HEADER@
o Include Files — This section contains includes for the original C Header .h file.
Note that this section is equivalent to the following macro in Register Assistant’s
default c_utils.h template:
@GENERATED_INCLUDES@
o Initializations — This section defines macros for reset values for all the registers
and memories in the input files.
This section also contains function headers for the reset initialization functions of the
top block and sub-blocks.
Note that this section is equivalent to the following macro in Register Assistant’s
default c_utils.h template:
@GENERATED_RESET_VALUES@
@GENERATED_INIT_FUNCTIONS_PROTOTYPES@
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generating C Utility Files
The default template constitutes of macros which are substituted in the generated output
with the following sections based on the register definitions provide. The main sections
in the file include:
o File Header — Register Assistant adds a header at the beginning of the file to
provide general information such as the name of the project, the name of the
generated file, and so forth. This section specifically relies on a separate template
available on %(RA_HOME)/resources/templates/c_header_file_header.h.
Note that this section is equivalent to the following macro in Register Assistant’s
default c_utils.c template:
@FILE_HEADER@
o Include Files — This section contains includes for the original C Header .h file in
addition to the utility file <C Header File Name>_utils.h.
Note that this section is equivalent to the following macro in Register Assistant’s
default c_utils.c template:
@GENERATED_INCLUDES@
Examples
The following examples show generated <C Header File Name>_utils.h and <C Header File
Name>_utils.c utility files.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generating C Utility Files
/*----------------------------------------------------------------------
* THIS IS AUTOMATICALLY GENERATED CODE
* Generated by Mentor Graphics' Register Assistant V4.6 (Build 4)
*----------------------------------------------------------------------
* Project : output
* File : sw_utils.h
*----------------------------------------------------------------------
* Created by : user
* Creation Date : 14/09/14 09:50
*----------------------------------------------------------------------
* Title : output
*
* Description : Register Utilities Header
*
*----------------------------------------------------------------------
*/
#ifndef _SW_UTILS_H
#define _SW_UTILS_H
#include "sw.h"
#endif
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Generating C Utility Files
/*----------------------------------------------------------------------
* THIS IS AUTOMATICALLY GENERATED CODE
* Generated by Mentor Graphics' Register Assistant V4.6 (Build 4)
*----------------------------------------------------------------------
* Project : output
* File : sw_utils.c
*----------------------------------------------------------------------
* Created by : user
* Creation Date : 14/09/14 09:50
*----------------------------------------------------------------------
* Title : output
*
* Description : Register Utilities
*
*----------------------------------------------------------------------
*/
#include "sw.h"
#include "sw_utils.h"
Related Topics
C Header Generator
Parameters
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Word Addressable Output
In the default byte addressing mode, Register Assistant assumes that all addresses are 1 byte (8
bits) apart. Hence, for a 32-bit bus, each entry in the address maps is 4 bytes apart, which means
that address values increment by 4 to access the start of the next register. For example, the first
register might be at address 0x0, the second at 0x4, the third at 0x8 and so on.
In the word addressing mode, address values simply increment by 1 word each time given that
the word size is defined as multiples of 8-bit bytes. Using the 32-bit bus example, the first
register might be at address 0x0, the second at 0x1, the third at 0x2 and so on.
As shown in the table, for byte addressing, the first word starts at address 0x0, the second word
at address 0x4, whereas for word addressing (in this 32-bit example) all 4 bytes of the first word
are at address 0x0, all 4 bytes for the second word at 0x1 and so on.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Applying Word Addressing in Register Assistant
2. Depending on the input format you are using, set the word addressing feature as follows
on the block map level:
a. For CSV input files, make sure you add the following columns:
BlockMap Word Bytes Decimal Number Specify the number of bytes in a word.
The default value is “4”.
Note
If you are generating UVM output, then you have the ability to specify the
endianness using the BlockMap Endian column in case of CSV input or using the
setEndian() API in case of JavaScript input. For details, refer to the CSV Columns table
or to the Register Assistant’s APIs on the path <installation_folder>\registerassistant\
api\index.html.
3. Prepare your control file. For more information, refer to “Preparing the Control File” on
page 180.
4. Run Register Assistant. For more information, refer to “Command Line Switches” on
page 219.
Results
Having set the word addressing mode, the following aspects will be affected on running
Register Assistant:
• The calculation of block sizes.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Applying Word Addressing in Register Assistant
The following are excerpts of a UVM output example generated for the above inputs. To view
the full example, refer to “UVM Word Addressable Output Example” on page 257.
• In the following UVM code snippet, note the create_map() method which is affected by
the word addressability settings in the CSV input files. This method allows the creation
of an address map in a block. The arguments of this method are:
o name — The name of the address map.
o base_addr — The base address for the address map.
o n_bytes — The byte-width of the bus on which the map is used. This is related to the
UVM parameter uvmgen.N_BYTES as will be explained later.
o endian — The endianness setting. This is based on the value of the BlockMap
Endian column as will be explained later.
o byte_addressing — The addressing mode. The value “0” indicates word addressing,
and “1” indicates byte addressing.
Note the usage of the endianness setting, which is already defined in the BlockMap
Endian column in the CSV input, as an argument in the create_map() method in the
following code snippet.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Applying Word Addressing in Register Assistant
// Function: build
//
virtual function void build();
if(has_coverage(UVM_CVR_ADDR_MAP)) begin
SUB_MAP1_cg =
sw_sub_block_SUB_MAP1_coverage::type_id::create("SUB_MAP1_cg");
SUB_MAP1_cg.ra_cov.set_inst_name(this.get_full_name());
void'(set_coverage(UVM_CVR_ADDR_MAP));
end
stopwatch_value_reg =
stopwatch_value::type_id::create("stopwatch_value_reg");
stopwatch_value_reg.configure(this);
stopwatch_value_reg.build();
stopwatch_reset_value_reg =
stopwatch_reset_value::type_id::create("stopwatch_reset_value_reg")
;
stopwatch_reset_value_reg.configure(this);
stopwatch_reset_value_reg.build();
stopwatch_upper_limit_reg =
stopwatch_upper_limit::type_id::create("stopwatch_upper_limit_reg")
;
stopwatch_upper_limit_reg.configure(this);
stopwatch_upper_limit_reg.build();
stopwatch_lower_limit_reg =
stopwatch_lower_limit::type_id::create("stopwatch_lower_limit_reg")
;
stopwatch_lower_limit_reg.configure(this);
stopwatch_lower_limit_reg.build();
stopwatch_csr_reg =
stopwatch_csr::type_id::create("stopwatch_csr_reg");
stopwatch_csr_reg.configure(this);
stopwatch_csr_reg.build();
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Applying Word Addressing in Register Assistant
end
It is also important to note that the parameter uvmgen.N_BYTES can be used in the
CSV input files to define the word size of the bus to which the address map is
associated. This is only applicable when generating UVM output. The value of this
parameter, which should be specified in terms of bytes, is used as an argument by the
create_map() method. As shown in the above example, the size is “4” bytes.
If this parameter is not specified or if its value is invalid (not a positive integer), then
Register Assistant calculates the value automatically and a warning is raised as shown in
the following example:
Warning: Map 'SW_MAP2' has parameter 'uvmgen.N_BYTES' set to invalid
value 'x'. Only positive integers are allowed. Using automatically
calculated value '4' instead.
Information on this parameter can be found in the OVM/UVM Parameters table which
contains a full list of the supported UVM parameters.
• In the above UVM code snippet, the word addressing settings also impacts the foreach
loop in the calculation of the address increments in the second parameter.
• Another item in the generated code affected by the word addressing mode is
covergroups. The following code snippet shows Register Assistant’s automatic
calculation of instance array addresses in coverpoints.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Register Assistant Output
Applying Word Addressing in Register Assistant
/* BLOCKS */
//--------------------------------------------------------------
// Class: sw_sub_block_SUB_MAP1_coverage
//
// Coverage for the 'SUB_MAP1' in 'sw_sub_block'
//--------------------------------------------------------------
option.per_instance = 1;
option.name = name;
endgroup: ra_cov
endclass: sw_sub_block_SUB_MAP1_coverage
Related Topics
Word Addressable Output
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Chapter 6
Customization
Custom Properties
Register Assistant’s internal data model consists of a set of objects (for example, register, field,
field value, memories, and so on). The data model provides a set of built-in properties for these
objects, each property holds a certain piece of information related to the object.
Register Assistant enables you to define custom data for objects. That is to say, you can add
custom properties to objects in the data model. For example, if you have certain proprietary
information related to registers which is not available in the data model, Register Assistant
enables you to add a property to the register object to reflect this information. By that, this
information will be accepted by Register Assistant and will not cause errors during the import
process.
You will be able to view the added data in the generated HTML output for documentation
purposes.
Also, you can use this data when creating your own custom generators (other than Register
Assistant’s default generators which produce OVM and HTML output for example) and when
creating your own custom checks script (all using the API commands provided by Register
Assistant).
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Defining Properties for Register Assistant Objects
Or:
tcl, file_location/file_name.tcl
The script should be referenced before the import section. Refer to “Control File” on
page 23 for further information on control files.
3. Set the value of the added property.
It is important to note that Register Assistant can automatically extract custom data
when importing from CSV files or from IP-XACT XML format. Hence, you can directly
add a column in your CSV file to define the value of the added object’s property. If you
are using IP-XACT XML format, you can add Vendor Extensions (or attributes). (See
Handling Custom Properties.)
Otherwise, if you are importing from any other format, you will need to use the “set”
APIs in the import script itself in order to assign property values to objects.
RAObject.setCustomData(String ID, Object value);
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Custom Properties Definition Script
/* Define some custom data that will be used later in the import */
importPackage(com.mentor.regassist.dm);
RACustomDataFactory.defineCustomData(applyTo,
RACustomDataFactory.RACustomDataType.LIST, "abc", "", vals);
RACustomDataFactory.defineCustomData(applyTo,
RACustomDataFactory.RACustomDataType.BOOLEAN, "xyz", "Bool Type", null);
return 0;
}
Example
This example adds the property “cust_prop”, of type “list”, to the object “register instance”.
importPackage(com.mentor.regassist.dm);
RACustomDataFactory.defineCustomData(applyToRegI,
RACustomDataFactory.RACustomDataType.LIST, "cust_prop",
"Custom_Property", vals);
return 0;
}
The following step is to reference the above script in the control file (before the import section).
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Custom Properties Definition Script
Also, if the import takes place from CSV files, then a column should be added in the CSV files
with the title “cust_prop” and the value should be set for each register instance as either
“Value1” or “Value2” or null. If the import takes place from IP-XACT XML files, you can add
Vendor Extensions (or attributes).
On running Register Assistant, the property you added with the ID “Custom_Property” will be
displayed in the HTML output as shown in the following figure:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Using Custom Properties
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Handling Custom Properties
CSV Import
The CSV import utility automatically extracts custom data from CSV spreadsheets. The CSV
import utility looks for columns that match the string ID of the added property (added for the
register object for example), and will automatically set the value of that property for the object.
Custom data can be added to the following objects:
• Registers: Can include custom data for Registers, Fields, and Field Values.
• Memory: Can include custom data for Memories and Memory Instances.
• Sub-blocks/Register Files: Can include custom data for Register Instances, and Sub-
block Instances/Register File Instances.
• Block/Memory Map: Can include custom data for Block Instances/Memory Map
Instances, Register Instances, and Sub-block Instances/Register File Instances.
IP-XACT Import
The IP-XACT import utility automatically extracts custom data from IP-XACT files. The IP-
XACT import utility looks for vendor extensions that match the string ID of the property
defined for the current object being imported, and will automatically set the value of that
property for the object.
Based on IP-XACT schema for IEEE Std 1685-2009, only Registers and Fields have Vendor
Extensions. Therefore, custom data import will work only for registers and fields.
For example:
<spirit:register>
<spirit:name>stopwatch_value</spirit:name>
...
<spirit:vendorExtensions>
<idList>2</idList>
</spirit:vendorExtensions>
</spirit:register>
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Parameters
The property “idList” must be defined before using it in IP-XACT import, for example:
Parameters
Register Assistant provides a set of predefined parameters you can use with generators such as
the UVM and RTL generators. These parameters enable you to pass to Register Assistant’s
generators extra information that affect the output.
For example, when generating RTL output, you can use certain parameters to set the language
of the generated output to be VHDL. Likewise, when generating UVM output, you can use
certain parameters to specify your own user-defined packages and force certain registers to
extend from classes in these packages (such registers are referred to as quirky registers).
Register Assistant supports a list of fixed parameters each performing a certain function. Refer
to RTL Parameters, OVM/UVM Parameters and C Header Parameters tables to view the full
list of supported parameters, the possible values of each parameter and the default values if the
parameter is not explicitly set, the scope to which the parameter applies, and so on. Each
parameter can be applied to objects within a certain scope such as registers, blocks and projects.
To use parameters, you have to set them in the register input files, whether CSV or JavaScript
input files.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Using Parameters
Using Parameters
Register Assistant provides several methods to use parameters.
Standard Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Alias-Based Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Standard Method
You can use the parameters feature by adding the required parameters in your input files,
whether CSV files or JavaScript.
To use parameters in CSV files, you have to add the following columns:
Adding the above columns for the parameter “rtl.LANGUAGE” to the top block CSV file
indicates that you want to change the language of the generated RTL code from Verilog (which
is the default) to VHDL.
Each parameter has a default value which is automatically used by Register Assistant in
generation. To change the default value, you have to explicitly set the parameter. As shown in
the above example, the default language for RTL generation is Verilog; to generate VHDL
output, the corresponding parameter should be set accordingly.
You can refer to RTL Parameters table to view a list of the supported parameters in terms of the
names (such as rtl.LANGUAGE in the above example), the possible values (such as VHDL_93
and VLOG_2005), the default values, and so on.
Following the above example, when using JavaScript as the input source, you can set the
parameter using the following API:
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Standard Method
Generally, when using JavaScript as the input source, you can use the following format to add
parameters:
Below is another example showing the use of parameters to define quirky registers. The quirky
registers feature enables you to force certain registers to extend from user-defined packages
rather than built-in packages when generating UVM output. The following columns are added
in the CSV files:
Table 6-3. Parameters — Standard Method Example 2
Project Parameter Name Project Parameter Project Parameter
Value Description
uvmgen.EXTRA_IMPORTS mypkg::* pkg2::* Extra imports
The example above sets the parameter “uvmgen.EXTRA_IMPORTS” which signifies that you
will define your own imports in the generated UVM register package as follows:
// Extra imports
import mypkg::*;
import pkg2::*;
In addition to the above columns, you need to add the following columns and place values on
the same line of the register(s) that should extend from alternative parents:
Table 6-4. Parameters — Standard Method Example 2 (Continued)
Register Parameter Name Register Parameter Register Parameter
Value Description
uvmgen.ALT_PARENT my_custom_reg Alternative parent for
this register.
In the above example, the parameter “uvmgen.ALT_PARENT” is set and given a certain value
which is the actual name of the alternative parent. For example, if the above values are placed
on the same line of “Register_X”, then in the generated UVM output, this register will extend
from the class my_custom_reg instead of extending from the built-in class uvm_reg.
You can also use parameters to define quirky registers when using JavaScript as your input
source. The same imports in the above example are set through the following API:
project.addParameter(UVMGenerator.PARAM_EXTRA_IMPORTS, "mypkg::*
pkg2::*", "Extra imports");
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Alias-Based Method
Likewise, the following API signifies that “Register_X” will extend from an alternative parent
called my_custom_reg:
Register_X.addParameter(UVMGenerator.PARAM_ALT_PARENT, "my_custom_reg",
"Alternative parent for this register");
It should be noted that quirky registers are only applicable when generating UVM output. Refer
to “UVM Output” on page 71 for more information on quirky registers.
Note
* The columns <Object> Parameter Name, <Object> Parameter Value and <Object>
Parameter Description are already mapped in the example csv.js file shipped with Register
Assistant. Refer to the CSV Columns list to view the column names mapped in the csv.js file.
* The parameters common among a number of blocks can be defined only once on the project
level. That is to say, if you have a set of parameters with the same set of values, you can define
them only once on the project level rather than defining them on the level of each block
separately.
* Generally, you can add parameters in the CSV files containing the register definitions or the
block definitions. The same also applies to project parameters, but it should be noted that if you
are adding project parameters in a separate CSV file, you will need to add a dummy “Block
Name” column in that file.
Alias-Based Method
Some parameters already have predefined aliases. You can use these aliases to set parameters
when importing register definitions using CSV as the input source.
For example, to set the language of the generated RTL code to be VHDL instead of Verilog, this
can be done through the alias “Block Language”. That is, instead of adding columns for the
parameter name “rtl.LANGUAGE” and adding another column for the value such as
“VHDL_93” as explained in the Standard Method section, you can add a single column in the
top block file with the title “Block Language” and directly give it the value “VHDL_93” as
shown in the following example.
Table 6-5. Parameters — Alias-Based Method Example
Block Name Block Language
Block_XYZ VHDL_93
You have to make sure that the used alias is mapped in the csv.js file. If a parameter does not
have a predefined alias, you can give it any alias and map this alias in the csv.js file.
You can refer to RTL Parameters to view a table containing a list of the supported RTL
parameters in terms of the names (such as rtl.LANGUAGE), the possible values (such as
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Alias-Based Method
VHDL_93 and VLOG_2005), the predefined aliases (that is, the CSV column title such as
Block Language) if available.
Related Topics
Supporting Simple “Quirky” Registers
RTL Alternative Resets
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Customization
Alias-Based Method
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Appendix A
Command Line Switches
This appendix provides command line switches to run the Register Assistant.
Running Register Assistant in Batch Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
2. Use the command switches listed in the following table when invoking Register
Assistant.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Command Line Switches
Running Register Assistant in Batch Mode
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Appendix B
Examples
This appendix contains miscellaneous examples for different Register Assistant input and
output files.
JavaScript/Tcl Import File Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
UVM Output Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
OVM Output Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
RTL Pipelining Output Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
UVM Word Addressable Output Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
The examples also shows fields using reset values from the overall register reset values rather
than field-specific reset values.
For more information using scripts, refer to “Importing Data from Scripts” on page 45.
Example 1 — JavaScript
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
JavaScript/Tcl Import File Example
importPackage(com.mentor.regassist.dm);
importPackage(com.mentor.regassist.suppliedgenerators);
project.setName("sw_reg");
project.setDescription("Stopwatch UVM Project");
project.addParameter(UVMGenerator.PARAM_EXTRA_IMPORTS, "my_pkg::*", "");
// Field: F (auto)
var stopwatch_value_F = stopwatch_value.addField("F");
stopwatch_value_F.setBitWidth(32);
stopwatch_value_F.setBitOffset(0);
stopwatch_value_F.setAccess(RAAccessType.READ_ONLY);
stopwatch_value_F.setResetValue("0x0");
// Field: F (auto)
var stopwatch_counter_F = stopwatch_counter.addField("F");
stopwatch_counter_F.setBitWidth(32);
stopwatch_counter_F.setBitOffset(0);
stopwatch_counter_F.setAccess(RAAccessType.READ_WRITE);
stopwatch_counter_F.setResetValue("0x0");
// Field: F (auto)
var stopwatch_reset_value_F = stopwatch_reset_value.addField("F");
stopwatch_reset_value_F.setBitWidth(32);
stopwatch_reset_value_F.setBitOffset(0);
stopwatch_reset_value_F.setAccess(RAAccessType.READ_WRITE);
stopwatch_reset_value_F.setResetValue("0x0");
// Field: F (auto)
var stopwatch_upper_limit_F = stopwatch_upper_limit.addField("F");
stopwatch_upper_limit_F.setBitWidth(32);
stopwatch_upper_limit_F.setBitOffset(0);
stopwatch_upper_limit_F.setAccess(RAAccessType.READ_WRITE);
stopwatch_upper_limit_F.setResetValue("0x0");
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
JavaScript/Tcl Import File Example
// Field: F (auto)
var stopwatch_lower_limit_F = stopwatch_lower_limit.addField("F");
stopwatch_lower_limit_F.setBitWidth(32);
stopwatch_lower_limit_F.setBitOffset(0);
stopwatch_lower_limit_F.setAccess(RAAccessType.READ_WRITE);
stopwatch_lower_limit_F.setResetValue("0x0");
// Field: F (auto)
var stopwatch_memory_F = stopwatch_memory.addField("F");
stopwatch_memory_F.setBitWidth(32);
stopwatch_memory_F.setBitOffset(0);
stopwatch_memory_F.setAccess(RAAccessType.READ_WRITE);
stopwatch_memory_F.setResetValue("0x0");
// Field: Padding
var padding = stopwatch_csr.addField("padding");
padding.setDescription("Reserved");
padding.setBitWidth(25);
padding.setBitOffset(7);
padding.setAccess(RAAccessType.READ_WRITE);
padding.setResetValue("0x0");
padding.setCover(false);
padding.setReserved(true);
// Field: Stride
var stride = stopwatch_csr.addField("stride");
stride.setDescription("Stride length");
stride.setBitWidth(4);
stride.setBitOffset(3);
stride.setAccess(RAAccessType.READ_WRITE);
stride.setResetValue("0x0");
stride.setConstraints("constraint my_constraint {x > 5;}");
// Field: Updown
var updown = stopwatch_csr.addField("updown");
updown.setDescription("Indicates whether counting up or down");
updown.setBitWidth(1);
updown.setBitOffset(2);
updown.setAccess(RAAccessType.READ_WRITE);
updown.setResetValue("0x0");
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
JavaScript/Tcl Import File Example
// Memory: My Mem
var my_mem = project.addMemory("my_mem");
my_mem.setDescription("Memory");
my_mem.setRange("0x400");
my_mem.setWidth(32);
my_mem.setAccess(RAAccessType.READ_WRITE);
// Register: My Reg
var my_reg = project.addRegister("my_reg");
my_reg.setDescription("Custom register");
my_reg.addParameter(UVMGenerator.PARAM_ALT_PARENT, "my_reg_type", "");
my_reg.setSize(32);
// Field: F
var my_reg_F = my_reg.addField("F");
my_reg_F.setBitWidth(32);
my_reg_F.setBitOffset(0);
my_reg_F.setAccess(RAAccessType.READ_WRITE);
my_reg_F.setResetValue("0x0");
var stopwatch_value_reg =
sw_sub_block.addRegisterInstance("stopwatch_value",
"stopwatch_value_reg");
stopwatch_value_reg.setDescription("Value instance");
var stopwatch_reset_value_reg =
sw_sub_block.addRegisterInstance("stopwatch_reset_value",
"stopwatch_reset_value_reg");
stopwatch_reset_value_reg.setDescription("Reset Value instance");
var stopwatch_upper_limit_reg =
sw_sub_block.addRegisterInstance("stopwatch_upper_limit",
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
JavaScript/Tcl Import File Example
"stopwatch_upper_limit_reg");
stopwatch_upper_limit_reg.setDescription("Upper Limit instance");
stopwatch_lower_limit_reg =
sw_sub_block.addRegisterInstance("stopwatch_lower_limit",
"stopwatch_lower_limit_reg");
stopwatch_lower_limit_reg.setDescription("Lower Limit instance");
var stopwatch_memory_reg =
sw_sub_block.addRegisterInstance("stopwatch_memory",
"stopwatch_memory_reg");
stopwatch_memory_reg.setDescription("MEM instances");
stopwatch_memory_reg.setDimension(8);
SW_MAP.addAddress("stopwatch_value_reg", "0x04",
RAAccessType.READ_WRITE);
SW_MAP.addAddress("stopwatch_reset_value_reg", "0x08",
RAAccessType.READ_WRITE);
SW_MAP.addAddress("stopwatch_upper_limit_reg", "0x0C",
RAAccessType.READ_WRITE);
SW_MAP.addAddress("stopwatch_lower_limit_reg", "0x10",
RAAccessType.READ_WRITE);
SW_MAP.addAddress("stopwatch_memory_reg", "0x34",
RAAccessType.READ_WRITE);
project.setTopBlock(sw_top_block);
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
JavaScript/Tcl Import File Example
return 0;
}
Example 2 — Tcl
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
JavaScript/Tcl Import File Example
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
JavaScript/Tcl Import File Example
# Field: Padding
::raAddRegisterField "stopwatch_csr" "padding" "Reserved"
::raSetFieldBitOffset "stopwatch_csr" "padding" 7
::raSetFieldBitWidth "stopwatch_csr" "padding" 25
::raSetFieldAccess "stopwatch_csr" "padding" "read-write"
# ::raSetFieldResetValue "stopwatch_csr" "padding" "0x0"
::raSetFieldResetMask "stopwatch_csr" "padding" "0xFFFFFFFF"
::raSetFieldReserved "stopwatch_csr" "padding" 1
# Field: Stride
::raAddRegisterField "stopwatch_csr" "stride" "Stride length"
::raSetFieldBitOffset "stopwatch_csr" "stride" 3
::raSetFieldBitWidth "stopwatch_csr" "stride" 4
::raSetFieldAccess "stopwatch_csr" "stride" "read-write"
# ::raSetFieldResetValue "stopwatch_csr" "stride" "0x0"
::raSetFieldResetMask "stopwatch_csr" "stride" "0xFFFFFFFF"
::raSetFieldCover "stopwatch_csr" "stride" 1
# Field: Updown
::raAddRegisterField "stopwatch_csr" "updown" "Indicates whether
counting up or down"
::raSetFieldBitOffset "stopwatch_csr" "updown" 2
::raSetFieldBitWidth "stopwatch_csr" "updown" 1
::raSetFieldAccess "stopwatch_csr" "updown" "read-write"
# ::raSetFieldResetValue "stopwatch_csr" "updown" "0x0"
::raSetFieldResetMask "stopwatch_csr" "updown" "0xFFFFFFFF"
::raSetFieldCover "stopwatch_csr" "updown" 1
::raAddFieldValue "stopwatch_csr" "updown" "countDown" "Counting down"
"0"
::raAddFieldValue "stopwatch_csr" "updown" "countUp" "Counting up" "1"
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
::raAddRegisterFileInstance "stopwatch_register_map"
"stopwatch_register_file" "sw1" ""
::raAddRegisterFileInstance "stopwatch_register_map"
"stopwatch_register_file" "sw2" ""
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
package output_pkg_uvm;
import uvm_pkg::*;
import mypkg::*;
`include "uvm_macros.svh"
//--------------------------------------------------------------------
// Class: stopwatch_lower_limit
//
// Lower limit
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_lower_limit");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: stopwatch_upper_limit
//
// Upper limit
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_upper_limit");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
//--------------------------------------------------------------------
// Class: stopwatch_reset_value
//
// Reset value
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_reset_value");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: stopwatch_memory
//
// Memory register
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_memory");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
// Class: stopwatch_csr
//
// Control Status Register
//--------------------------------------------------------------------
// Function: coverage
//
covergroup cg_vals;
stride : coverpoint stride.value[3:0];
updown : coverpoint updown.value[0];
upper_limit_reached : coverpoint upper_limit_reached.value[0];
lower_limit_reached : coverpoint lower_limit_reached.value[0];
endgroup
// Constraints
constraint my_constraint {x > 5;}
// Function: new
//
function new(string name = "stopwatch_csr");
super.new(name, 32, build_coverage(UVM_CVR_FIELD_VALS));
add_coverage(build_coverage(UVM_CVR_FIELD_VALS));
if(has_coverage(UVM_CVR_FIELD_VALS))
cg_vals = new();
endfunction
// Function: sample_values
//
virtual function void sample_values();
super.sample_values();
if (get_coverage(UVM_CVR_FIELD_VALS))
cg_vals.sample();
endfunction
// Function: build
//
virtual function void build();
padding = uvm_reg_field::type_id::create("padding");
stride = uvm_reg_field::type_id::create("stride");
updown = uvm_reg_field::type_id::create("updown");
upper_limit_reached =
uvm_reg_field::type_id::create("upper_limit_reached");
lower_limit_reached =
uvm_reg_field::type_id::create("lower_limit_reached");
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
//--------------------------------------------------------------------
// Class: stopwatch_value
//
// Current value
//--------------------------------------------------------------------
uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_value");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RO", 1, 32'h00000000, 1, 0, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: my_mem
//
// Memory
//--------------------------------------------------------------------
// Function: new
//
function new(string name = "my_mem");
super.new(name, 'h400, 32, "RW", UVM_NO_COVERAGE);
endfunction
endclass
//--------------------------------------------------------------------
// Class: my_reg
//
// Custom register
//--------------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
rand uvm_reg_field F;
// Function: new
//
function new(string name = "my_reg");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: stopwatch_counter
//
// Stop Watch Counter
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_counter");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
/* BLOCKS */
//--------------------------------------------------------------------
// Class: sw_sub_block_SW_MAP_coverage
//
// Coverage for the 'SW_MAP' in 'sw_sub_block'
//--------------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
option.per_instance = 1;
option.name = name;
endgroup: ra_cov
endclass: sw_sub_block_SW_MAP_coverage
//--------------------------------------------------------------------
// Class: sw_sub_block
//
// Sub_block for the stopwatch design
//--------------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
instance
rand stopwatch_csr stopwatch_csr_reg; // CSR instance
rand stopwatch_memory stopwatch_memory_reg[8]; // MEM instances
// Function: new
//
function new(string name = "sw_sub_block");
super.new(name, build_coverage(UVM_CVR_ALL));
endfunction
// Function: build
//
virtual function void build();
if(has_coverage(UVM_CVR_ADDR_MAP)) begin
SW_MAP_cg =
sw_sub_block_SW_MAP_coverage::type_id::create("SW_MAP_cg");
SW_MAP_cg.ra_cov.set_inst_name(this.get_full_name());
void'(set_coverage(UVM_CVR_ADDR_MAP));
end
stopwatch_value_reg =
stopwatch_value::type_id::create("stopwatch_value_reg");
stopwatch_value_reg.configure(this);
stopwatch_value_reg.build();
stopwatch_reset_value_reg =
stopwatch_reset_value::type_id::create("stopwatch_reset_value_reg");
stopwatch_reset_value_reg.configure(this);
stopwatch_reset_value_reg.build();
stopwatch_upper_limit_reg =
stopwatch_upper_limit::type_id::create("stopwatch_upper_limit_reg");
stopwatch_upper_limit_reg.configure(this);
stopwatch_upper_limit_reg.build();
stopwatch_lower_limit_reg =
stopwatch_lower_limit::type_id::create("stopwatch_lower_limit_reg");
stopwatch_lower_limit_reg.configure(this);
stopwatch_lower_limit_reg.build();
stopwatch_csr_reg =
stopwatch_csr::type_id::create("stopwatch_csr_reg");
stopwatch_csr_reg.configure(this);
stopwatch_csr_reg.build();
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
lock_model();
endfunction
// Function: sample
//
function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map
map);
if(get_coverage(UVM_CVR_ADDR_MAP)) begin
if(map.get_name() == "SW_MAP") begin
SW_MAP_cg.sample(offset, is_read);
end
end
endfunction: sample
endclass
//--------------------------------------------------------------------
// Class: sw_top_block_SW_MAP2_coverage
//
// Coverage for the 'SW_MAP2' in 'sw_top_block'
//--------------------------------------------------------------------
option.per_instance = 1;
option.name = name;
endgroup: ra_cov
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Output Example
endclass: sw_top_block_SW_MAP2_coverage
//--------------------------------------------------------------------
// Class: sw_top_block
//
// Top block for the stopwatch design
//--------------------------------------------------------------------
// Function: new
//
function new(string name = "sw_top_block");
super.new(name, build_coverage(UVM_CVR_ALL));
endfunction
// Function: build
//
virtual function void build();
if(has_coverage(UVM_CVR_ADDR_MAP)) begin
SW_MAP2_cg =
sw_top_block_SW_MAP2_coverage::type_id::create("SW_MAP2_cg");
SW_MAP2_cg.ra_cov.set_inst_name(this.get_full_name());
void'(set_coverage(UVM_CVR_ADDR_MAP));
end
sw1 = sw_sub_block::type_id::create("sw1");
sw1.configure(this);
sw1.build();
sw2 = sw_sub_block::type_id::create("sw2");
sw2.configure(this);
sw2.build();
vreg1 = stopwatch_counter::type_id::create("vreg1");
vreg1.configure(this, null, "top.counter1.count");
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
OVM Output Example
vreg1.build();
vreg2 = stopwatch_counter::type_id::create("vreg2");
vreg2.configure(this, null, "top.counter2.counter_i0.count");
vreg2.build();
vreg3 = stopwatch_counter::type_id::create("vreg3");
vreg3.configure(this, null, "top.counter2.counter_i1.count");
vreg3.build();
my_reg1 = my_reg::type_id::create("my_reg1");
my_reg1.configure(this);
my_reg1.build();
mem1 = my_mem::type_id::create("mem1");
mem1.configure(this);
SW_MAP2.add_submap(sw1.SW_MAP, 'h1000);
SW_MAP2.add_submap(sw2.SW_MAP, 'h2000);
SW_MAP2.add_reg(vreg1, 'h3000, "RW");
SW_MAP2.add_reg(vreg2, 'h3004, "RW");
SW_MAP2.add_reg(vreg3, 'h3008, "RW");
SW_MAP2.add_reg(my_reg1, 'h300c, "RW");
SW_MAP2.add_mem(mem1, 'h4000, "RW");
// Function: sample
//
function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map
map);
if(get_coverage(UVM_CVR_ADDR_MAP)) begin
if(map.get_name() == "SW_MAP2") begin
SW_MAP2_cg.sample(offset, is_read);
end
end
endfunction: sample
endclass
endpackage
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
OVM Output Example
package output_pkg_ovm;
import ovm_pkg::*;
`include "ovm_macros.svh"
import ovm_register_pkg::*;
`include "ovm_register_macros.svh"
//--------------------------------------------------------------------
// stopwatch_lower_limit
//--------------------------------------------------------------------
// Lower limit
class stopwatch_lower_limit extends ovm_register #(bit32_t);
`ovm_named_object_utils(stopwatch_lower_limit)
//------------------------------------------------------------------
// new
//------------------------------------------------------------------
function new(string name, ovm_named_object parent);
super.new(name, parent);
ovm_report_info("stopwatch_lower_limit::new()", get_full_name());
endfunction
endclass
//--------------------------------------------------------------------
// stopwatch_upper_limit
//--------------------------------------------------------------------
// Upper limit
class stopwatch_upper_limit extends ovm_register #(bit32_t);
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
OVM Output Example
`ovm_named_object_utils(stopwatch_upper_limit)
//------------------------------------------------------------------
// new
//------------------------------------------------------------------
function new(string name, ovm_named_object parent);
super.new(name, parent);
ovm_report_info("stopwatch_upper_limit::new()", get_full_name());
endfunction
endclass
//--------------------------------------------------------------------
// stopwatch_reset_value
//--------------------------------------------------------------------
// Reset value
class stopwatch_reset_value extends ovm_register #(bit32_t);
`ovm_named_object_utils(stopwatch_reset_value)
//------------------------------------------------------------------
// new
//------------------------------------------------------------------
function new(string name, ovm_named_object parent);
super.new(name, parent);
ovm_report_info("stopwatch_reset_value::new()", get_full_name());
endfunction
endclass
//--------------------------------------------------------------------
// stopwatch_csr
//--------------------------------------------------------------------
// Control Status Register
class stopwatch_csr extends ovm_register #(stopwatch_csr_t);
`ovm_named_object_utils(stopwatch_csr)
`ovm_register_begin_fields
`ovm_register_field(stride)
`ovm_register_enum_field(updown, stopwatch_csr_updown_enum)
`ovm_register_field(upper_limit_reached)
`ovm_register_field(lower_limit_reached)
`ovm_register_end_fields
//------------------------------------------------------------------
// coverage
//------------------------------------------------------------------
covergroup c;
stride : coverpoint data.stride;
updown : coverpoint data.updown;
upper_limit_reached : coverpoint data.upper_limit_reached;
lower_limit_reached : coverpoint data.lower_limit_reached;
endgroup
//------------------------------------------------------------------
// sample
//------------------------------------------------------------------
function void sample();
c.sample();
endfunction
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
OVM Output Example
//------------------------------------------------------------------
// new
//------------------------------------------------------------------
function new(string name, ovm_named_object parent);
super.new(name, parent);
ovm_report_info("stopwatch_csr::new()", get_full_name());
c = new();
`add_field_rw(stride, 4'h0);
`add_enum_field_rw(updown, stopwatch_csr_updown_countDown,
stopwatch_csr_updown_enum);
`add_field_ro(upper_limit_reached, 1'b0);
`add_field_ro(lower_limit_reached, 1'b0);
endfunction
//------------------------------------------------------------------
// convert2string
//------------------------------------------------------------------
function string convert2string();
return $psprintf("CSR: (%p) (%x %x %x %x %x )", data,
data.padding, data.stride, data.updown, data.upper_limit_reached,
data.lower_limit_reached);
endfunction
endclass
//--------------------------------------------------------------------
// stopwatch_memory
//--------------------------------------------------------------------
// Memory register
class stopwatch_memory extends ovm_register #(bit32_t);
`ovm_named_object_utils(stopwatch_memory)
//------------------------------------------------------------------
// new
//------------------------------------------------------------------
function new(string name, ovm_named_object parent);
super.new(name, parent);
ovm_report_info("stopwatch_memory::new()", get_full_name());
endfunction
endclass
//--------------------------------------------------------------------
// stopwatch_value
//--------------------------------------------------------------------
// Current value
class stopwatch_value extends ovm_register #(bit32_t);
`ovm_named_object_utils(stopwatch_value)
//------------------------------------------------------------------
// new
//------------------------------------------------------------------
function new(string name, ovm_named_object parent);
super.new(name, parent);
ovm_report_info("stopwatch_value::new()", get_full_name());
WMASK = 32'h00000000;
endfunction
endclass
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
OVM Output Example
/* REGISTER FILE */
//--------------------------------------------------------------------
// sw_reg_file
//--------------------------------------------------------------------
class sw_reg_file extends ovm_register_file;
`ovm_named_object_utils(sw_reg_file)
// Value instance
rand stopwatch_valueVALUE;
// Reset Value instance
rand stopwatch_reset_valueRESET_VALUE;
// Upper Limit instance
rand stopwatch_upper_limitUPPER_LIMIT;
// Lower Limit instance
rand stopwatch_lower_limitLOWER_LIMIT;
// CSR instance
rand stopwatch_csrCSR;
// MEM instances
rand stopwatch_memoryMEM[8];
//------------------------------------------------------------------
// new
//------------------------------------------------------------------
function new(string name, ovm_named_object parent);
super.new(name, parent);
ovm_report_info("sw_reg_file::new()", get_full_name());
VALUE.set_reset_value(32'h00000000);
RESET_VALUE.set_reset_value(32'h00000000);
UPPER_LIMIT.set_reset_value(32'h00000000);
LOWER_LIMIT.set_reset_value(32'h00000000);
CSR.set_reset_value(32'h00000000);
foreach(MEM[i]) begin
MEM[i].set_reset_value(32'h00000000);
end
endfunction
//------------------------------------------------------------------
// build_maps
//------------------------------------------------------------------
function void build_maps();
ovm_report_info("sw_reg_file::build_maps()", get_full_name());
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
OVM Output Example
add_register(VALUE.get_fullname(),'h4,VALUE);
add_register(RESET_VALUE.get_fullname(),'h8,RESET_VALUE);
add_register(UPPER_LIMIT.get_fullname(),'hc,UPPER_LIMIT);
add_register(LOWER_LIMIT.get_fullname(),'h10,LOWER_LIMIT);
add_register(CSR.get_fullname(),'h34,CSR);
foreach(MEM[i]) begin
add_register(MEM[i].get_fullname(), (i * ('h4)) + ('h14) ,
MEM[i]);
end
endfunction
//------------------------------------------------------------------
// do_copy
//------------------------------------------------------------------
function void do_copy(ovm_object rhs = null);
sw_reg_file l_rhs;
ovm_report_info("sw_reg_file::do_copy()", get_full_name());
$cast(l_rhs, rhs);
VALUE.copy(l_rhs.VALUE);
RESET_VALUE.copy(l_rhs.RESET_VALUE);
UPPER_LIMIT.copy(l_rhs.UPPER_LIMIT);
LOWER_LIMIT.copy(l_rhs.LOWER_LIMIT);
CSR.copy(l_rhs.CSR);
foreach(MEM[i]) begin
MEM[i].copy(l_rhs.MEM[i]);
end
endfunction
endclass
/* REGISTER MAP */
//--------------------------------------------------------------------
// sw_mem_map
//--------------------------------------------------------------------
class sw_mem_map extends ovm_register_map;
`ovm_named_object_utils(sw_mem_map)
//------------------------------------------------------------------
// new
//------------------------------------------------------------------
function new(string name, ovm_named_object parent);
super.new(name, parent);
ovm_report_info("sw_mem_map::new()", get_full_name());
endfunction
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
OVM Output Example
//------------------------------------------------------------------
// build_maps
//------------------------------------------------------------------
function void build_maps();
ovm_report_info("sw_mem_map::build_maps()", get_full_name());
sw1.build_maps();
sw2.build_maps();
add_register_file(sw1, 'h1000);
add_register_file(sw2, 'h2000);
endfunction
//------------------------------------------------------------------
// do_copy
//------------------------------------------------------------------
function void do_copy(ovm_object rhs = null);
sw_mem_map l_rhs;
ovm_report_info("sw_mem_map::do_copy()", get_full_name());
$cast(l_rhs, rhs);
sw1.copy(l_rhs.sw1);
sw2.copy(l_rhs.sw2);
endfunction
endclass
//
// Class to automatically load a register map.
//---------------------------------------------------------------------
// register_map_auto_load
//---------------------------------------------------------------------
class register_map_auto_load;
sw_mem_map register_map;
register_map.build_maps();
set_config_string("*",
"default_auto_register_test",
"register_sequence_all_registers#(REQ, RSP)");
set_config_object("*",
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
"register_map",
register_map, 0);
return 1;
endfunction
endclass
endpackage
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
------------------------------------------------------------------------
ENTITY top IS
------------------------------------------------------------------------
PORT
(
------------------------------------------------------------------------
ARCHITECTURE top_arch OF top IS
------------------------------------------------------------------------
-- READ/WRITE ENABLE SIGNALS
SIGNAL wen_REG1_inst : std_logic ;
SIGNAL wen_REG2_inst : std_logic ;
SIGNAL wen_REG3_inst : std_logic ;
SIGNAL wen_REG4_inst : std_logic ;
SIGNAL wen_REG5_inst : std_logic ;
SIGNAL wen_REG6_inst : std_logic ;
SIGNAL wen_REG7_inst : std_logic ;
-- AUXILIARY SIGNALS
SIGNAL Field_REG1_REG1_inst_local : std_logic_vector (7 DOWNTO 0);
SIGNAL Field_REG2_REG2_inst_local : std_logic_vector (7 DOWNTO 0);
SIGNAL Field_REG3_REG3_inst_local : std_logic_vector (7 DOWNTO 0);
SIGNAL Field_REG4_REG4_inst_local : std_logic_vector (7 DOWNTO 0);
SIGNAL Field_REG5_REG5_inst_local : std_logic_vector (7 DOWNTO 0);
SIGNAL Field_REG6_REG6_inst_local : std_logic_vector (7 DOWNTO 0);
SIGNAL Field_REG7_REG7_inst_local : std_logic_vector (7 DOWNTO 0);
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
--------------------------------------------------------------
-- Register: REG1
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: REG1_inst
-- Address Offset: 0x0
-- Reset Value :
--
-- Fields:
-- 7:0 Field_REG1 (SW:read-write, HW:None)
--------------------------------------------------------------
-- Field: Field_REG1
-- Width: 8 , Offset: 0
-- SW Access: read-write , HW Access: None
--------------------------------------------------------------
reg_reg1_field_reg1_reg1_inst_local : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
Field_REG1_REG1_inst_local <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (wen_REG1_inst_D1 = '1') THEN
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
--------------------------------------------------------------
-- Register: REG2
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: REG2_inst
-- Address Offset: 0x1
-- Reset Value :
--
-- Fields:
-- 7:0 Field_REG2 (SW:read-write, HW:None)
--------------------------------------------------------------
-- Field: Field_REG2
-- Width: 8 , Offset: 0
-- SW Access: read-write , HW Access: None
--------------------------------------------------------------
reg_reg2_field_reg2_reg2_inst_local : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
Field_REG2_REG2_inst_local <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (wen_REG2_inst_D1 = '1') THEN
Field_REG2_REG2_inst_local <= wdata_D2;
END IF;
END IF;
END PROCESS reg_reg2_field_reg2_reg2_inst_local;
--------------------------------------------------------------
-- Register: REG3
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: REG3_inst
-- Address Offset: 0x2
-- Reset Value :
--
-- Fields:
-- 7:0 Field_REG3 (SW:read-write, HW:None)
--------------------------------------------------------------
-- Field: Field_REG3
-- Width: 8 , Offset: 0
-- SW Access: read-write , HW Access: None
--------------------------------------------------------------
reg_reg3_field_reg3_reg3_inst_local : PROCESS (clock, reset)
BEGIN
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
-- Reset
IF (reset = '0') THEN
Field_REG3_REG3_inst_local <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (wen_REG3_inst_D1 = '1') THEN
Field_REG3_REG3_inst_local <= wdata_D2;
END IF;
END IF;
END PROCESS reg_reg3_field_reg3_reg3_inst_local;
--------------------------------------------------------------
-- Register: REG4
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: REG4_inst
-- Address Offset: 0x3
-- Reset Value :
--
-- Fields:
-- 7:0 Field_REG4 (SW:read-write, HW:None)
--------------------------------------------------------------
-- Field: Field_REG4
-- Width: 8 , Offset: 0
-- SW Access: read-write , HW Access: None
--------------------------------------------------------------
reg_reg4_field_reg4_reg4_inst_local : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
Field_REG4_REG4_inst_local <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (wen_REG4_inst_D1 = '1') THEN
Field_REG4_REG4_inst_local <= wdata_D2;
END IF;
END IF;
END PROCESS reg_reg4_field_reg4_reg4_inst_local;
--------------------------------------------------------------
-- Register: REG5
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: REG5_inst
-- Address Offset: 0x4
-- Reset Value :
--
-- Fields:
-- 7:0 Field_REG5 (SW:read-write, HW:None)
--------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
-- Field: Field_REG5
-- Width: 8 , Offset: 0
-- SW Access: read-write , HW Access: None
--------------------------------------------------------------
reg_reg5_field_reg5_reg5_inst_local : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
Field_REG5_REG5_inst_local <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (wen_REG5_inst_D1 = '1') THEN
Field_REG5_REG5_inst_local <= wdata_D2;
END IF;
END IF;
END PROCESS reg_reg5_field_reg5_reg5_inst_local;
--------------------------------------------------------------
-- Register: REG6
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: REG6_inst
-- Address Offset: 0x5
-- Reset Value :
--
-- Fields:
-- 7:0 Field_REG6 (SW:read-write, HW:None)
--------------------------------------------------------------
-- Field: Field_REG6
-- Width: 8 , Offset: 0
-- SW Access: read-write , HW Access: None
--------------------------------------------------------------
reg_reg6_field_reg6_reg6_inst_local : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
Field_REG6_REG6_inst_local <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (wen_REG6_inst_D1 = '1') THEN
Field_REG6_REG6_inst_local <= wdata_D2;
END IF;
END IF;
END PROCESS reg_reg6_field_reg6_reg6_inst_local;
--------------------------------------------------------------
-- Register: REG7
-- SW Access : read-write
-- Address Offset:
-- HW Access : read-write
--
-- Instance: REG7_inst
-- Address Offset: 0x6
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
-- Reset Value :
--
-- Fields:
-- 7:0 Field_REG7 (SW:read-write, HW:None)
--------------------------------------------------------------
-- Field: Field_REG7
-- Width: 8 , Offset: 0
-- SW Access: read-write , HW Access: None
--------------------------------------------------------------
reg_reg7_field_reg7_reg7_inst_local : PROCESS (clock, reset)
BEGIN
-- Reset
IF (reset = '0') THEN
Field_REG7_REG7_inst_local <= (OTHERS => '0');
ELSIF (clock'EVENT) AND (clock = '1') THEN
-- SW:read-write
IF (wen_REG7_inst_D1 = '1') THEN
Field_REG7_REG7_inst_local <= wdata_D2;
END IF;
END IF;
END PROCESS reg_reg7_field_reg7_reg7_inst_local;
-----------------------------------------------------------------------
-
-- READ BUS MULTIPLEXER
-----------------------------------------------------------------------
-
rmux_REG1_inst <= Field_REG1_REG1_inst_local;
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
RTL Pipelining Output Example
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
For more information on word addressing, refer to “Word Addressable Output” on page 201.
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
package output_pkg_uvm;
import uvm_pkg::*;
import mypkg::*;
`include "uvm_macros.svh"
//--------------------------------------------------------------------
// Class: stopwatch_lower_limit
//
// Lower limit
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_lower_limit");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: stopwatch_upper_limit
//
// Upper limit
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_upper_limit");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
//--------------------------------------------------------------------
// Class: stopwatch_reset_value
//
// Reset value
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_reset_value");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: stopwatch_memory
//
// Memory register
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_memory");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: stopwatch_csr
//
// Control Status Register
//--------------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
`uvm_object_utils(stopwatch_csr)
// Function: coverage
//
covergroup cg_vals;
stride : coverpoint stride.value[3:0];
updown : coverpoint updown.value[0];
upper_limit_reached : coverpoint upper_limit_reached.value[0];
lower_limit_reached : coverpoint lower_limit_reached.value[0];
endgroup
// Constraints
constraint my_constraint {x > 5;}
// Function: new
//
function new(string name = "stopwatch_csr");
super.new(name, 32, build_coverage(UVM_CVR_FIELD_VALS));
add_coverage(build_coverage(UVM_CVR_FIELD_VALS));
if(has_coverage(UVM_CVR_FIELD_VALS))
cg_vals = new();
endfunction
// Function: sample_values
//
virtual function void sample_values();
super.sample_values();
if (get_coverage(UVM_CVR_FIELD_VALS))
cg_vals.sample();
endfunction
// Function: build
//
virtual function void build();
padding = uvm_reg_field::type_id::create("padding");
stride = uvm_reg_field::type_id::create("stride");
updown = uvm_reg_field::type_id::create("updown");
upper_limit_reached =
uvm_reg_field::type_id::create("upper_limit_reached");
lower_limit_reached =
uvm_reg_field::type_id::create("lower_limit_reached");
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
//--------------------------------------------------------------------
// Class: stopwatch_value
//
// Current value
//--------------------------------------------------------------------
uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_value");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RO", 1, 32'h00000000, 1, 0, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: my_mem
//
// Memory
//--------------------------------------------------------------------
// Function: new
//
function new(string name = "my_mem");
super.new(name, 'h400, 32, "RW", UVM_NO_COVERAGE);
endfunction
endclass
//--------------------------------------------------------------------
// Class: my_reg
//
// Custom register
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "my_reg");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
//--------------------------------------------------------------------
// Class: stopwatch_counter
//
// Stop Watch Counter
//--------------------------------------------------------------------
rand uvm_reg_field F;
// Function: new
//
function new(string name = "stopwatch_counter");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
// Function: build
//
virtual function void build();
F = uvm_reg_field::type_id::create("F");
F.configure(this, 32, 0, "RW", 1, 32'h00000000, 1, 1, 1);
endfunction
endclass
/* BLOCKS */
//--------------------------------------------------------------------
// Class: sw_sub_block_SUB_MAP1_coverage
//
// Coverage for the 'SUB_MAP1' in 'sw_sub_block'
//--------------------------------------------------------------------
option.per_instance = 1;
option.name = name;
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
'h6,
'h7,
'h8,
'h9,
'ha,
'hb,
'hc};
}
endgroup: ra_cov
endclass: sw_sub_block_SUB_MAP1_coverage
//--------------------------------------------------------------------
// Class: sw_sub_block
//
// Sub_block for the stopwatch design
//--------------------------------------------------------------------
// Function: new
//
function new(string name = "sw_sub_block");
super.new(name, build_coverage(UVM_CVR_ALL));
endfunction
// Function: build
//
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
if(has_coverage(UVM_CVR_ADDR_MAP)) begin
SUB_MAP1_cg =
sw_sub_block_SUB_MAP1_coverage::type_id::create("SUB_MAP1_cg");
SUB_MAP1_cg.ra_cov.set_inst_name(this.get_full_name());
void'(set_coverage(UVM_CVR_ADDR_MAP));
end
stopwatch_value_reg =
stopwatch_value::type_id::create("stopwatch_value_reg");
stopwatch_value_reg.configure(this);
stopwatch_value_reg.build();
stopwatch_reset_value_reg =
stopwatch_reset_value::type_id::create("stopwatch_reset_value_reg");
stopwatch_reset_value_reg.configure(this);
stopwatch_reset_value_reg.build();
stopwatch_upper_limit_reg =
stopwatch_upper_limit::type_id::create("stopwatch_upper_limit_reg");
stopwatch_upper_limit_reg.configure(this);
stopwatch_upper_limit_reg.build();
stopwatch_lower_limit_reg =
stopwatch_lower_limit::type_id::create("stopwatch_lower_limit_reg");
stopwatch_lower_limit_reg.configure(this);
stopwatch_lower_limit_reg.build();
stopwatch_csr_reg =
stopwatch_csr::type_id::create("stopwatch_csr_reg");
stopwatch_csr_reg.configure(this);
stopwatch_csr_reg.build();
lock_model();
endfunction
// Function: sample
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
//
function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map
map);
if(get_coverage(UVM_CVR_ADDR_MAP)) begin
if(map.get_name() == "SUB_MAP1") begin
SUB_MAP1_cg.sample(offset, is_read);
end
end
endfunction: sample
endclass
//--------------------------------------------------------------------
// Class: sw_top_block_TOP_MAP_coverage
//
// Coverage for the 'TOP_MAP' in 'sw_top_block'
//--------------------------------------------------------------------
option.per_instance = 1;
option.name = name;
endgroup: ra_cov
endclass: sw_top_block_TOP_MAP_coverage
//--------------------------------------------------------------------
// Class: sw_top_block
//
// Top block for the stopwatch design
//--------------------------------------------------------------------
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
// Function: new
//
function new(string name = "sw_top_block");
super.new(name, build_coverage(UVM_CVR_ALL));
endfunction
// Function: build
//
virtual function void build();
add_hdl_path("top.dut");
if(has_coverage(UVM_CVR_ADDR_MAP)) begin
TOP_MAP_cg =
sw_top_block_TOP_MAP_coverage::type_id::create("TOP_MAP_cg");
TOP_MAP_cg.ra_cov.set_inst_name(this.get_full_name());
void'(set_coverage(UVM_CVR_ADDR_MAP));
end
foreach ( sw1[i] ) begin
sw1[i] = sw_sub_block::type_id::create($psprintf("sw1[%0d]",
i));
sw1[i].configure(this);
sw1[i].build();
end
sw2 = sw_sub_block::type_id::create("sw2");
sw2.configure(this);
sw2.build();
vreg1 = stopwatch_counter::type_id::create("vreg1");
vreg1.configure(this, null, "count_FF1");
vreg1.build();
vreg2 = stopwatch_counter::type_id::create("vreg2");
vreg2.configure(this, null, "count_FF2");
vreg2.build();
vreg3 = stopwatch_counter::type_id::create("vreg3");
vreg3.configure(this, null, "count_FF3");
vreg3.build();
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
my_reg1 = my_reg::type_id::create("my_reg1");
my_reg1.configure(this);
my_reg1.build();
mem1 = my_mem::type_id::create("mem1");
mem1.configure(this);
foreach(sw1[i]) begin
TOP_MAP.add_submap(sw1[i].SUB_MAP1, (i * ('hd)) + ('h1000));
end
TOP_MAP.add_submap(sw2.SUB_MAP1, 'h2000);
TOP_MAP.add_reg(vreg1, 'h3000, "RW");
TOP_MAP.add_reg(vreg2, 'h3001, "RW");
TOP_MAP.add_reg(vreg3, 'h3002, "RW");
TOP_MAP.add_reg(my_reg1, 'h3003, "RW");
TOP_MAP.add_mem(mem1, 'h3004, "RW");
lock_model();
endfunction
// Function: sample
//
function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map
map);
if(get_coverage(UVM_CVR_ADDR_MAP)) begin
if(map.get_name() == "TOP_MAP") begin
TOP_MAP_cg.sample(offset, is_read);
end
end
endfunction: sample
endclass
endpackage
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Examples
UVM Word Addressable Output Example
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Appendix C
Migrating to Register Assistant
This appendix provides information that you should know if you are migrating from Register
Assistant UVM tool (which supports only UVM output generation) to Register Assistant tool
(which in addition to UVM output generation also supports RTL, OVM, HTML, and so on).
Mapping Command Line Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Related Topics
Command Line Switches
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Migrating to Register Assistant
Mapping Command Line Switches
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
End-User License Agreement
The latest version of the End-User License Agreement is available on-line at:
www.mentor.com/eula
IMPORTANT INFORMATION
USE OF ALL SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS. CAREFULLY READ THIS LICENSE
AGREEMENT BEFORE USING THE PRODUCTS. USE OF SOFTWARE INDICATES CUSTOMER’S COMPLETE
AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT.
ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS AND CONDITIONS SHALL NOT APPLY.
This is a legal agreement concerning the use of Software (as defined in Section 2) and hardware (collectively “Products”)
between the company acquiring the Products (“Customer”), and the Mentor Graphics entity that issued the corresponding
quotation or, if no quotation was issued, the applicable local Mentor Graphics entity (“Mentor Graphics”). Except for license
agreements related to the subject matter of this license agreement which are physically signed by Customer and an authorized
representative of Mentor Graphics, this Agreement and the applicable quotation contain the parties’ entire understanding
relating to the subject matter and supersede all prior or contemporaneous agreements. If Customer does not agree to these
terms and conditions, promptly return or, in the case of Software received electronically, certify destruction of Software and all
accompanying items within five days after receipt of Software and receive a full refund of any license fee paid.
1.1. To the extent Customer (or if agreed by Mentor Graphics, Customer’s appointed third party buying agent) places and Mentor
Graphics accepts purchase orders pursuant to this Agreement (each an “Order”), each Order will constitute a contract between
Customer and Mentor Graphics, which shall be governed solely and exclusively by the terms and conditions of this Agreement,
any applicable addenda and the applicable quotation, whether or not those documents are referenced on the Order. Any
additional or conflicting terms and conditions appearing on an Order or presented in any electronic portal or automated order
management system, whether or not required to be electronically accepted, will not be effective unless agreed in writing and
physically signed by an authorized representative of Customer and Mentor Graphics.
1.2. Amounts invoiced will be paid, in the currency specified on the applicable invoice, within 30 days from the date of such invoice.
Any past due invoices will be subject to the imposition of interest charges in the amount of one and one-half percent per month
or the applicable legal rate currently in effect, whichever is lower. Prices do not include freight, insurance, customs duties, taxes
or other similar charges, which Mentor Graphics will state separately in the applicable invoice. Unless timely provided with a
valid certificate of exemption or other evidence that items are not taxable, Mentor Graphics will invoice Customer for all
applicable taxes including, but not limited to, VAT, GST, sales tax, consumption tax and service tax. Customer will make all
payments free and clear of, and without reduction for, any withholding or other taxes; any such taxes imposed on payments by
Customer hereunder will be Customer’s sole responsibility. If Customer appoints a third party to place purchase orders and/or
make payments on Customer’s behalf, Customer shall be liable for payment under Orders placed by such third party in the event
of default.
1.3. All Products are delivered FCA factory (Incoterms 2010), freight prepaid and invoiced to Customer, except Software delivered
electronically, which shall be deemed delivered when made available to Customer for download. Mentor Graphics retains a
security interest in all Products delivered under this Agreement, to secure payment of the purchase price of such Products, and
Customer agrees to sign any documents that Mentor Graphics determines to be necessary or convenient for use in filing or
perfecting such security interest. Mentor Graphics’ delivery of Software by electronic means is subject to Customer’s provision
of both a primary and an alternate e-mail address.
2. GRANT OF LICENSE. The software installed, downloaded, or otherwise acquired by Customer under this Agreement, including any
updates, modifications, revisions, copies, documentation, setup files and design data (“Software”) are copyrighted, trade secret and
confidential information of Mentor Graphics or its licensors, who maintain exclusive title to all Software and retain all rights not
expressly granted by this Agreement. Except for Software that is embeddable (“Embedded Software”), which is licensed pursuant to
separate embedded software terms or an embedded software supplement, Mentor Graphics grants to Customer, subject to payment of
applicable license fees, a nontransferable, nonexclusive license to use Software solely: (a) in machine-readable, object-code form
(except as provided in Subsection 4.2); (b) for Customer’s internal business purposes; (c) for the term of the license; and (d) on the
computer hardware and at the site authorized by Mentor Graphics. A site is restricted to a one-half mile (800 meter) radius. Customer
may have Software temporarily used by an employee for telecommuting purposes from locations other than a Customer office, such as
the employee’s residence, an airport or hotel, provided that such employee’s primary place of employment is the site where the
Software is authorized for use. Mentor Graphics’ standard policies and programs, which vary depending on Software, license fees paid
or services purchased, apply to the following: (a) relocation of Software; (b) use of Software, which may be limited, for example, to
execution of a single session by a single user on the authorized hardware or for a restricted period of time (such limitations may be
technically implemented through the use of authorization codes or similar devices); and (c) support services provided, including
eligibility to receive telephone support, updates, modifications, and revisions. For the avoidance of doubt, if Customer provides any
feedback or requests any change or enhancement to Products, whether in the course of receiving support or consulting services,
evaluating Products, performing beta testing or otherwise, any inventions, product improvements, modifications or developments made
by Mentor Graphics (at Mentor Graphics’ sole discretion) will be the exclusive property of Mentor Graphics.
3. BETA CODE.
3.1. Portions or all of certain Software may contain code for experimental testing and evaluation (which may be either alpha or beta,
collectively “Beta Code”), which may not be used without Mentor Graphics’ explicit authorization. Upon Mentor Graphics’
authorization, Mentor Graphics grants to Customer a temporary, nontransferable, nonexclusive license for experimental use to
test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics. Mentor Graphics may
choose, at its sole discretion, not to release Beta Code commercially in any form.
3.2. If Mentor Graphics authorizes Customer to use the Beta Code, Customer agrees to evaluate and test the Beta Code under normal
conditions as directed by Mentor Graphics. Customer will contact Mentor Graphics periodically during Customer’s use of the
Beta Code to discuss any malfunctions or suggested improvements. Upon completion of Customer’s evaluation and testing,
Customer will send to Mentor Graphics a written evaluation of the Beta Code, including its strengths, weaknesses and
recommended improvements.
3.3. Customer agrees to maintain Beta Code in confidence and shall restrict access to the Beta Code, including the methods and
concepts utilized therein, solely to those employees and Customer location(s) authorized by Mentor Graphics to perform beta
testing. Customer agrees that any written evaluations and all inventions, product improvements, modifications or developments
that Mentor Graphics conceived or made during or subsequent to this Agreement, including those based partly or wholly on
Customer’s feedback, will be the exclusive property of Mentor Graphics. Mentor Graphics will have exclusive rights, title and
interest in all such property. The provisions of this Subsection 3.3 shall survive termination of this Agreement.
4. RESTRICTIONS ON USE.
4.1. Customer may copy Software only as reasonably necessary to support the authorized use. Each copy must include all notices
and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics. All copies shall
remain the property of Mentor Graphics or its licensors. Except for Embedded Software that has been embedded in executable
code form in Customer’s product(s), Customer shall maintain a record of the number and primary location of all copies of
Software, including copies merged with other software, and shall make those records available to Mentor Graphics upon
request. Customer shall not make Products available in any form to any person other than Customer’s employees and on-site
contractors, excluding Mentor Graphics competitors, whose job performance requires access and who are under obligations of
confidentiality. Customer shall take appropriate action to protect the confidentiality of Products and ensure that any person
permitted access does not disclose or use Products except as permitted by this Agreement. Customer shall give Mentor Graphics
written notice of any unauthorized disclosure or use of the Products as soon as Customer becomes aware of such unauthorized
disclosure or use. Customer acknowledges that Software provided hereunder may contain source code which is proprietary and
its confidentiality is of the highest importance and value to Mentor Graphics. Customer acknowledges that Mentor Graphics
may be seriously harmed if such source code is disclosed in violation of this Agreement. Except as otherwise permitted for
purposes of interoperability as specified by applicable and mandatory local law, Customer shall not reverse-assemble,
disassemble, reverse-compile, or reverse-engineer any Product, or in any way derive any source code from Software that is not
provided to Customer in source code form. Log files, data files, rule files and script files generated by or for the Software
(collectively “Files”), including without limitation files containing Standard Verification Rule Format (“SVRF”) and Tcl
Verification Format (“TVF”) which are Mentor Graphics’ trade secret and proprietary syntaxes for expressing process rules,
constitute or include confidential information of Mentor Graphics. Customer may share Files with third parties, excluding
Mentor Graphics competitors, provided that the confidentiality of such Files is protected by written agreement at least as well as
Customer protects other information of a similar nature or importance, but in any case with at least reasonable care. Customer
may use Files containing SVRF or TVF only with Mentor Graphics products. Under no circumstances shall Customer use
Products or Files or allow their use for the purpose of developing, enhancing or marketing any product that is in any way
competitive with Products, or disclose to any third party the results of, or information pertaining to, any benchmark.
4.2. If any Software or portions thereof are provided in source code form, Customer will use the source code only to correct software
errors and enhance or modify the Software for the authorized use, or as permitted for Embedded Software under separate
embedded software terms or an embedded software supplement. Customer shall not disclose or permit disclosure of source
code, in whole or in part, including any of its methods or concepts, to anyone except Customer’s employees or on-site
contractors, excluding Mentor Graphics competitors, with a need to know. Customer shall not copy or compile source code in
any manner except to support this authorized use.
4.3. Customer agrees that it will not subject any Product to any open source software (“OSS”) license that conflicts with this
Agreement or that does not otherwise apply to such Product.
4.4. Customer may not assign this Agreement or the rights and duties under it, or relocate, sublicense, or otherwise transfer the
Products, whether by operation of law or otherwise (“Attempted Transfer”), without Mentor Graphics’ prior written consent and
payment of Mentor Graphics’ then-current applicable relocation and/or transfer fees. Any Attempted Transfer without Mentor
Graphics’ prior written consent shall be a material breach of this Agreement and may, at Mentor Graphics’ option, result in the
immediate termination of the Agreement and/or the licenses granted under this Agreement. The terms of this Agreement,
including without limitation the licensing and assignment provisions, shall be binding upon Customer’s permitted successors in
interest and assigns.
4.5. The provisions of this Section 4 shall survive the termination of this Agreement.
5. SUPPORT SERVICES. To the extent Customer purchases support services, Mentor Graphics will provide Customer with updates and
technical support for the Products, at the Customer site(s) for which support is purchased, in accordance with Mentor Graphics’ then
current End-User Support Terms located at http://supportnet.mentor.com/supportterms.
6. OPEN SOURCE SOFTWARE. Products may contain OSS or code distributed under a proprietary third party license agreement, to
which additional rights or obligations (“Third Party Terms”) may apply. Please see the applicable Product documentation (including
license files, header files, read-me files or source code) for details. In the event of conflict between the terms of this Agreement
(including any addenda) and the Third Party Terms, the Third Party Terms will control solely with respect to the OSS or third party
code. The provisions of this Section 6 shall survive the termination of this Agreement.
7. LIMITED WARRANTY.
7.1. Mentor Graphics warrants that during the warranty period its standard, generally supported Products, when properly installed,
will substantially conform to the functional specifications set forth in the applicable user manual. Mentor Graphics does not
warrant that Products will meet Customer’s requirements or that operation of Products will be uninterrupted or error free. The
warranty period is 90 days starting on the 15th day after delivery or upon installation, whichever first occurs. Customer must
notify Mentor Graphics in writing of any nonconformity within the warranty period. For the avoidance of doubt, this warranty
applies only to the initial shipment of Software under an Order and does not renew or reset, for example, with the delivery of (a)
Software updates or (b) authorization codes or alternate Software under a transaction involving Software re-mix. This warranty
shall not be valid if Products have been subject to misuse, unauthorized modification, improper installation or Customer is not in
compliance with this Agreement. MENTOR GRAPHICS’ ENTIRE LIABILITY AND CUSTOMER’S EXCLUSIVE
REMEDY SHALL BE, AT MENTOR GRAPHICS’ OPTION, EITHER (A) REFUND OF THE PRICE PAID UPON
RETURN OF THE PRODUCTS TO MENTOR GRAPHICS OR (B) MODIFICATION OR REPLACEMENT OF THE
PRODUCTS THAT DO NOT MEET THIS LIMITED WARRANTY. MENTOR GRAPHICS MAKES NO WARRANTIES
WITH RESPECT TO: (A) SERVICES; (B) PRODUCTS PROVIDED AT NO CHARGE; OR (C) BETA CODE; ALL OF
WHICH ARE PROVIDED “AS IS.”
7.2. THE WARRANTIES SET FORTH IN THIS SECTION 7 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NOR ITS
LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO
PRODUCTS PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY
DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.
8. LIMITATION OF LIABILITY. TO THE EXTENT PERMITTED UNDER APPLICABLE LAW, IN NO EVENT SHALL
MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES (INCLUDING LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER
LEGAL THEORY, EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. IN NO EVENT SHALL MENTOR GRAPHICS’ OR ITS LICENSORS’ LIABILITY UNDER THIS
AGREEMENT EXCEED THE AMOUNT RECEIVED FROM CUSTOMER FOR THE HARDWARE, SOFTWARE LICENSE OR
SERVICE GIVING RISE TO THE CLAIM. IN THE CASE WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS
LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 8
SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT.
9.1. Customer acknowledges that Mentor Graphics has no control over the testing of Customer’s products, or the specific
applications and use of Products. Mentor Graphics and its licensors shall not be liable for any claim or demand made against
Customer by any third party, except to the extent such claim is covered under Section 10.
9.2. In the event that a third party makes a claim against Mentor Graphics arising out of the use of Customer’s products, Mentor
Graphics will give Customer prompt notice of such claim. At Customer’s option and expense, Customer may take sole control
of the defense and any settlement of such claim. Customer WILL reimburse and hold harmless Mentor Graphics for any
LIABILITY, damages, settlement amounts, costs and expenses, including reasonable attorney’s fees, incurred by or awarded
against Mentor Graphics or its licensors in connection with such claims.
9.3. The provisions of this Section 9 shall survive any expiration or termination of this Agreement.
10. INFRINGEMENT.
10.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against Customer in the United States,
Canada, Japan, or member state of the European Union which alleges that any standard, generally supported Product acquired
by Customer hereunder infringes a patent or copyright or misappropriates a trade secret in such jurisdiction. Mentor Graphics
will pay costs and damages finally awarded against Customer that are attributable to such action. Customer understands and
agrees that as conditions to Mentor Graphics’ obligations under this section Customer must: (a) notify Mentor Graphics
promptly in writing of the action; (b) provide Mentor Graphics all reasonable information and assistance to settle or defend the
action; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the action.
10.2. If a claim is made under Subsection 10.1 Mentor Graphics may, at its option and expense: (a) replace or modify the Product so
that it becomes noninfringing; (b) procure for Customer the right to continue using the Product; or (c) require the return of the
Product and refund to Customer any purchase price or license fee paid, less a reasonable allowance for use.
10.3. Mentor Graphics has no liability to Customer if the action is based upon: (a) the combination of Software or hardware with any
product not furnished by Mentor Graphics; (b) the modification of the Product other than by Mentor Graphics; (c) the use of
other than a current unaltered release of Software; (d) the use of the Product as part of an infringing process; (e) a product that
Customer makes, uses, or sells; (f) any Beta Code or Product provided at no charge; (g) any software provided by Mentor
Graphics’ licensors who do not provide such indemnification to Mentor Graphics’ customers; (h) OSS, except to the extent that
the infringement is directly caused by Mentor Graphics’ modifications to such OSS; or (i) infringement by Customer that is
deemed willful. In the case of (i), Customer shall reimburse Mentor Graphics for its reasonable attorney fees and other costs
related to the action.
10.4. THIS SECTION 10 IS SUBJECT TO SECTION 8 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR
GRAPHICS AND ITS LICENSORS, AND CUSTOMER’S SOLE AND EXCLUSIVE REMEDY, FOR DEFENSE,
SETTLEMENT AND DAMAGES, WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT
OR TRADE SECRET MISAPPROPRIATION BY ANY PRODUCT PROVIDED UNDER THIS AGREEMENT.
11.1. If a Software license was provided for limited term use, such license will automatically terminate at the end of the authorized
term. Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement immediately upon
written notice if Customer: (a) exceeds the scope of the license or otherwise fails to comply with the licensing or confidentiality
provisions of this Agreement, or (b) becomes insolvent, files a bankruptcy petition, institutes proceedings for liquidation or
winding up or enters into an agreement to assign its assets for the benefit of creditors. For any other material breach of any
provision of this Agreement, Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement
upon 30 days written notice if Customer fails to cure the breach within the 30 day notice period. Termination of this Agreement
or any license granted hereunder will not affect Customer’s obligation to pay for Products shipped or licenses granted prior to
the termination, which amounts shall be payable immediately upon the date of termination.
11.2. Upon termination of this Agreement, the rights and obligations of the parties shall cease except as expressly set forth in this
Agreement. Upon termination of this Agreement and/or any license granted under this Agreement, Customer shall ensure that
all use of the affected Products ceases, and shall return hardware and either return to Mentor Graphics or destroy Software in
Customer’s possession, including all copies and documentation, and certify in writing to Mentor Graphics within ten business
days of the termination date that Customer no longer possesses any of the affected Products or copies of Software in any form.
12. EXPORT. The Products provided hereunder are subject to regulation by local laws and European Union (“E.U.”) and United States
(“U.S.”) government agencies, which prohibit export, re-export or diversion of certain products, information about the products, and
direct or indirect products thereof, to certain countries and certain persons. Customer agrees that it will not export or re-export Products
in any manner without first obtaining all necessary approval from appropriate local, E.U. and U.S. government agencies. If Customer
wishes to disclose any information to Mentor Graphics that is subject to any E.U., U.S. or other applicable export restrictions, including
without limitation the U.S. International Traffic in Arms Regulations (ITAR) or special controls under the Export Administration
Regulations (EAR), Customer will notify Mentor Graphics personnel, in advance of each instance of disclosure, that such information
is subject to such export restrictions.
13. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. The parties agree that all Software is
commercial computer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to U.S. FAR 48
CFR 12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. government or a U.S.
government subcontractor is subject solely to the terms and conditions set forth in this Agreement, which shall supersede any
conflicting terms or conditions in any government order document, except for provisions which are contrary to applicable mandatory
federal laws.
14. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporation and
other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein.
15. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice and during
Customer’s normal business hours, Mentor Graphics may engage an internationally recognized accounting firm to review Customer’s
software monitoring system and records deemed relevant by the internationally recognized accounting firm to confirm Customer’s
compliance with the terms of this Agreement or U.S. or other local export laws. Such review may include FlexNet (or successor
product) report log files that Customer shall capture and provide at Mentor Graphics’ request. Customer shall make records available in
electronic format and shall fully cooperate with data gathering to support the license review. Mentor Graphics shall bear the expense of
any such review unless a material non-compliance is revealed. Mentor Graphics shall treat as confidential information all information
gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights
under this Agreement. The provisions of this Section 15 shall survive the termination of this Agreement.
16. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of certain Mentor Graphics intellectual
property licensed under this Agreement are located in Ireland and the U.S. To promote consistency around the world, disputes shall be
resolved as follows: excluding conflict of laws rules, this Agreement shall be governed by and construed under the laws of the State of
Oregon, U.S., if Customer is located in North or South America, and the laws of Ireland if Customer is located outside of North or
South America or Japan, and the laws of Japan if Customer is located in Japan. All disputes arising out of or in relation to this
Agreement shall be submitted to the exclusive jurisdiction of the courts of Portland, Oregon when the laws of Oregon apply, or Dublin,
Ireland when the laws of Ireland apply, or the Tokyo District Court when the laws of Japan apply. Notwithstanding the foregoing, all
disputes in Asia (excluding Japan) arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a
single arbitrator to be appointed by the chairman of the Singapore International Arbitration Centre (“SIAC”) to be conducted in the
English language, in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to be
incorporated by reference in this section. Nothing in this section shall restrict Mentor Graphics’ right to bring an action (including for
example a motion for injunctive relief) against Customer in the jurisdiction where Customer’s place of business is located. The United
Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement.
17. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid, unenforceable or
illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect.
18. MISCELLANEOUS. This Agreement contains the parties’ entire understanding relating to its subject matter and supersedes all prior
or contemporaneous agreements. Any translation of this Agreement is provided to comply with local legal requirements only. In the
event of a dispute between the English and any non-English versions, the English version of this Agreement shall govern to the extent
not prohibited by local law in the applicable jurisdiction. This Agreement may only be modified in writing, signed by an authorized
representative of each party. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent, waiver
or excuse.