Design of a FPGA-Based Multiple Motors Control

System

Yue Ma, Rong Xiong, and Fan Zhang

Institute of Cyber-Systems and Control, Zhejiang University, Hangzhou, 310027

mayue.zju@gmail.com, rxiong@iipc.zju.edu.cn,
Isaac33zhang@gmail.com

Abstract. In this paper, a FPGA-based motor control system is designed to

fulfill the requirement of controlling multiple motors accurately and
simultaneously. With the implementation of hardware logic modules with
hardware description language, each control module works independently in a
parallel mode, so the control frequency of motors is elevated. By modifying the
signal sampling method for the motor encoder, the speed measurement accuracy
is significantly improved. The proposed control system is successfully applied
on the platform of RoboCup small size soccer robot of Zhejiang University,
ZJUNlict, in which the improvements on response speed and control accuracy
of the robots are verified.

Keywords: Robot, FPGA, BLDC motor, small, parallel.

1 Introduction
Frequently, a motor controller is used for only one motor in robot system, while the
synchronous control of the motors is realized through the controller clock
synchronization [1-5] . Due to the limits of weight and volume, it is desirable to
control multiple motors simultaneously with single motor controller. In this way, the
accurate synchronous control of multiple motors can be ensured by the shared
controller’s clock while the motors is required to work in parallel to guarantee the
control frequency.
In general, the DSP or FPGA are both used as motor control chips. The DSP
controller calculates fast and works well at floating-point operation. However, each
piece of DSP chip usually has only two way outputs. Once there are more than two
motors to be controlled, extra DSP chips are thus needed [6-8], which extraordinarily
increases the volume and cost of control circuit. Due to its flexible port configuration,
FPGA with embedded CPU IP core is widely used in motor control system. Though it
can realize multiple motors’ closed-loop control, the function of operation is a little
bit weak [9-12]. When multiple motors are controlled, each motor’s control cycle will
be evidently extended, which results in large overshoot and low steady precision of
the speed feedback.
In this paper, a parallel multi-motor control system based on FPGA and by the way
of logic programming is realized, which uses logic hardware to implement the closed-
loop speed control, so that each motor has an independent logic controlling module.

D. Yang (Ed.): Informatics in Control, Automation and Robotics, Volume 2, LNEE 133, pp. 557–567.
springerlink.com © Springer-Verlag Berlin Heidelberg 2011
558 M. Yue, X. Rong, and Z. Fan

Since multi-motor closed-loop control logic modules works in parallel without any
interaction, the motor control frequency will not be deteriorated by the amount of the
motors. This logic hardware implementation can minimize the external logic circuit
and reduce the volume and cost extremely. Meanwhile, the motor’s encoder signal
sampling method in the system is improved so that the speed measuring accuracy is
enhanced. The multi-motor control system works successfully in Robocup small size
robot soccer on-board subsystem of ZJUNlict teams of Zhejiang University. The
experimental tests demonstrate that the response speed and control accuracy of the
robot are improved by the proposed method.

2 System Architecture
The control system based on FPGA is shown in Fig 1, which is composed of a IP core
embedded controller and some motor control modules. IP core controller is the core
of the whole system. It is responsible for initializing the robot system, collecting the
robot's sensors information, calculating the set points for each motor according to the
requirements, and assigning values to the motor control modules through the motor
control peripheral interfaces. Each motor has a motor control module, which is
responsible for the motor velocity closed-loop control, including filtering the input
digital signal, measuring the motor velocity, operating PI, modulating the PWM
wave, commutating the brushless motor, protecting the whole circuit against over-
current and so on.
IP core embedded controller and motor control modules work in parallel. All of the
logic functions about the motor control can be integrated in one FPGA chip, and there
is no need of other logical control chips such as chip MC33035 used to modulate
BLDC motors. The integrated design makes the control system lighter, smaller, more
stable and with lower power consumption. For the mobile robot, the shape will be
more elegant if the size of control circuit is smaller. Also, lighter weight and lower
power consumption means that the battery capacity can be reduced, so that the battery
weight and size will be cut. The system’s CPU focuses on the response of external
signals, while the traditional method spends a lot of time in calculating the each motor
control objects' PI regulators with a serial multi-motor control algorithm.
Consequently, the real-time performance of the system is enhanced. Because each
motor control module works in parallel, when the system needs one more motors, the
real-time performance and control frequency of system will not be hurt.
The multi-motor parallel control system in parallel is only limited by the FPGA's
pin number and capacity. With the popularity of the BGA package and increasing
capacity of FPGA, these two constraints will not be problems in future. In our system,
a single motor control module requires 11 clock control cycles, so the frequency of
the motor control modules is limited by the FPGA clock frequency; controlling a
brushless motor with hall sensors requires a total of 12 pins: 2 encoder pins, 3 hall
signal pins, 1 over-current signal pin, 6 motor drive pins; controlling a brush motor
requires 2 encoder pins and 4 motor drive pins. Since each motor control module
occupies 25,000 gates, the system should select the FPGA which has an appropriate
size and pin number. According to the conditions above, Altera's FPGA
EP3C25Q240C8 is selected.
 Design of a FPGA-Based Multiple Motors Control System 559

l
l
a
H

Fig. 1. Multi-motor control system structure

3 Design of Motor Control Module

The motor control module is realized by hardware logic, which consists of signal
、
filtering sub-module high-precision velocity measuring sub-module, PI controller
operating sub-module, Pulse Width Modulation sub-module, over-current protecting
sub-module, BLDC commutating sub-module and so on. Sub-module is written by
Verilog HDL language and can be encapsulated into block diagram which can also be
invoked into upper block diagram. The top-level map of motor control module is
shown in Fig 2.

Fig. 2. Top-level map of motor control module

560 M. Yue, X. Rong, and Z. Fan

The main difficulty of using hardware logic to realize the motor control module is
the correctness of the value involved to calculate. Complex hardware logic function
consists of some simple circuit logic units which are all working independently, such
as register, trigger, adder, multiplier and so on. PI closed-loop calculating function is
executed each control cycle, in which the result of the controller got in the last cycle
is also needed. In this paper, the closed-loop function is divided into many sub-
modules. There is an enable pin for each sub-module and the number of the clock
cycles between its input moment and its output moment has been restricted. There is a
state machine sub-module in this system which triggers every sub-module in order of
the data flow to make sure that the value in registers of sub-modules will not be
replaced by mistake. There is also an enable pin for state machine sub-module which
is triggered by controller timer. Every 2ms, the controller timer triggers the state
machine and then the state machine triggers the other sub-module to complete the PI
closed-loop calculation. What’s more, hardware logic development is different from
software program development. Designers have to deal with the positive and negative
、 、
value the implementing of the base circuit the temporal logic and the combination
logic. Logic simulation is a kind of indispensible development tools, by which
designers can check the value of every register and find out the logic mistakes more
easily, compared with the hardware debugging.
Fig 3 shows the function structure of the BLDC motor control sub-module. All the
modules of this system are triggered by the same synchronous clock signal. A and B
are orthogonal input signals of the encoder; SA, SB, SC are the hall commutating
signal of the BLDC motor; I is the over-current signal of the motor; AT, BT, CT, AB,
BB, CB are signals that trigger the converter of the BLDC motor; SET is from
software core controller. The cycle period how long the system executes PI
calculation can be set by users, while here it is set to 2ms. The state machine is used
to control enable signal involved in order because they are working in parallel while
the PID calculating process is executed serially. There is a timer in this system, which
triggers the state machine to calculate the PI value once every cycle.
、
Now the input signal filtering sub-module high-precision velocity measuring sub-
、 、
module PI operating sub-module BLDC commutating sub-module are to be
introduced in detail as follows.

Fig. 3. Functional map of motor control module

3.1 Input Signal Filtering Sub-module

Encoder signals, hall signals, over-current signals and other signals of the motor are
all connected to the control circuit boards by wires and connectors. These signals sent
 Design of a FPGA-Based Multiple Motors Control System 561

to the decision module as judging basis often have electronic interference, which need
to be removed via input signal filtering sub-module.
Input signal filtering sub-module uses a signal sequence check method. Samples
are taken from the input signals once every clock cycle and compared with those got
in the last clock cycle. If they are equivalent, the sampling counter will increase by 1.
Otherwise sampling counter will be clear. If the sampling counter is accumulated to
number N, which means that the signal has been held on for N times, then the
sampling signal is considered as an effective signal and then sent to the next unit to
proceed.

3.2 Velocity Measuring Sub-module

Velocity measuring sub-module is designed to detect the direction of the motor’s

rotation by comparing the two-way pulse signal captured by motor light code wheel
and to precisely calculate the speed of the motor rotation through improved-M
algorithm. This sub-module consists of two sub slave modules. One of them accounts
for the measurement of signal A and B. It produces a pulse defined as “count” once
signal A or B changes. The other is applied to record the status of the pulse output
from the former module in unit sampling time and then calculates the current speed of
the motor.
The traditional M algorithm obtains the angle of the motor rotation in unit
sampling time “t” by multiplying by the angle that the motor rolls between two pulses
and the number of the pulses “M” in the same period. The error of this algorithm
comes from the method that regards the number of the pulses as the real angle of the
motor rotation. In this way, the angle between the start of the sampling and the first
pulse will be omitted and so does the angle between the final pulse and the end of the
sampling. The precision of the sampling can be improved by increasing the number of
the code wheel line which, however, has no meaning for eliminating the error. To
solve this problem, an improved-M algorithm is proposed herein.
The precision of the sampling in traditional M algorithm is:
2π 360°
Δ= = . (1)
4*L 4*L

1
Δv = . (2)
4*L*t
in which Δ stands for the angle of the motor rotation between two pulses of the code
wheel; Δv is the precision of the velocity indicated by the code wheel sampling; and L
is the number of the code wheel line.
Improved-M algorithm: based on the M algorithm, in a given time “t”, the pulse
count that between start of the sampling and the first pulse, so does the pulse count
between the final pulse and the end of the sampling will be add to M as the decimal
part which is got by dividing the interval mentioned above by their whole period
between two pulse.
The time series of the improved-M algorithm is shown as Fig 4. A and B are the
orthogonal input signals of the code wheel; t is the unit sampling time; T1 is the
starting time of t; T2 is the ending time of t; t1 is the time from T1 to the first change
562 M. Yue, X. Rong, and Z. Fan

of signal A or B; t2 is the time from the final change of signal A or B to T2; t3 is the
time between two changes of signal A, B before T1; t4 is the time between two
changes of signal A, B before T2; t5 is the time between two changes of signal A, B
which T1 is contained; t6 is the time between two changes of signal A, B which T2 is
contained. Therefore the sampling value of the code wheel calculated through the
improved-M algorithm is:
t1 t2
MM = M − 1 + + . (3)
t3 t4

in which M is the velocity of the motor rotation measured by the improved-M

algorithm; M-1 is the angle that the motor rolls during M pulses; t1/t3 is the angle that
the motor rolls from the start of the sampling time to the arrival of the first pulse; t2/t4
is the angle that the motor rolls from the arrival of the final pulse to the end of the
sampling time.
Improved-M algorithm improves the precision of the sampling of the signal from
the code wheel in unit sampling time so that the value calculated is much closer to the
true value of the current velocity of the motor rotation. In this way, the algorithm
creates a high-precision feedback which could contribute to the high-precision motor
control system.
The error of the improved-M algorithm comes from the assumption that the
interval between two pulse are const, i.e., t3=t5, t4=t6. In this assumption, the error
will increase when the speed of the motor is at a low level. The measurement of t1-t4
is based on the system clock. The error can be ignored because of the high frequency
of the system clock.
Definition:
t5 = Δ1 + t3 . (4)

t6 = Δ 2 + t4 . (5)
The precision of the sampling in improved-M algorithm is:
t1 t2 t1 t2
ΔMM = + − − . (6)
t3 + Δ1 t4 + Δ 2 t3 t4
in which the value of Δ1 and Δ2 is affected by the acceleration of the motor.

Fig. 4. Timing diagram of improved-M algorithm

 Design of a FPGA-Based Multiple Motors Control System 563

3.3 PI Operating Sub-module

The PI operating sub-module is applied to execute PI operation with the set from CPU
and the velocity from the velocity measuring sub-module. The result will be the duty
value of PWM modulation module after amplitude limitation and parameter
compensation.
The PI operating sub-module uses the incremental PI algorithm which calculates
the control incremental value Δ based on difference between the setting value of the
motor control module and the current rotational velocity measured by improved-M
algorithm. With the purpose of reducing the procedure of the operation, the parameter
Kp and Ki of the PI formula is combined together. When the program sets the
parameters of the motor control module, the setting parameter is also of A and B. It is
aimed to ensure that Δ calculation in one cycle.
PI computing formula is:
Δ = A*error − B*pre _ error . (7)

A = Kp + Ki . (8)

B = Ki . (9)

U （k）= U(k − 1) + Δ . (10)

3.4 BLDC Motor Commutating Sub-module

The BLDC motor commutating sub-module is used to decode the input hall signal of
the motor, then drive the three-phase BLDC motor by measuring the position of the
motor. In addition, it can drive the BLDC motor when the FPGA chip sets the hall
signal in a fixed value.
The BLDC motor commutation apply the trapezoidal wave commutating mode,
which estimate the rotor’s position by the output signal of hall sensors, and turn on
the MOS-FETs in corresponding phase sequence to drive the rotor. The MOS-FET of
upper bridge of the three-phase full controlled bridge is put in sequence of 1, 3, 5,
while the MOS-FETs of lower bridge is put in sequence of 4, 6, 2. The hall signal SA,
SB, SC is in sequence of 100, 110, 010, 011, 001 and 101. So, when the motor rotates
clockwise, the sequence of turning on the MOS-FETs is: 12, 23, 34, 45, 56, 61, while
when the motor rotates anti-clockwise, the sequence of turning on the MOS-FETs is:
45, 56, 61, 12, 23 and 34.

4 Test Results
Robocup small size soccer robot is required to control four wheel-drive motors and
one dribble-control motor simultaneously. The robot with the limit that its diameter
cannot exceed 180 millimeters and its height cannot exceed 150 millimeters is based
on typical mobile robot motion control system which strictly limits the volume of
control circuit. Therefore, the ZJUNlict small size soccer robot control system is
564 M. Yue, X. Rong, and Z. Fan

designed using the technological method above and conduct the performance test and
comparison.
The wheel-drive motor is disc type motor whose rated power is 45 watts. Its rated
rotational speed is 5000 rpm and grid number of its photoelectric encoder is 512. The
dribble-control motor is hollow cup motor whose rated power is 15 watts and rated
rotational speed is 40000 rpm. Five motors are all blushless motors. The maximum
acceleration of robot is 4m2/s, corresponding 198rad2/s for motor. The circuit system
we design is showed in Fig 5. Circuit boards use laminated structure, which provide
sufficient protection for each part of circuit including core board, motherboard, driver
board and power board from top to bottom. Since small size soccer robots may
encounter strong collision with opponents during competition and circuit boards are
easily damaged or burned, adding protection can make circuit boards more stable and
easier to maintain.
A Labview-based data collection platform is developed to observe conveniently the
dynamic response process of motor. The platform can set up incentive mode,
incentive parameter, open or closed loop control mode, PI operating parameter and
upload data type. After the robot receives computer instruction, it will move
according to the computer specified way and upload real time data at the rate of
packet/6ms. Data collection platform can display received data to waveform frame
and store data in a text file.
Fig 6 shows comparing data measured by M and improved-M algorithm under the
motor no-load running condition. Data measured by M algorithm are scattered in the
three integer points, 27 to 29, while data measured by improved-M algorithm are
distributed in the decimal point from 27.2 to 28.8. According to the formula 1, the
sampling error is 0.17° when M algorithm is used. While improved-M algorithm is
adopted with the acceleration set to the maximum, in terms of formula 4, the sampling
error gets smaller with the speed increasing. This principle is supported by the data as
follows; the sampling error grows from 0.2 ° to 2.76*10-5 ° while the given motor
speed increases from 0 to 1 grids/2ms. According to this principle, we choose M
algorithm instead of improved-M algorithm when the speed of the motor is set to 0.
Improved-M algorithm is more accurate from theoretical error analysis and
experiments. In order to avoid floating point operations, the value of improved-M is
enlarged to 128 times.
Fig 7 shows the motor’s steady state effect chart motor at control frequency of 500HZ
motor homeostatic control diagram in control frequency of 500HZ, and Fig 8 shows
the control diagram at control frequency of 250HZ. When the setting speed value of
the motor control module is 6 grids/2ms in control frequency of 500HZ, actual speed
of the motor fluctuates between 5 grids and 7 grids, the mean value is 6.0031 and the
variance is 0.1941; at control frequency of 250HZ, actual speed of the motor
fluctuates between 4.5 grids and 7.5 grids, the mean value is 6.0587 and the variance
is 0.4885. Experiments prove that the control frequency increase can improve the
motor’s control accuracy. Feedback value of the motor participates directly in PI
closed loop operation without filter processing, thus fluctuation range of motor speed
is still large.
 Design of a FPGA-Based Multiple Motors Control System 565

Fig. 5. Small size soccer robot circuits

Fig. 6. Chart of M and improved-M algorithm

Fig. 7. Steady state effect with motor control frequency 500HZ

566 M. Yue, X. Rong, and Z. Fan

Fig. 8. Steady state effect with motor control frequency 250HZ

5 Conclusion
In this paper, a parallel design is proposed for multi-motor system, and it is
successfully used in the Robocup small size soccer robot system of Zhejiang
University. Closed loop control for BLDC motor is implemented by hardware
description language, which improves real time response and control accuracy of
system. Embedded CPU and motor control module can be downloaded into one
FPGA chip to compress the volume of circuits. Improved-M algorithm is given in
order to increase sampling accuracy under the condition of low line number encoder
and reduce hardware cost.
For further development, the effect of motor control can be improved by some
advanced algorithm such as fuzzy control algorithm, instead of PI algorithm used at
present which leads to larger speed overshoot.

References
1. Joo, J., et al.: Design of a DSP controller and driver for the power-by-wire driving system
with BLDC servo motor pump. In: 8th Electrical Engineering/ Electronics, Computer,
Telecommunications and Information Technology (ECTI) Association of Thailand -
Conference 2011, ECTI-CON 2011, May 17-19. IEEE Computer Society, Khon Kaen
(2011)
2. Sivaramakrishna, M., et al.: Development of pid controller algorithm over FPGA for motor
control in failed fuel location module in Indian fast reactors. In: 3rd International
Conference on Electronics Computer Technology, ICECT 2011, April 8-10. IEEE
Computer Society, Kanyakumari (2011)
3. Li, G., et al.: Study on speed and acceleration characteristics of 100 nm scale motion
platform driven by linear servo motors. In: 4th Conference on Application of Diamond and
Related Materials in China, CADRM 2010 and the 1st International Symposium on
Advances in Brazed Superabrasive Tools, ISABS 2010, August 19- 23. Trans. Tech.
Publications Ltd., Xiamen (2010)
 Design of a FPGA-Based Multiple Motors Control System 567

4. Castano, L.F., Osorio, G.A.: Design of a FPGA based position PI servo controller for a DC
motor with dry friction. In: 2011 7th Southern Conference on Programmable Logic, SPL
2011, April 13-15. IEEE Computer Society, Cordoba (2011)
5. Chen, Y., et al.: DSP-based real-time implementation of a neural network observer and
hybrid H adaptive controller for servo-motor drives. In: 27th Chinese Control Conference,
CCC, July 16-18. Inst. of Elec. and Elec. Eng. Computer Society, Kunming (2008)
6. Sun, Z., et al.: Design of Control System Based on Soccer Robot. In: International
Conference on Multimedia Technology, ICMT (2010)
7. Jae-Hun, J., et al.: Design of a DSP controller and driver for the power-by-wire driving
system with BLDC servo motor pump. In: 2011 8th International Conference on Electrical
Engineering/Electronics, Computer, Telecommunications and Information Technology,
ECTI-CON (2011)
8. Niasar, A.H., Moghbeli, H., Vahedi, A.: Implementation of Four-Switch Brushless DC
Motor Drive based on TMS320LF2407 DSP. In: IEEE International Conference on Signal
Processing and Communications, ICSPC 2007 (2007)
9. Wolf, D.F., et al.: An FPGA-Based Mobile Robot Controller. In: 3rd Southern Conference
on Programmable Logic, SPL 2007 (2007)
10. Charitkhuan, C., Bhuripanyo, J., Choomuang, R.: FPGA Implementation of Closed-loop
Control System for Small-sized RoboCup. In: IEEE Conference on Robotics, Automation
and Mechatronics (2006)
11. Wei, Z., et al.: FPGA implementation of closed-loop control system for small-scale robot.
In: Proceedings of the 12th International Conference on Advanced Robotics, ICAR 2005
(2005)
12. Ce, L., et al.: A Multiprocessor System for a Small Size Soccer Robot Control System. In:
4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA
2008 (2008)