2210 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO.

10, OCTOBER 2012

Design of Efficient Class-E Power Amplifiers for

Short-Distance Communications
Jun Tan, Student Member, IEEE, Chun-Huat Heng, Member, IEEE, and Yong Lian, Fellow, IEEE

Abstract—This paper presents a new Class-E power amplifier

(PA) with a -matching output network. The PA is targeted at
low output power wireless applications. Analytical formulae are
derived to aid the PA design, characterization and optimization.
A fully integrated 2.4-GHz PA for short distance communications
has been implemented in 0.13 m CMOS technology to verify the
proposed design method. The measured output power levels vary
from 3.2 to 5.7 dBm while achieving maximum overall efficiency
of 55%.
Index Terms—Circuit theory, class-E, efficiency, low-power, non-
linear circuits, power amplifier.

I. INTRODUCTION

L OW power transmitter design requires to optimize the

energy efficiencies of key building blocks including
VCO, mixer, and PA [1], [14]–[28]. Class-E PA is a nonlinear
switching type power amplifier which can ideally achieve 100%
efficiency. This high efficiency has spurred many research in-
terests on the design and analysis of Class-E PAs [1]–[20]. A
typical Class-E PA is shown in Fig. 1. The transistor serves as
an on/off switch. The reactance, , can be either capacitive
or inductive, depending on the desired output power level [1].
An output matching network is usually required to match the
antenna’s 50 resistance to a different value, . As the
matching network’s quality factor is normally limited, a
serial resonant filter composed of and is incorporated
to create a short circuit at the desired switching frequency, and
block all the undesired higher harmonic components to reach
the output. The Class-E PA requires the periodical steady-state
(PSS) waveform of to satisfy the following two criteria
[1]–[8], [20]: at the instance when the switch is turned on, (1)
the drain voltage of the switch equals to 0; and (2) its time
derivative also equals to 0, as shown in Fig. 1(b).
The Class-E PAs can be categorized into two types according
to the inductor’s function: Class-E PA with RF choke inductor
or with DC feed inductor [1]. For the former case, the RF choke
inductor maintains the DC biasing while behaves like an open
circuit at the desired output frequency. Design equations for
Manuscript received August 12, 2011; revised December 17, 2011; accepted
January 18, 2012. Date of publication April 03, 2012; date of current version
September 25, 2012. This work was supported by the Singapore Agency for Sci-
ence, Technology and Research (A*STAR), Science & Engineering Research
Council under Grant: 092-148-0066. This paper was recommended by Asso-
ciate Editor Y. Sun.
The authors are with Department of Electrical and Computer Engineering,
National University of Singapore, Singapore 117576 (e-mail: eletj@nus.edu.sg;
elehch@nus.edu.sg; eleliany@nus.edu.sg).
Digital Object Identifier 10.1109/TCSI.2012.2188951
Fig. 1. (a) Circuit diagram of the conventional Class-E PA. (b) PSS wave-form
of the drain voltage.
Class-E PA with RF choke are discussed comprehensively in
[5] and [6]. For the latter case, generalized design methodolo-
gies are presented in [1]–[4].
The existing works of Class-E PA mostly focus on designs
optimized at high output level, ranging from 23 to 33 dBm
[9]–[13]. If these PAs are used at lower output level, the overall
efficiency significantly degrades. In [14] the PA is built based on
injection-locked oscillators (ILO) which works in Class-E type.
However the power added efficiency (PAE) drops from 44.5%
to 30% when the output power level decreases from 11.1 dBm to
6 dBm. For most short distance communication, such as Blue-
tooth and ZigBee, the output power ranges between 0 to 10 dBm
[20]–[22]. Therefore, it is critical to look at the optimization of
class-E PA with high energy efficiency at low power levels.
To deliver low output power, the equivalent impedance
in Fig. 1(a) is usually chosen to be comparable to or even higher
than 50 [25]. If functions as RF choke, its impedance
should be much higher than to maximize the AC current
delivery to the output. This usually results in too high an in-
ductance value to be implemented practically on-chip. For ex-
ample at 2.4 GHz, of 33.2 nH is needed to have its reac-
tance 10 times larger than . Therefore, Class-E PA
with functions as RF choke is not suitable for output power
below 10 dBm. In addition, the series resonant network (
and ) needed for larger harmonic rejection also imposes in-
ductance constraint, which makes the on-chip integration diffi-
cult. It should be pointed out that due to low for high power

1549-8328/$31.00 © 2012 IEEE

TAN et al.: DESIGN OF EFFICIENT CLASS-E POWER AMPLIFIERS 2211

Fig. 3. Circuitry of the proposed Class-E PA.

Fig. 2. Circuit Model of the Class-E PA. (a) Conventional Structure. (b) Pro-
posed Structure.

applications, the inductance constraint discussed above is much

relaxed.
To circumvent this inductance constraint for low power appli-
cations, we present a new Class-E PA architecture in this paper
to facilitate fully integrated PA solution. The paper is organized
as follows. In Section II, we present the circuitry of the pro-
Fig. 4. Simplified circuit model.
posed PA and its qualitative analysis. The analytical equations
are derived in Section III to characterize the proposed Class-E
PA. Section IV presents the analysis and design methodologies drain parasitic capacitance of switching transistor can be incor-
for the proposed PA. A design example of a 2.4-GHz PA is pre- porated into , whereas the pad parasitic can be merged with
sented in Section V to verify our circuitry and theories, and is . Therefore, the circuit shown in Fig. 3 can be a compact
then followed by the conclusion in Section VI. representation of the actual implemented PA with all parasitic
taken into considerations. As the proposed architecture is dif-
II. THE PROPOSED CLASS-E PA
ferent from the existing class-E PA, a new set of design formulae
The inductance constraint imposed by can be relaxed needs to be derived for optimization purpose.
if it functions as DC feed [1] instead of RF choke. To ob- As there are now a total of six reactive elements ( , , and
viate the need for large inductance in series resonant network to ), it offers more design freedoms in PA optimization
, different topology has to be employed. Fig. 2 as compared with the original architecture. The detailed com-
illustrates our proposed idea which considers impedance net- ponent selection will be discussed next.
work right after the impedance . Conventionally, only series
resonant network is used to improve the harmonic rejection. For III. ANALYTICAL DESIGN EQUATIONS FOR THE PROPOSED
Fig. 2(a) with large (required for low output power), the re- CLASS-E PA
jection ratio is directly related to , where The Class-E PA conditions are defined solely in the time do-
is the desired output frequency, and is the harmonic main. The PSS solutions are needed to design the PA. The fol-
generated by Class-E PA . To improve the rejection, we lowing assumptions are made before we derive the design equa-
have no choice but to increase and thus . For Fig. 2(b), tions.
a parallel network is added. Now the rejection ratio would 1) The resistor is the only component which dissipates
depend on the ratio of power. The transistor serves as an ideal switch with an ‘on’
to for . Better resistance of 0 and ‘off’ resistance of infinity.
harmonic rejection would require and 2) The current waveform of the inductor is sinusoidal
, which implies a capacitive network (high- assumption).
and inductive networks respectively. Due to presence of , The second assumption implies that the output network has a
it relaxes the requirement on to achieve same harmonic high harmonic rejection and thus high quality factor. This is
rejection. This will reduce the and allow better integration. achieved through and in our architecture. Similar sim-
The proposed new circuitry of the Class-E PA is shown in plifications have been made in [1], [4] and [5] as well to obtain
Fig. 3. The inductor is chosen as DC feed. The capacitor explicit solutions.
functions as which provides alternative current path for With the above approximations, a simplified circuit model is
higher harmonics. The inductor and the capacitor form shown in Fig. 4. The current of the inductor is denoted by
an impedance matching network which transforms the antenna . The ideal switch is driven by an input square wave, ,
resistance to at the desired output frequency . The with a period of . The switch is turned off from 0 to , and
inductor also functions as which helps reducing higher turned on from to . The ratio of to is defined as the
harmonics current component. Unlike conventional structure, on time duty cycle . Let denote the angular frequency of
the harmonic rejection is now provided by both and . This the driving voltage of the switch, which satisfies: .
allows smaller to be chosen for on-chip integration. It should The output current represents the current of the inductor
be pointed out that the proposed architecture has merged the in Fig. 3, and is given as
harmonic rejection and impedance matching into a -network
consisting of , and . For the proposed architecture, the (1)
2212 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012

where is the amplitude of the current and is the phase dif- When the switch is on , the voltage is pulled to
ference between the output current and the input voltage. zero. The state equations become
Suppose the supply voltage , the angular frequency of
the driving signal , and the on time duty cycle are known. (11)
There are totally six unknown variables in the circuitry in Fig. 4,
namely , , , , , and . To determine these variables, (12)
six independent equations are required. The Class-E conditions
define two equations as below [1]–[8], [20] The general solutions of the ODE set of (8), (9) and (10) are
given below when
(2)
(3)
(13)
where is the PSS waveform of the switch voltage with a
period of . Therefore, four additional equations are required
to solve all the six unknowns. We define four design variables
, , and , which are depicted in (4) to (7) (14)

(4)
(15)
(5)
The variable in (13) and (15) is defined as
(6)
(16)
(7)
When , the waveforms of and can be ob-
tained from the ODE set of (11) and (12). The initial conditions
where is the total equivalent capacitance at the switch node,
of and are computed from (14) and (15). The so-
is related to the capacitance ratio of and , is the ratio of
lutions are given by
the parallel capacitance to , and is the normalized fre-
quency defined by and . These four new variables would
(17)
be the key design variables. Once determined, the actual compo-
nent values of and can be determined subsequently.
The remaining two unknown variables of , and are derived (18)
next.
When the switch is off , the state equations of the The three variables of , and are determined by the
system are given by the ordinary differential equations (ODE) boundary conditions of the voltage waveform of during
of (8), (9) and (10). . The initial condition of is given by .
The voltage and its derivative at are defined by the
(8) Class-E conditions in (2) and (3). As a result, by substituting
depicted by (13) into these three equations, , and
(9) may be obtained by solving the linear algebraic equations (AE)
shown at the bottom of the page. The detailed expressions of
the sub-functions of and are provided in
(10)
Appendix B.

(19)

(20)

(21)
TAN et al.: DESIGN OF EFFICIENT CLASS-E POWER AMPLIFIERS 2213

The PSS conditions require all the waveforms to be periodical TABLE I

with a cycle of . This implies that , and satisfy the NORMALIZED COMPONENT VALUES OF THE PROPOSED PA
following three conditions: , ,
and . From (13), (14), (17) and (19)–(21), it
can be seen that the first two conditions are already satisfied for
arbitrary . By substituting given by (15) and given
by (18) into the third condition, the required phase difference
can be derived by solving the AE. The result is given by (22).
where and can be calculated from (24) and
The detailed expressions of the sub-function and
(36)–(39).
are given in Appendix B
To summarize the above analysis, the component values of
the proposed PA are listed in Table I. Note the normalized ca-
(22) pacitance and inductance are defined as

The constant is related to the DC component of , and it (28)

is relatively trivial in characterizing the PA. Its detailed expres- (29)
sion is omitted here.
From the above analysis it can be seen that by choosing , The output power of the PA can be computed by averaging
, , and as free design variables, all the six unknowns in the current through as follows:
Fig. 4, namely , , , , , and can be solved explicitly
from (4)–(7), (16), (21), and (22). The PSS waveforms of the
(30)
system are also determined by (13)–(22).
The output network composed of and are determined
from the output current and the voltage waveform of The function is described by (40) in Appendix A.
. The current through the inductor (in Fig. 3) should
be equal to (in Fig. 4). As is a periodical function, IV. ANALYSIS AND DESIGN OF FULLY INTEGRATED
it can be expanded into Fourier series CLASS-E PA
In this section, we discuss the design perspectives of the pro-
posed Class-E PA. Relationships between the design variables
and the PA’s performance are briefly studied. Simplified design
equations are provided to approximate the PA’s output power
where and are the voltage amplitude and phase offset
and the values of and . We also present the methodolo-
at the harmonic frequency respectively. At the fundamental
gies on the selection of the component values of the proposed
frequency , the equivalent output impedance seen from the
PA to meet the integration criteria.
left of the output current source in Fig. 4 is
The PA’s output power is given by (30). It scales linearly with
and the square of the supply voltage. The output power
(24)
is also related to the design parameters of and . By setting
the normalized equivalent capacitance to be 10 mF, the
where and are the real and imaginary parts relationships between the output power and the normalized fre-
of the impedance . The expressions to compute and quency under different duty cycle are shown in Fig. 5. The
are derived from PSS waveform of . The detailed formulae output power decreases with larger and smaller . As illus-
are given by (36)–(39) in Appendix A. trated, the desired output power level has strong dependencies
From the circuit in Fig. 3, it can be seen that the equivalent on . For the targeted moderate and low output power ( 10
output impedance seen from the left of the inductor at dBm), of 0.4 or 0.5 can be chosen.
the fundamental frequency can be calculated by The current of the DC feed inductor is also plotted in
Fig. 6. When approaches 0, behaves like RF choke and ex-
hibits almost constant DC current. As increases, functions
as DC feed inductor and it exhibits higher AC current swing.
(25) The current through the switch when it is turned on can be com-
puted by the summing the currents through and . Its wave-
form is plotted in Fig. 7. The duty cycle is chosen to be 0.5 and
By equating (24) and (25), the component values of and
equals to 10 mF. The current through the switch increases
can be obtained from
gradually from 0, which verifies the soft switching feature of the
Class-E PA [20]. The switch transistor should be large enough
(26) such that the voltage drop across it is close to zero.
The PSS waveform of the switch voltage is plotted in
(27) Fig. 8. The supply voltage is set to 1-volt. and are both
chosen to be 0.3. The waveform deviates gradually from the
2214 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012

Fig. 5. Output power of the PA versus the normalized frequency . The supply Fig. 8. PSS waveform of voltage when the switch is off. .
voltage is set to 1-Volt. The switch duty cycle changes from 0.4 to 0.6.
.
TABLE II
POLYNOMIAL COEFFICIENTS TO ESTIMATE OUTPUT POWER

the higher harmonic components to ground. Hence, the high-

Fig. 6. Current waveform of the inductor
approximation is more valid for smaller . If is chosen to be
0.3, simulation results indicate that it is proper to choose
for and .8 for .
Although all the explicit equations have been derived in the
previous section, the equations for computing the PA’s output
power and the component values of and are quite com-
plicated. Simplified design equations are provided here to ease
computation. Cubical polynomial approximations are used to
compute these variables. Least squares fitting techniques are
. . . used to derive all the polynomial coefficients. The errors caused
by these approximations are below 3%. The PA’s output power
can be estimated by the following equation for .

(31)

The polynomial coefficients of for different

duty cycle are summarized in Table II.
The inductance value depicted by (26) is related to ,
, , , and . To simplify analysis, and are both fixed to
0.3. The antenna resistance is assumed to be 50 . The nor-
malized inductance is plotted in Fig. 9. We approximate its
value by a cubical polynomial of as shown in (32).

(32)

The fitting parameters of when is equal to 10, 15 and

20 mF are listed in Tables III and IV.
Fig. 7. Current of the switch when it is turned on. . . The capacitance depicted by (27) is related to , ,
, and . Its relationships with and are plotted in Fig. 10.
The variable is set to be 0.3. A cubical polynomial approxi-
Class-E requirements with larger . This is because the error mation is provided to estimate this capacitance, i.e.
caused by the high- assumption is larger when increases. A
smaller value implies larger value of , which helps to divert (33)
TAN et al.: DESIGN OF EFFICIENT CLASS-E POWER AMPLIFIERS 2215

TABLE V
THE FITTING PARAMETERS TO COMPUTE ( , )

TABLE VI
THE FITTING PARAMETERS TO COMPUTE ( , )

Fig. 9. The normalized inductance value versus for different

values. . and 0.5.

TABLE III TABLE VII

FITTING PARAMETERS TO COMPUTE ( , ) COMPONENT VALUES OF THE PA

Step 1) Choose the parameters of , , and according

TABLE IV
FITTING PARAMETERS TO COMPUTE
Fig. 10. The normalized capacitance value
values. . and 0.5.
The fitting parameters of are listed in Tables V and VI.
The design procedure of the PA is summarized below.
to the required targeted power and supply voltage.
Compute the inductance value accordingly.
Step 2) Choose the parameters of and to determine ,
( , ) and .
Step 3) Compute the output network of and .
Step 4) Ensure all the component values to be within the
practical range for on-chip integration. Otherwise go
back to Step 1 to adjust the design variables.
To illustrate the advantage of our proposed circuitry, we
present a design example of a 433-MHz Class-E PA for on-chip
integration with 3 dBm output power. Normally the low-power
PAs at such low frequency range require inductance values
larger than 40 nH, making it impractical to be implemented
on-chip due to huge area penalty and poorer quality factor
[27], [28]. Our proposed circuitry can potentially overcome
such issues and provide full chip solution even for such a
low operating frequency. The simplified design equations are
adopted to design this PA. The on time duty cycle is chosen
to be 0.4, and the normalized frequency is selected to be 1.55
to reduce the output power level and the required inductance
values. The values of and are both chosen to be 0.3. The
supply voltage is set to be 0.5-V. From (31), it can be derived
that should be 13.2 mF such that the output power is 3
dBm with 0.5-V supply voltage. In order to use the polynomial
approximation formulae to compute and , we round
up to 15 mF resulting in an output power of 2.28 mW.
The values of , , and can be obtained from
versus for different the equations depicted in Table I. The values of and
are obtained from (32) and (33). The unnormalized component
values of the PA are summarized in Table VII. The simulated
PSS waveform of the switch voltage is plotted in Fig. 11. It can
be seen that the waveform satisfies the Class-E requirements
2216 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012

used as the pre-driver, the inverter itself consumes high power

because of the large loading capacitance, hence degrading the
overall efficiency. To reduce the power consumption, an induc-
tively biased NFET inverter composed of and is used as
the pre-driver. The inductance helps to tune out the gate ca-
pacitance of . The transistor is designed to have a small
aspect ratio m m to reduce the loading capacitance
of the previous stage. A small sized CMOS inverter is used to
drive the gate of . The RF tone is generated from an on-chip
VCO locked by a PLL. The pre-driver and the PA share the same
power supply with a nominal voltage of 0.5 V and the CMOS
inverter works with a supply voltage of 1.2 V. When the gate
driving voltage of is high, is pulled down to a low voltage
closed to 0. Hence, the transistor is turned off. When the
driving voltage of is low, is determined by the transient
Fig. 11. The simulated PSS voltage waveform of the switch. The time is nor- waveform defined by and the total capacitances at the drain
malized to one period. node of .
The analytical formulae and waveforms derived in
Sections III and IV are based on ideal devices. When the
PA is implemented in CMOS as depicted in Fig. 12, simula-
tions are needed to characterize the circuit performance with
lossy elements and none ideal driving voltage of the switch. The
simulated PSS waveforms of and the channel current
of are plotted in Fig. 13(a) with a supply voltage of
0.5 V. Because has a large aspect ratio, it is approximately
turned off when is below the threshold voltage , and
turned on when is larger than . The on duty cycle is
about 40%. The normalized power loss and
accumulated power loss are defined in (34)
Fig. 12. Circuitry of the proposed 2.4-GHz PA.
and (35), and their waveforms are plotted in Fig. 13(b). It can
be seen that there are two positive peaks in the waveform of
well. The maximum inductance required is only about 10.2 nH . The first peak is due to the reason that
facilitating a fully on-chip solution. is turned on slightly before reaches zero. The second peak
is because of the finite ‘on’ resistance of . The energy
V. CIRCUIT DESIGN AND MEASUREMENT RESULTS loss from the switching transistor accounts for 13.6% of
In this section, we present the design and measurement results the total power of the entire PA (including the PA-stage and
of a 2.4-GHz PA with output power levels around 0 dBm. This pre-driver).
PA is implemented in 0.13 m CMOS technology. The die of
the PA is encapsulated in a Quad-Flat-No-leads (QFN) package. (34)
The design parameters are chosen as: , ,
and . With this setting, the output power
is about 2.5 mW with 0.5-volt supply voltage if all the compo- (35)
nents are ideal. This guarantees the output power to be close to 0
dBm by assuming an overall energy efficiency of 50% when the
PA is implemented in CMOS. The circuitry of the PA and all the As the pre-driver is an indispensible stage, when we refer to
component values are shown in Fig. 12. The switching transistor ‘PA’ in the rest of the paper, both the pre-driver and PA stage are
is designed to have a large W/L ratio m m to included. The microphotograph of the PA is shown in Fig. 14.
reduce the ‘on’ resistance. All the parasitic capacitances at the The core area is 0.5 mm and the total area with bonding PADs
drain terminal of are lumped into the parallel capacitance is 1.0 mm . It should be noted that the input port of the PA
. Two identical output pads are implemented at the output (composed of the PA-stage and the pre-driver) is mainly the
node. Therefore, two bonding wires in parallel connect the PA’s gate capacitance of instead of being matched to 50 . It
output to the package lead. This reduces the influences of the is driven by a small sized CMOS inverter as shown in Fig. 12.
bonding wire inductance by half. The output node of the PA is The input power of the PA is mainly caused by the signal
DC biased to ground potential without any need of DC block ca- feed through between the gate and drain nodes of through
pacitor or other external components. The parasitic capacitances the of the transistor. Due to the small size of , is
of the output pads are lumped into . The gate capacitance of quite small. Simulation results verify that the power gain of the
the switching transistor is large for its relatively large aspect total PA is larger than 20 dB when V, implying the
ratio. If a CMOS inverter composed of both NFET and PFET is differences between PE and PAE is less than 0.5%. Although
TAN et al.: DESIGN OF EFFICIENT CLASS-E POWER AMPLIFIERS
Fig. 13. Simulated PSS waveforms in one complete cycle of (a) ,
. (b) Normalized power loss and accumulated power loss of .
Fig. 14. The die photo of this work.
PAE is a good definition for stand-alone PAs with 50 input
impedance matching, overall PE is a better indication to char-
acterize integrated PA from the system point of view [20]. We
therefore use PE to evaluate the performance of the PA. Only
the component at the fundamental frequency is taken into ac-
count when computing the output power and efficiency. The re-
sults are shown in Fig. 15. The input frequency is set to be 2.45
GHz. The measured power levels and efficiencies are slightly
lower than the simulation prediction. This may be caused by the
process variation and imperfect matching and excessive losses
from the testing PCB. When the supply voltage varies from 0.45
2217
Fig. 15. The simulated and measured results of the output power and overall
efficiency of the PA (pre-driver and PA-stage) at frequency of 2.45 GHz.
and
Fig. 16. The simulated and measured results of the output power and effi-
ciency of the PA (pre-driver and PA-stage) under different frequencies. The
supply voltage is set to 0.5 V.
to 0.8 V, the measured output power level ranges from 1 to 3.7
mW, and the overall PE is from 53.5% to 55%. According to
simulation, the PA’s pre-driver consumes about 2% to 3% of the
total power. Therefore, it has no significant impact on the overall
performance. Fig. 16 shows the simulated and measured results
under different frequencies. The measurement frequency is con-
fined to 2.1 2.5 GHz due to the limited tuning range of the
on-chip VCO. According to the measurement, in the 300 MHz
bandwidth from 2.2 to 2.5 GHz the PE variation is less than 2%
and the output power level changes less than 5%. This implies
the PA can operate in a wide frequency range. The measured
2nd and 3rd order harmonics are less than 25.5 and 41 dBc
respectively. Therefore, the energy losses at higher harmonics
are negligible.
We also compare our results with other reported 2.4-GHz
PAs. The core area of this PA is comparable with the existing
integrated low-power PAs reported in [17], [24], and [25]. The
Class-E PA in [17] is targeted at higher power levels ( 6 dBm).
Smaller inductances can therefore be used, which reduces the
on-chip area. The ILO PA in [24] and the low-power Class-C
2218 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012

TABLE VIII
PERFORMANCE COMPARISON WITH EXISTING PA
(38)

(39)

(40)

APPENDIX B
SUB-FUNCTIONS

Unless stated, all designs are implemented in CMOS technology and use
on-chip spiral inductors.
SiGe technology . Bonding wire inductors . Estimated core area
Only the DC feed inductor is integrated, lacking the output filter.
Off-chip matching network/inductors required.

PA in [25] only require one inductor, resulting in smaller area.

However, their maximum PEs are worse as compared to the
Class-E PAs in [14]–[17] and this work. As pointed out earlier,
most reported Class-E PAs are not optimized for low-power ap-
plications, and the measurement results are usually limited to
10 dBm and above. However, due to the characteristics of these
Class-E PAs, the efficiencies are expected to deteriorate further
with lower output power. As illustrated in Table VIII, the power
efficiencies for [14]–[16] worsen when the output power levels
drop below 10 dBm. Although high PE of 52.5% is achieved
in [17], only the DC feed inductor is integrated on-chip, lacking
the output filter for harmonic suppression. Our structure exhibits
superior efficiency at low output power levels without any need
of external components. The achieved peak PE of 55% is at
least 10% better than other types of low-power PAs reported
in [24]–[26].

VI. CONCLUSION
In this paper, we present a new circuitry of Class-E PA which
is optimized for delivering low output power level with high ef-
ficiency and allows for fully integrated solution. Explicit design
equations are derived to characterize the PA. As a proof of con-
cept, a 2.4-GHz Class-E PA is implemented in 0.13 m CMOS
technology. Measurement results show the PA can deliver an
output power level from 3.2 to 5.7 dBm with maximum effi-
ciency of 55% including the auxiliary pre-drive stage.

APPENDIX A
DETAILED FUNCTION EXPRESSIONS
The required functions for deriving the output network of
and are given by (36)–(39). The function which defines the
output power of the PA is given by (40). The sub-functions of
, , and in (36)–(40) are provided
in Appendix B.

(36)

(37)
TAN et al.: DESIGN OF EFFICIENT CLASS-E POWER AMPLIFIERS
ACKNOWLEDGMENT
The authors would like to thank Dr. Yuan Gao from Singapore
Institute of Microelectronics for his help in chip assembly.
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Jun Tan (S’06) received the B.Sc. and M.Sc. degrees
in electrical engineering from Fudan University,
Shanghai, China, in 2001 and 2004, respectively. He
has been with the National University of Singapore
since 2006, where he is currently working towards
the Ph.D. degree.
He was with Intel Product, Shanghai, China, in
2004. He worked at Agilent Technology, Shanghai,
China from 2005 to 2006. His research interests
include analog and RF circuit design for low-power
wireless communications.
Chun-Huat Heng (S’96–M’04) received the B.Eng.
and M.Eng. degrees from the National University of
Singapore in 1996 and 1999, respectively, and the
Ph.D. degree from the University of Illinois at Ur-
bana-Champaign, in 2003.
He has been working on CMOS integrated circuits
involving synthesizer, delay-locked loop, and trans-
ceiver circuits. From 2001 to 2004, he was with Wire-
less Interface Technologies, which was later acquired
by Chrontel. Since 2004, he has been with the Na-
tional University of Singapore. He has received NUS
Annual Teaching Excellence Award in 2008.
Dr. Heng is currently serving as an Associate Editor for IEEE TRANSACTION
ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, and a Technical Program
Committee member for Asian Solid-State Circuits Conference.
Yong Lian (M’90–SM’99–F’09) received the B.Sc
degree from the College of Economics and Manage-
ment of Shanghai Jiao Tong University in 1984, and
the Ph.D. degree from the Department of Electrical
Engineering, National University of Singapore, in
1994.
He worked in industry for 9 years and joined the
National University of Singapore in 1996, where he
is currently the Provost’s Chair Professor and Area
Director for IC and Embedded Systems in the Depart-
ment of Electrical and Computer Engineering. His re-
search interests include biomedical circuits and systems and signal processing.
He is author or coauthor of over 160 scientific publications in peer reviewed
journals, conference proceedings.
2220 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 10, OCTOBER 2012
Dr. Lian is the recipient of the 1996 IEEE CAS Society’s Guillemin–Cauer
Award for the best paper published in the IEEE TRANSACTION ON CIRCUITS
AND SYSTEMS—II: EXPRESS BRIEFS, the 2008 Multimedia Communications
Best Paper Award from the IEEE Communications Society for the paper
published in the IEEE TRANSACTIONS ON MULTIMEDIA, winner of the 47th
DAC/ISSCC Student Design Contest (as a Ph.D. Advisor), the Best Student
Paper Award in the ICME’07 (as a M.Eng. Advisor), 2011 IES Prestigious
Engineering Achievement Award, and many other awards. He teaches VLSI
Digital Circuit Design, Integrated Digital Design, and Emerging Technologies
in Electrical Engineering. He received 2009 and 2010 University Annual
Teaching Excellent Awards and many other teaching awards. Dr. Lian is the
Founder of ClearBridge VitalSigns Pte. Ltd, a start-up for wireless wearable
biomedical devices. Dr. Lian is the Editor-in-Chief of the IEEE TRANSACTION
ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS (TCAS-II), a Steering
Committee Member of the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS
AND SYSTEMS (TBioCAS), the Chair of DSP Technical Committee of the IEEE
Circuits and Systems (CAS) Society, and a Member of the IEEE Medal for In-
novations in Healthcare Technology Committee. He served as Associate Editors
for IEEE TCAS-I, TCAS-II, TBioCAS, and journal of Circuits Systems Signal
Processing (CSSP) in the past 10 years, and was the Guest Editor for 7 Special
Issues in TCAS-I, TBioCAS, and CSSP. He was the Vice President for Asia
Pacific Region of the IEEE CAS Society from 2007 to 2008, AdComm Member
of the IEEE Biometrics Council (2008–2009), CAS Society Representative
to the BioTechnology Council (2007–2009); Chair of the BioCAS Technical
Committee of the IEEE CAS Society (2007–2009), Member of the Prize Paper
Award Subcommittee of the IEEE CAS Society (2007 and 2009), Member of
the Chapter of the Year Award Subcommittee of the IEEE CAS Society (2007),
Member of the Regional Activities and Membership Development Division of
the IEEE CAS Society (2007), the Distinguished Lecturer of the IEEE CAS
Society (2004–2005), Member of Chapter and Regional Activity Committee
of the IEEE Education Society. Dr. Lian is the Founder of the International
Conference on Green Circuits and Systems (ICGCS), Asia Pacific Conference
on Postgraduate Research in Microelectronics and Electronics (PrimeAsia),
and IEEE Biomedical Circuits and Systems Conference (BioCAS).