Analog to digital converter

Delta-sigma (ΔΣ; or sigma-delta, ΣΔ) modulation is a method for encoding analog signals into digital
signals as found in an analog-to-digital converter (ADC). It is also used to convert high bit-count, low-
frequency digital signals into lower bit-count, higher-frequency digital signals as part of the process
to convert digital signals into analog as part of a digital-to-analog converter (DAC).

In a conventional ADC, an analog signal is sampled with a sampling frequency and

subsequently quantized in a multi-level quantizer into a digital signal. This process introduces
quantization error noise. The first step in a delta-sigma modulation is delta modulation. In delta
modulation the change in the signal (its delta) is encoded, rather than the absolute value. The result
is a stream of pulses, as opposed to a stream of numbers as is the case with pulse code
modulation (PCM). In delta-sigma modulation, accuracy of the modulation is improved by passing
the digital output through a 1-bit DAC and adding (sigma) the resulting analog signal to the input
signal (the signal before delta modulation), thereby reducing the error introduced by the delta-
modulation.

Both ADCs and DACs can employ delta-sigma modulation. A delta-sigma ADC first encodes an analog
signal using high-frequency delta-sigma modulation, and then applies a digital filter to form a higher-
resolution but lower sample-frequency digital output. A delta-sigma DAC encodes a high-resolution
digital input signal into a lower-resolution but higher sample-frequency signal that is mapped
to voltages, and then smoothed with an analog filter. In both cases, the temporary use of a lower-
resolution signal simplifies circuit design and improves efficiency.

Primarily because of its cost efficiency and reduced circuit complexity, this technique has found
increasing use in modern electronic components such as DACs, ADCs, frequency
synthesizers, switched-mode power supplies and motor controllers.[1] The coarsely-quantized output
of a delta-sigma modulator is occasionally used directly in signal processing or as a representation
for signal storage. For example, the Super Audio CD (SACD) stores the output of a delta-sigma
modulator directly on a disk.

One of the more advanced ADC technologies is the so-called delta-sigma, or ΔΣ (using the proper
Greek letter notation). In mathematics and physics, the capital Greek letter delta (Δ)
represents difference or change, while the capital letter sigma (Σ) represents summation: the adding
of multiple terms together. Sometimes this converter is referred to by the same Greek letters in
reverse order: sigma-delta, or ΣΔ.

In a ΔΣ converter, the analog input voltage signal is connected to the input of an integrator,
producing a voltage rate-of-change, or slope, at the output corresponding to input magnitude. This
ramping voltage is then compared against ground potential (0 volts) by a comparator. The
comparator acts as a sort of 1-bit ADC, producing 1 bit of output (“high” or “low”) depending on
whether the integrator output is positive or negative. The comparator’s output is then latched
through a D-type flip-flop clocked at a high frequency, and fed back to another input channel on the
integrator, to drive the integrator in the direction of a 0 volt output. The basic circuit looks like this:
The leftmost op-amp is the (summing) integrator. The next op-amp the integrator feeds into
is the comparator, or 1-bit ADC. Next comes the D-type flip-flop, which latches the
comparator’s output at every clock pulse, sending either a “high” or “low” signal to the
next comparator at the top of the circuit. This final comparator is necessary to convert the
single-polarity 0V / 5V logic level output voltage of the flip-flop into a +V / -V voltage
signal to be fed back to the integrator.
If the integrator output is positive, the first comparator will output a “high” signal to the D
input of the flip-flop. At the next clock pulse, this “high” signal will be output from the Q
line into the noninverting input of the last comparator. This last comparator, seeing an
input voltage greater than the threshold voltage of 1/2 +V, saturates in a positive direction,
sending a full +V signal to the other input of the integrator. This +V feedback signal tends
to drive the integrator output in a negative direction. If that output voltage ever becomes
negative, the feedback loop will send a corrective signal (-V) back around to the top input
of the integrator to drive it in a positive direction. This is the delta-sigma concept in action:
the first comparator senses a difference (Δ) between the integrator output and zero volts.
The integrator sums (Σ) the comparator’s output with the analog input signal.
Functionally, this results in a serial stream of bits output by the flip-flop. If the analog input
is zero volts, the integrator will have no tendency to ramp either positive or negative,
except in response to the feedback voltage. In this scenario, the flip-flop output will
continually oscillate between “high” and “low,” as the feedback system “hunts” back and
forth, trying to maintain the integrator output at zero volts:
If, however, we apply a negative analog input voltage, the integrator will have a tendency
to ramp its output in a positive direction. Feedback can only add to the integrator’s ramping
by a fixed voltage over a fixed time, and so the bit stream output by the flip-flop will not be
quite the same:

By applying a larger (negative) analog input signal to the integrator, we force its output to
ramp more steeply in the positive direction. Thus, the feedback system has to output more
1’s than before to bring the integrator output back to zero volts:
As the analog input signal increases in magnitude, so does the occurrence of 1’s in the
digital output of the flip-flop:

A parallel binary number output is obtained from this circuit by averaging the serial stream
of bits together. For example, a counter circuit could be designed to collect the total
number of 1’s output by the flip-flop in a given number of clock pulses. This count would
then be indicative of the analog input voltage.
Variations on this theme exist, employing multiple integrator stages and/or comparator
circuits outputting more than 1 bit, but one concept common to all ΔΣ converters is that
of oversampling. Oversampling is when multiple samples of an analog signal are taken by
an ADC (in this case, a 1-bit ADC), and those digitized samples are averaged. The end
result is an effective increase in the number of bits resolved from the signal. In other
words, an oversampled 1-bit ADC can do the same job as an 8-bit ADC with one-time
sampling, albeit at a slower rate.
ADCs can be described as either Nyquist-rate or oversampled converters. In my previous
article, Deciphering Resolution and Sampling Rate, I explained how sampling in the
Nyquist-rate family of converters works and one of the key concepts this type of converter
relies upon, the Nyquist Criterion.
The Delta-Sigma ADC works a little differently from the Nyquist-rate ADC. It relies upon
oversampling and noise shaping to achieve high-resolution conversions.
My previous article, Understanding the Successive Approximation Register ADC,
demonstrates a weakness of this Nyquist-rate architecture: Its accuracy and linearity, and
thus its maximum effective resolution, are limited by the imperfections of analog
components such as the DAC.
The oversampled family of converters, to which the Delta-Sigma ADC belongs, aims to
overcome the limitations of Nyquist-rate converters. The Delta-Sigma ADC consists of a
modulator, a filter, and a decimator as shown below. Delta-Sigma ADCs are approximately
75% digital.
By introducing more complex digital circuitry and oversampling the data, they attempt to
reduce the requirements for accurate analog components that can be considered the limiting
factor in other ADC architectures.

For the
benefit of software and hardware developers whose experience has been mainly in the digital
domain, we provide a review of the basics of sigma delta (SD) analog to digital converters
(ADCs). It will be useful to a designer as a review, whether implementing an ADC on a board to
work with associated digital components, or in a more complex SoC environment. We explain the
functioning of all components by using an analog input example. Many different parameters used
with respect to sigma delta ADCs are also explained. (This article is meant to be read as a
companion to Mixed Signal Verification of Sigma Delta ADCs in an SoC environment.

An SD-ADC has a modulator and a digital filter (also known as decimation filter) as shown
in Figure 1. A modulator converts the input analog signal into digital bit streams (1s and 0s). One
can observe a bit, either 1’b1 or 1’b0 coming at every clock edge of the modulator.

The decimation filter receives the input bit streams and, depending on the over sampling ratio
(OSR) value, it gives one N-bit digital output per OSR clock edge. For example, if we consider
OSR to be 64, then the Filter gives one N-bit output for every 64 clock edges (64 data outputs of
the modulator). Here N is the resolution of the SD ADC.
 Click on image to enlarge.

Figure 1: Signal flow diagram in a first order Sigma Delta ADC

How a modulator works

The working of a modulator can be explained using a conversion example. In Table 1 the
headings X, B, C, D, and W correspond to points in the signal path of the block diagram
in Figure 2. For this example, the input X is a DC input of 3/8. The resultant signal at each point
in the signal path for each signal sample is shown in Table 1.

Note that a repetitive pattern develops every sixteen samples, and that the average of the signal
W over samples 1 to 16 is 3/8, thus showing that the feedback loop forces the average of the
feedback signal W to be equals to the input X.

Figure 2: First order sigma delta block diagram