UNITED INTERNATIONAL UNIVERSITY (UIU)

Dept. Of Electrical & Electronic Engineering (EEE)

Exam: Midterm, Trimester: Fall, Year: 2016
Course: EEE 441 (Sec – A), Title: VLSI Design
Marks: 60, Time: 1:45 Hour

There are 5 questions. Answer any 4. Figures in the right-hand margin indicate full marks.

1. a) Draw the symbolic diagram of a serial/parallel multiplier for 4-bit slices with all the [4]
connections shown in class.

b) Calculate the clock frequency and latency of the design in Q1(a) given the delay [4]
information below:
2-input AND gate = 150ps Flip-flop setup = 100ps
FA = 330ps Flip-flop hold = 100ps

c) Show the data flow of the serial/parallel multiplier at each step to multiply 1011 with [7]
0101

2. a) From the following report generated by RTL Compiler calculate [7]

i. total number of Instances,
ii. percentage (%) of Area used and
iii. percentage (%) of Internal Power consumed
by sequential cells and combinational cells

rc:/> report gates -power

=====================================================
Leakage Internal
Gate Instances Area Power (nW) Power (nW)
------------------------------------------------------------------------------------------
ADDFX1 6 419.126 21.794 73426.384
ADDHXL 1 36.590 1.424 2476.158
AOI22X1 16 266.112 5.126 36422.124
DFFHQX1 1 53.222 1.877 9146.022
DFFTRX1 15 848.232 22.955 197777.220
DFFTRXL 9 508.939 13.197 111296.336
DFFX1 1 56.549 1.505 6822.529
INVX1 1 6.653 0.135 0.000
INVXL 15 99.792 1.708 10005.965
MX2X1 1 26.611 1.307 0.000
NAND2XL 1 9.979 0.217 442.351
NOR2BX1 1 13.306 0.485 0.000
OAI21XL 2 26.611 0.468 1037.529
OAI2BB1X1 1 16.632 0.602 904.414
OAI2BB2X1 2 46.570 1.258 4361.223
-------------------------------------------------------------------------------------------
Total 73 2434.925 74.058 454118.257
2. b) Draw the path from Start-point to End-point showing delay in each part of the path [8]
from the report generated by RTL Compiler below:

rc:/> report timing

===========================================================
Pin Type Fanout Load Slew Delay Arrival
(fF) (ps) (ps) (ps)
-----------------------------------------------------------------------------------------------------
(clock clk) launch 0R
clk1_reg[1]/CK 100 0R
clk1_reg[1]/QN DFFTRXL 3 10.6 138 +568 568 F
g1082/S0 +0 568
g1082/Y MX2X1 19 82.2 1037 +790 1359 R
g1081/A +0 1359
g1081/Y INVX1 16 71.9 585 +524 1883 F
g1072/B0 +0 1883
g1072/Y AOI22X1 1 2.6 225 +268 2151 R
g1071/A +0 2151
g1071/Y INVXL 1 2.2 68 +56 2207 F
f1_reg[4]/D DFFTRX1 +0 2207
f1_reg[4]/CK setup 100 +393 2600 R
------------------------- --------------------------------
(clock clk) capture 10000 R
uncertainty -100 9900 R
-----------------------------------------------------------------------------------------------------
Start-point : clk1_reg[1]/CK
End-point : f1_reg[4]/D

3. a) Choose the correct word(s) to fill the blanks: [7]

i. NMOS pass weak ______ but strong 0 while PMOS pass degraded ______
(1, 0, Vdd, Gnd )
ii. Complementary CMOS is also known as ________ CMOS.
(static, dynamic, domino)
iii. Pseudo-NMOS follows the Rule of ____________ Complement.
(Conduction, Reduction, Deduction)
iv. Transmission gates pass both _______ and ______ well.
(1, 0, Vdd, Gnd )
v. D latch has _________ delay. (D-to-Q, Clk-to-Q, skew)
vi. D flip flop has __________ delay. (D-to-Q, Clk-to-Q, skew)
vii. SiO2 is a very good _______. (insulator, semiconductor, conductor)
viii. VDD has _________ with time. (increased, decreased, stayed same)
ix. Substrate must be tied to _______ and n-well to _______.
(VDD, GND, Gate, Source)
x. Use heavily doped well tap and substrate tap to avoid ____________.
(Latchup, Shottky Diode, Hobit)

b) Write Verilog RTL code to implement a 32-bit Fibonacci Series generator. Your code [8]
is controlled by clock and reset signals. The output signal, say out, will show the next
Fibonacci number at each positive edge of the clock. The reset signal will take the out
to zero (0).
4. a) Name different types of IO pads. What’s the purpose of IO pads? Draw the schematic [5]
diagram of an output pad.

b) Name the different types of adder discussed in class. Which type(s) of adder will you [6]
choose to build a 4-bit adder and a 32-bit adder? Justify your answer.

c) What is race condition? Why does it happen? What solution does our text book [4]
suggest? How does the industry solve this problem?

5. a)

Write the function implemented by the static [1]

A B CMOS circuit.
C
We are targeting 100nm process i.e. L = 100nm =
0.1µm. Widths of all the NMOS in the schematic
D are given in micron (µm).
OUT
Calculate the widths of all the PMOS, given the [3]
A 0.4 mobility: µn = 3µp.
D
0.2 B C Draw the stick diagram of the circuit and calculate [3]
0.2
the width and height of the circuit in micron.

b) Draw the pseudo-NMOS schematic of the static CMOS above. Specify how it works. [8]
Which problem(s) of static CMOS does pseudo-NMOS solve? Does it create any new
problem(s) while solving the static CMOS problems?