On Behavioral Modeling of a Mixed-Signal Analog
to Digital Converter
Todd Wey 1, Jim McGough2
1
Electrical and Computer Eng. Dept., Lafayette College, Easton, Pennsylvania, USA
2
AMI Semiconductor, Lower Gwynedd, Pennsylvania, USA
Abstract-A mixed-signal simulation approach is presented
where analog cells are characterized and modeled in Verilog.
Transient simulations are performed by modeling the analog
circuits in terms of an event driven forward Euler solver. The
technique is applied to a hybrid algorithmic/successive
approximation analog to digital converter and the results
presented.
I. INTRODUCTION
A common problem in mixed-signal design is simulation to
verify the overall design. Traditionally, transistor level analog
has been simulated with SPICE or similar tool and digital
designs simulated in a HDL simulator. Both of these
simulators are mature and readily available from multiple
vendors and can be purchased at a reasonable cost across most
computer platforms. The problem is that they don’t readily
provide an efficient way to simulate the overall mixed-signal
design.
In this paper, we will consider a mixed-signal simulation
strategy meeting five fundamental goals: accuracy, simulation
speed, interconnect integrity, debug capability, and simulator
cost. This strategy will then be applied to an analog to digital
converter (ADC) and the system simulation results presented.
Behavioral modeling with math tools and system simulators
provide good speed and accuracy capability [1] and is highly
recommended as the conceptual starting point for any mixed-
signal design. A primary limitation of these tools is that they
tend to be isolated from the design flow and typically don’t
meet the interconnect integrity goal. Another problem is that
each designer has his favorite system or math tool which is
incompatible with other similar tools.
The electronic design automation (EDA) vendors have
traveled down many paths in recent years to address this
mixed-signal simulation problem. One response has to been to
provide more powerful SPICE simulators using multiple
processors and to provide a “fast” SPICE processors that
evaluate the entire mixed-signal design in the analog domain.
The SPICE simulator meets the interconnect integrity and
compatibility goals but due to the large transistor count
obtained in a relatively simple mixed-signal circuit, they often
can’t provide adequate simulation speed. In the case of the
“fast” SPICE simulator, accuracy is traded for simulation
speed and the only information gained from the simulation is
validity of the interconnect.
0-7803-9197-7/05/$20.00 © 2005 IEEE. 175
Another approach has been the mixed-mode simulators
which separate the design into analog and digital domains [2]
with data passed between SPICE and HDL type simulators.
This solution provides for the interconnect integrity goal and
but for designs with relatively low analog content may provide
the accuracy and speed requirement. A current disadvantage
with this simulation approach is cost, compatibility, and speed
in designs with high frequency analog content.
A simulator that meets the goals outlined are the HDL
simulators. Although Verilog-A with “analog” behavioral
extensions has been defined and introduced in the last few
years, standard Verilog simulators with the capability of “real”
interconnect wires and basic algebraic capability have existed
for several years. Using a Verilog simulator with this
increased functionality allows the analog circuit designer to
take control of the simulation at a low level and develop block
behavioral models that simulate at high speed and capture the
fundamental dynamic limitations of the circuit block. In this
work, the transient effects of a hybrid algorithmic/successive
approximation ADC similar to [3] are modeled with an
extended Verilog simulator, SILOS™ by Simucad. The ADC
architecture is a switched-capacitor analog core with digital
control and error correction. The switched-capacitor opamp
circuits are analyzed as local level event driven differential
equations and implemented in Verilog by a local forward Euler
solving engine. The technique allows for full simulation and
analysis of bandwidth limiting effects of the analog
architecture in conjunction with the digital feedback error
correction and reconstruction technique. A further benefit of
this Verilog technique is that the full delay estimated gate-level
digital models can be simulated with first-order delay accurate
analog functional cells. This avoids the zero time delay analog
model problem of some behavioral approaches [4].
II. SWITCHED -CAPACITOR AMPLIFIER MODELING
A. The Switched-Capacitor Amplifier Simulation Model
The operational transconductance amplifier (OTA) is a
common architecture used in switched-capacitor amplifiers
where driving resistive loads is unimportant. An advantage of
the OTA is that it presents a single high impedance node at its
output and capacitive load increases stability margin [5]. The
basic continuous time small-signal OTA model is shown in
Fig. 1.
 V1
+
VO
V
V2 C1
-
- Vout

+
C2
+ +

V gmV R C VO

- - A. Inverting Switched-Capacitor Stage in Reset Phase

Figure 1. First-order OTA circuit model

C2
A common single-ended switched-capacitor circuit is shown
in Fig. 2. This circuit ideally provides an inverting signal gain
of -C1/C2. The full circuit including the small-signal OTA V1 C1
model can be analyzed in terms of event driven continuous - Vout
time circuits and initial conditions to analyze the overall small-
signal performance of the switched-capacitor cell including +
OTA finite open loop gain, capacitor loading conditions, CL

offsets, and finite circuit bandwidth. In this modeling case, it

is assumed the switch resistance is sufficiently low to not
significantly impact the transient results. B. Inverting Switched-Capacitor Stage in Sample Phase
Figure 3. Clock driven circuit topologies of the inverting switched-capacitor
CkB
gain amplifier.

C2
CkA In the sample phase, the circuit performance can again be
predicted by a first-order differential equation. Two nodal
CkA equations and a Kirchoff Voltage Law (KVL) loop equation
Vin CkB lead to the first-order differential equation describing the
sampling phase dynamics as given by equations (2) and (3).
CkB C1
- Vout • − g m RC1
τ ps Vout + Vout = V1 (2)
+ C1 + C 2 + g m RC 2
CL

R(C L (C1 + C 2 ) + C1C 2 )

τ ps =
C1 + C 2 + g m RC 2 (3)
Figure 2. The inverting switched-capacitor gain amplifier of interest.
The initial conditions for the sampling phase are a little more
The clock driven configurations of the switched-capacitor complex since switching to a non-zero voltage input will cause
amplifier are shown in Fig. 3. In the reset phase, the a high frequency transient through the capacitor loop. The
behavioral of the amplifier is predicted by a first-order result of this transient can be estimated by a capacitor divider,
differential equation from nodal analysis and given by (1). and the result added to the final condition of the reset phase.
Applying conservation of charge to the two capacitors coming The overall initial condition at the start of the sampling phase
out of the sample phase, the initial condition of the reset phase is given by (4). 1
is given by the final value of the output voltage at the end of C3
the sampling phase. Vout I = Vout I + V (4)
1 1 1 1
• R + +
τ pr Vout + Vout = 0 where τ pr = (C1 + C 2 ) (1) C1 C2 C3
1 + gm R

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B. Numerical Solution of the Switched-Capacitor Amplifier significant loss in accuracy in the faster SPICE mode. The
Verilog technique suggests about a 3X speed improvement in
One approach to solving the problem is to generate an event this switch-mode analog circuit.
driven solution by evaluating time domain differential equation
solutions over the sampling and reset phases. One difficulty Dynamic Performance of the Switched-Capacitor
that could occur in this approach is that the digital simulator Inverting Gain of Four Amplifier Simulation
Input Voltage
may not be able to evaluate transcendental functions. A
15 Output Voltage
second approach to solving the problem which can be
generalized to more complex systems is to numerically solve 10
the differential equations at the cell level using the fixed time

Voltage (Volts
step capability of the Verilog simulator. In this case, the 5

second solution option by means of a forward Euler integration

0
technique [6] was implemented. Although numerical stability
can be an issue with this technique, the time step was chosen -5
appropriately with respect to the time constants to provide
-10
adequate stability margin. The forward Euler intregration
leads to the reset and sample phase equations given by (5) and -15
(6) where Ts is the integration time step. The time constants 0 5 10 15 20
and initial conditions are those previously established. Time (usec)
Figure 4. Simulation results of the switched-capacitor amplifier in Verilog.
Ts
Vout n +1 = Vout n − (Vout n ) (5)
τ ps Comparison of Verilog Model and Spice Behavioral
Simulation
Ts g m RC1
Vout n +1 = Vout n − (Vout n − V1 ) (6)
τ ps C1 + C 2 + g m RC 2 0.5 SmartSpice

0 Verilog
-0.5
-1
Output Voltag

C. Verilog Simulation Results of the Amplifier -1.5

The switched-capacitor amplifier is implemented as -2
described in the Silos™ Verilog simulator. The design -2.5
variables for the simulation are an input sample capacitance of -3
4pF, feedback capacitance of 1pF, OTA transconductance of -3.5
1mmho, output resistance of 100Megohm, fixed load -4
capacitance of 1pF and additional sample phase load -4.5
capacitance of 10pF. The time step of the integration 23 23.5 24 24.5 25

algorithm within the amplifier cell was set to 1ns and the Time (usec)
switched-capacitor gain cell has a sample period of 1usec. The
Figure 5. SPICE versus Verilog simulation results. The noticeable region of
circuit is tested with an input ramp and a 25usec simulation
difference is the slightly faster reset to zero edge in Spice.
stop time. The output results are shown in Fig. 4. The same
structure was built in a SPICE deck using behavioral switches
and ideal linear components. The SPICE simulation was set to III. ALGORITHMIC ADC SIMULATION RESULTS
use a maximum time step of 1nsec and clocks with 1ns rise/fall
The proposed technique was applied to a mixed-signal
edges and run for 25usec of simulation time. The output
analog-to-digital converter that included both algorithmic and
results of the two simulations were overlain and shown in Fig.
successive approximation techniques to reduce die area. The
5. The only noticeable difference in the two simulation results
analog section consisted of a combined algorithmic/successive
was that the SPICE reset time was slightly faster than that
approximation hardware, comparator, and switched-capacitor
predicted by the Verilog model, but the performance of the
reference generator from variable external supplies. The
Verilog was well within expectations. To benchmark the
digital section included the state machine to drive the analog
speed, the simulators were run to a simulation stop time of
sections, the error correction algorithm, and serial output data
250usec with a fixed input of 1 Volt. The Verilog run time
driver. The mixed-signal top level interconnect is shown in
was 0.32 seconds on a Pentium 4 laptop with Windows XP
Fig. 6.
running at 3GHz and 512MB of RAM. SmartSpice™ by
The full 8-bit converter was simulated with an input ramp
Silvaco was run on the same platform with both a maximum
with 4mV steps over an input range of –0.02V to 4.02 Volts.
time step of 1nsec which took 48 seconds and with the default
The ramp was incremented after each conversion cycle of
maximum time step taking 1.1 seconds. There was no

177
approximately 41usec giving a simulation stop time of
41.71milliseconds and 1010 8-bit conversions. This simulation
required 353 seconds of processing time with Silos running on
the same computer platform as previous. The simulated ramp
output result is shown in Fig. 7 and example internal “analog”
nodes of the simulation are shown in Fig. 8.
IV. CONCLUSIONS
The mixed-signal simulation technique presented has met
the initial goals of our mixed-signal design flow: accuracy,
simulation speed, interconnect integrity, debug capability, and
simulator cost. The primary disadvantage is that it requires
custom model development work to support the Verilog
numerical techniques.
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for mixed-signal simulations of digital telecommunication front-ends,”
2000 Southwest Symposium on Mixed-Signal Design, pp. 27-29, February
2000.
[2] H.R. Ghasemi and Z. Navabi, “An effective VHDL-AMS simulation
algorithm with event partitioning,” Proceedings of the 18th International
Conference on VLSI Design, pp. 762-767, 2005.
[3] P.W. Li, M.J. Chin, P.R. Gray, and R. Castello, “A ratio-independent
algorithmic analog-to-digital conversion technique,” IEEE Journal of
Solid-State Circuits, vol. sc-19, no. 6, pp. 828-837, December 1984.
[4] M.K. Mayes and S.W. Chin, “All Verilog mixed-signal simulator with
analog behavioral and noise models,” 1996 Symposium on VLSI Circuits
Digest of Technical Papers,” pp. 186-187, June 1996..
[5] D. Johns and K. Martin, Analog Integrated Circuit Design, New York,
NY: John Wiley and Sons Inc., 1997.
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Circuits, Englewood Cliffs, NJ: Prentice-Hall Inc., 1975.

Sample Clocks
Transfer Clocks
Error Correction Clocks
SAR Clocks

Auto-zero / Compare Clock

Analog Input Sample_Hold

& Residue Auto-Zeroed
Successive Comparator 1 bit ADC Output
Approx
Digital State
Machine for Serial Data
VAVE Clocking
Algorithm and
VRefHI
Error Correction
VRefLO Average Value VAVE Sample Clk
Generator

Residue Gain
Amplifier VAVE

Gain Amp Sample Clocks

Gain Amp Transfer Clocks

Master ADC Clock

Figure 6. Analog-to-Digital Converter Block Diagram

Verilog Generated Output Ramp for Top Level of EmbeddedAnalog Waveforms in Verilog Simulation
Mixed-Signal IC
3.25
SuccApprox_Amp
300 FBGain_Amp

3
250

2.75
200
Voltage (Volt
Output Cod

150 2.5

100 2.25

50 2

0 1.75
0 1 2 3 4 0 1 2 3 4 5 6
Input Voltage Time (usec)

Figure 7. Full code range simulated ramp response of ADC Figure 8. Internal analog nodes within the Verilog ADC simulation

178