REGULATION: 2017 ACADEMIC YEAR: 2019-2020

PART-B
1. Define stability factor and derive the general expression for stability factor. (13)U
(N/D10, A/M 12, 13, N/D- 14)(T1:1.21-1.24)
Stability Factor:
The operating point must be stable for certain operation of the transistor. However the operating point
shifts with changes in transistor parameters such as β, I CO and VBE. As transistor parameters are
temperature dependent, the operating point also varies with temperature.
The stability factor indicates the degree of change in operating point due to variation in β, ICO and VBE.
Base circuit (2)
Applying Kirchhoff’s voltage law to the base circuit we get,
VCC-IB RB-VBE =0
Solving for the current IB,

Collector circuit (2)

Applying Kirchhoff’s voltage law to the collector circuit we get,
VCC-IC RC-VCE =0

The magnitude of the collector current is given by

Were VC : Collector voltage , VE : Emitter voltage ,Similarly,

Where VB : Base voltage

In this circuit, VE = 0,
Therefore

Expression for stability factor (5)

Stabilization techniques gives different biasing circuits in order to compare the stability provided
by these circuits,
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Stability factor S (4)

For a common emitter configuration collector current is given as,

When ICBO changes by ∆ICBO, IB changes by ∂ IB and IC changes by ∂ IC. So this equation becomes,

Therefore,

2. (a) Calculate the minimum and maximum values of I C and VCE for the base bias when hFE(min)=50
and hFE(max)=60. For circuit, Vcc = 12 V, Rc =2K and RB= 150 K. Assume silicon transistor.
(T1:1.11-1.12)(A/M-16) (6) A
Solution:
For silicon transistor VBE = 0.7 V

= 75.33µA (2)
For hFE(min)
= 50 X 75.33µA
= 3.767 mA (2)
And, VCE=VCC-ICRC
= 12-3.767mA X 2kΩ
= 4.466V
For hFE(max)
= 60 X 75.33µA
= 4.52 mA
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And, VCE=VCC-ICRC
= 12-4.52mA X 2kΩ
The voltahe between collector an emitter, VCE = 3 V. (2)

(b) Design a collector to base bias circuit for the specified conditions: V CC=15V, VCE=5V, IC=5mA
and β=100. (T1:1.29) (7) S
Solution:
I C 5mA
IB = = = 50m A (2)
b 100
We Know that for collector to base bias circuit,
VCE= VCC-(IB+IC) RC
Thus we can write,
VCC - VCE 15 - 5
RC = = = 1.98 K W
I B + IC 50 X 10-6 + 5 X 10-3 (3)
RC = 1.98K W
Applying KVL to the input circuit we have,
VCC -IBRB –VBE = 0
V -VBE 5 - 0.7
RB = CE =
IB 50 X 10-6
The base resistance RB = 86 K W
(2)

3. Derive the stability factors for voltage divider bias circuit and give reason why its advantageous
than fixed bias circuit. (T1:1.37-1.39 (A/M-17)(13) S
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 The voltage divider bias, the diode is connected in series with resistance R2 in the voltage divider
circuit and it is forward bias condition.
voltage divider bias,

 When VBE changes with temperature, IC also changes. To cancel the change in IC, one diode ID used
in this circuit for compensation as shown in figure the voltage at the base VB is now,
VB = VR2 + VD
Substituting above equation, we get,

 The diode which is used in this circuits is of same material and type as the transistor, the voltage
across the diode will have the same temperature, VD changes by ∂ VD = ∂VBE‫ ׳‬the changes tend to
cancel each other and leave the collector current as
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 Which is unaffected due to change in VBE? From the figure we can see that biasing is provided by
R1, R2 and RE. The change in VBE due to temperature is compensated by changes in the diode voltage
which keeps IC stable at Q point.
In case of germanium transistor, Change in ICO with temperature are comparatively larger than
silicon transistor. Thus in germanium transistor change in I CO with temperature play the most important
role in collector current stability than the change in the VBE. The figure shows diode compensation
technique commonly used for stabilizing against variation in ICO.

In the reverse biased condition the current flowing through diode is only the leakage current. If the
diode and the transistor are of the same type and material, the leakage current I O of the diode and the
transistor are of the same type and material, the leakage current I O of the diode will increase with
temperature at the same rate as the collector leakage current ICO.

VCC - VBE
I=
R1
I = IB + I 0
I = I - IO
\ B

 For germanium transistor VBE = 0.2 V which is very small and neglecting change in VBE with
temperature we can write,

If β >> 1 we get,
IC = β I – β IO + β ICO
Now if , IO = ICO we get,
IC = βI
As β-value is fixed for a given transistor, this relation can be satisfied either by keeping R E fairly large,
or making R1||R2 very low. (2)
 If RE is of large value, high VCC is necessary. This increases cost as well as precautions necessary
while handling.
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 If R1 || R2 is low, either R1 is low, or R2 is low, or both are low. A low R1 raises VB closer to VC,
reducing the available swing in collector voltage, and limiting how large RC can be made
without driving the transistor out of active mode. A low R2 lowers VBE, reducing the allowed
collector current. Lowering both resistor values draws more current from the power supply and
lowers the input resistance of the amplifier as seen from the base.
 AC as well as DC feedback is caused by RE, which reduces the AC voltage gain of the amplifier.
A method to avoid AC feedback while retaining DC feedback is discussed below.

4(a).Briefly explain the reason for keeping the operation point of a transistor as fixed (T1:1.13-
1.14) (6) U

 The biasing circuit provides stability of operating point in case of variation in the transistor
parameters such as ICO, VBE and β. The collector to base bias and the voltage follower bias use the
negative feedback to do the stabilization action. This negative feedback reduces the amplification of
the signal. If this loss in signal tolerance is intolerable and extremely stable biasing conditions are
required, then it is necessary to use compensation techniques.
(3)
The transistor can be operated in three regions: cut off, active and saturation by applying proper biasing
conditions.

Emitter Base Junction Collector Base Junction

Cut- off Reverse Biased Reverse Biased
Active Forward Biased Reverse Biased
Saturation Forward Biased Forward Biased

 In order to operate transistor in desired region we have to apply external d.c. voltages of correct
polarity and magnitude to the two junctions of the transistor. This is nothing but the biasing of the
transistor. Because d.c. voltages are used to bias the transistor, known as d.c. biasing of the
transistor.
 In transistor amplifier circuits, output signal power is always greater than input signal power. The
d.c. sources supplies the power to the transistor circuit to get the output signal power greater than
input signal power.
(3)
(b) Explain the design of fixed bias circuit. Mention the advantages and disadvantages of fixed
bias circuit. (T1:1.25-1.26) (A/M- 10)(7)
U
 The operating point must be stable for certain operation of the transistor. However the operating
point shifts with changes in temperature.
 The below figure shows the fixed bias circuit. It is the simplest d.c. bias configuration. For the d.c.
analysis we can replace capacitor with an open circuit because the reactance of a capacitor for d.c is
XC =1/2πfC=1/ 2π(0)C = ∞. The d.c. equivalent of fixed bias is shown.
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Base circuit (3)

Applying kirchoff’s voltage law to the base circuit we get,
VCC-IB RB-VBE =0
Solving for the current IB,

Collector circuit
We now consider the collector circuit as shown in figure.
Applying Kirchoff’s voltage law to the collector circuit we get,
VCC- IC RC- VCE = 0

The magnitude of the collector current is given by

And from equation 1.2 we have,

It is important to note that since the base current is controlled by the value of R B and IC is related to IB by
a constant β, the magnitude of IC is not a function of the resistance R C. Changing RC to any level will not
affect the level of IC or IB as long as we remain in the active region of the device. However the change in
RC will change the value of VCE.

Where VC : Collector voltage

VE: Emitter voltage
Similarly,

Where VB : Base voltageIn this circuit, VE = 0,

Therefore

(2)
Merits:
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 It is simple to shift the operating point anywhere in the active region by merely changing the base
resistor (RB).
 A very small number of components are required.
Demerits:
 The collector current does not remain constant with variation in temperature or power supply
voltage. Therefore the operating point is unstable.
 Changes in VBE will change IB and thus cause RE to change. This in turn will alter the gain of the
stage.
 When the transistor is replaced with another one, considerable change in the value of β can be
expected. Due to this change the operating point will shift.
 For small-signal transistors (e.g., not power transistors) with relatively high values of β (i.e., between
100 and 200), this configuration will be prone to thermal runaway.
Applications
 The fixed bias is rarely used in linear circuits (i.e., those circuits which use the transistor as a current
source). Instead, it is often used in circuits where transistor is used as a switch. However, one
application of fixed bias is to achieve crude automatic gain control in the transistor by feeding the
base resistor from a d.c. signal derived from the a.c. output of a later stage. (2)
5. Design the Emitter stabilized bias circuit and derive its stability factor.(T1;1.52-1.55)
(N/D-16) (13) S
To improve the stability of the biasing circuit over the fixed bias circuit, the emitter resistance is
connected in the biasing circuit. This circuit is called emitter bias circuit.
Design Steps:
Step1: To calculate VCC
Step2: To calculate IE
Step3: To calculate VB
Step4: To calculate VE (4)
VCC-IBRB-VBE-IERE=0
We have IE=(1+ β)IB.

We know that,
VB − VE = VBE
If RB is small enough, base voltage will be approximately zero. Therefore emitter current is,
IE = (VEE − VBE)/RE
 The operating point is independent of β if RE >> RB/β
 This type can only be used when a split (dual) power supply is available.
 When a split supply (dual power supply) is available, this biasing circuit is the most effective,
and provides zero bias voltage at the emitter or collector for load. The negative supply V EE is
used to forward-bias the emitter junction through RE.
 The positive supply VCC is used to reverse-bias the collector junction. Only two resistors are
necessary for the common collector stage and four resistors for the common emitter or common
base stage. (3)
Circuit diagram
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(6)

6. Explain Collector to Base bias circuit for BJT. (T1:1.27-1.29)

(13) S
The base bias resistor, RB is connected to the transistors collector C, instead of to the supply
voltage rail, Vcc. If the collector current increases, the collector voltage drops, reducing the base drive
and thereby automatically reducing the collector current to keep the transistors Q-point fixed.
(4)

This method of collector feedback biasing produces negative feedback as there is feedback from the
output to the input through resistor, RB. (4)

The base current can be derived as,

This connection is mostly used to stabilize the operating point against temperature changes. In this type,
the base resistor is connected to the collector instead of connecting it to the supply. So any thermal
runaway will induce IR drop in the collector resistor. (5)
7. (a) For a potential divider bias circuit with R 1=100 KΩ, R2=5 KΩ, RC=2 KΩ RE=500Ω, β=100
and VCE=7V, ICO=1Na 250C, calculate the thermal resistance θ for the transistor in order to make it
thermally stable. (T1:1.74-1.75) (7)A
Solution:
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RB =

= 4792 Ω (2)
Applying KVL to the collector circuit,
Vcc = VCC - IC RC - IE RE

(2)

<

The collector current is 1.346 X <

θ<7.427 x108◦C/W to make the circuit thermally stable. (3)
(b) Draw the dc load line for the following transistor configuration. Obtain the quiescent point.
(T1:1.41-1.42)(6) A

Solution:
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V R
VTH = CC B 2
RB1 + RB 2
12 X 1.24 K
= = 2.31V
5.2 K X 1.24 K
RB = RB1 || RB 2
5.2 K X 1.24 K (2)
= =1K
5.2 K + 1.24 K
Applying KVL to the base circuit we get,
VTH -VBE
IB =
RB + (1 + b ) RE
2.31 - 0.7
= = 145 m A
1K + (1 + 100)100

IC = βIB = 100 x 145 µA = 14.5 Ma

VCE = VCC-ICRC-IERE
=12- (14.5 mA x 330) – (101 x 145 µA x 100)
= 12 – 4.785 – 1.4645
The voltage between collector and emitter is = 5.7505 V (2)

The d.c. load line for the above circuit can be drawn as shown

(2)
8. Locate the operating point of the circuit shown in figure. VCC=15V, hfe=200. (T1:1.36-37) (13)A

Solution:
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VCC - VBE
I BQ =
RB + (1 + b )(R C + RE )
15 - 0.7
=
630 X 10 + (1 + 200)(4.7 X103 + 680)
3

= 8.356 m A
(4)
-6
ICQ = β IBQ = 200 x8.356 x10
=1.6712 Ma (3)

IEQ = ICQ + IBQ

=1.6712 x 10-3 + 8.356 x 10-6
=1.68 mA (3)
VCEQ = VCC – IE(RC+RE)
=15 - 1.68 x 10-3 (4.7 x103 + 680)
=5.9616 V (3)

9.A self bias circuit has RE= 1K, R1=130 K, R2=10K. If VCC and RC are adjusted to give IC=1 mA at 10
ºC, Calculate the variation in IC over temperature range of 10 ºC to 100 ºC. The transistor used has
the parameters given below. (T1:1.47-1.49) (13)A

Parameters 100C 1000C

ICO µA 0.01 1.2
VBE Volt 0.74 0.54
Β 60 140
Solution:
The self bias circuit is shown with all values

At 10˚C, IC = 1 mA
∆ICO = ICO2 – ICO1 = 1.2 – 0.01 = 1.19 µA
∂VBE = VBE2 – VBE1 = 0.54-0.74 = -0.2 V
∂β = β2 – β1 = 140 – 60 = 80
∂IC = S∂ICO + S'∂VBE + S"∂β (3)

S for self-bias is given by

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RB = R1║R2 = = 9.29 K

S= = = 8.93

And S' = = = -0.85×

At 100˚C, (4)

S" = where S2 = S with β = β2

S2 = = = 9.65 (3)

S" = = 1.140×

∂IC = (8.93) (1.19) µA + (-0.85× ) (-0.2) + (80) (1.140× )

= 10.63 µA + 0.17 mA + 92 µA = 272.63 µA (3)

10.(a) Explain the miscellaneous bias configuration with example. For the circuit shown in fig below
we need to calculate IB, VC and VCE. (T1:1.55-1.56)(7) U

Solution:
The emitter base junction is forward biased, assume transistor is in active region.
Applying KVL on base side we get,
VEE = IB RB + VBE act + IERE
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10 = IB RB + VBE act + ( 1+ β) IBRE
10 – 0.7 = 270 X 103 IB + 101 X 103 IB
9.3= 371 X 103 IB
IB = 9.3/(371 X 103) = 25.067 µA (3)
Applying KVL on collector side we get,
VEE = IC RC + VCE act + IERE
VEE = β IB RC + VCE act + (1+ β) IBRE
Substituting value of IB we get,
10 = 100 X 25.067 X 10-6 X 1 X 103 + VCE act + (1+ 100) X 25.067 X 10-6 X 1 X 103
= 2.5067 + VCE act + 2.53176
VCE act = 4.961 V
And IC = β IB = 100 X 25.067 X 10-6 = 2.5067 mA (4)

(b) Design a fixed bias circuit having operating point of 10V, 3mA the circuit is supplied with 20V
and uses a silicon transistor of hFE = 250. (T1:1.29-1.30)
(6)A
Solution:
Applying KVL to the collector circuit we have,
VCC- IC RC- VCE = 0
VCC -VCE 20 - 10
RC = =
IC 3mA
= 3.33 K W (2)
I 3mA
IB = C = =12 mA
b 250
Applying KVL to the Base circuit we have, (4)
VCC- IB RB- VBE = 0
VCC -VBE 20 - 0.7
RB = =
IB 12mA
RB =1.6 M W
11. Draw the circuit which uses a diode to compensate for changes in Ico .Explain how stabilization
is achieved in the circuit. (T1:1.64-1.65) (N/D-17)(13) R
Diode compensation techniques
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 The voltage divider bias with basic compensation technique. Here separate supply V DD is used to
keep diode in forward bias condition. If the diode used in the circuit is of same material and type
as the transistor,
 The voltage across the diode will have same temperature co-efficient (-2.5 mV/ ᵒC) as the base to
emitter voltage VBE. So when VBE changes by ∂VBE with change in temperature, VD changes by ∂
VD and ∂ VD‫ ∂= ׳‬VBE‫ ׳‬the changes tends to cancel each other.
(3)
Applying KVL to the base circuit, we have
VT = IB RB + VBE + (IB + IC) RE-VD (2)
= IB (RB + RE) + IC RE + VBE –VD
Considering leakage current we have,
IC = β IB + (1 + β) ICO

Substituting the values in equation (1) we have

Therefore,

Therefore,

(9)
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12. Define operating point and explain DC load line with neat sketch. (N/D 13) (T1:1.17)
(13) R
Operating Point: (3)
 The operating point must be stable for proper operation of the transistor. As transistor parameters
are temperature dependent, the operating point also varies with change in temperature. The stability
factor indicates the degree of change in operating point due to variation in transistor parameters
such as β, ICO and VBE.
DC load line (3)
For fixed-bias circuit, we have

 Comparing this equation with equation of straight line y=mx+ c, where m is the slope of the line
and c is the intercept on Y-axis, then we can draw straight line on the graph of I C versus VCE which is
having slope -1/RC and Y-intercept VCC/RC. To determine the two points on the line we assume V CE =
VCC and VCE = 0.
When VCE=VCC; IC=0 and we get a point A
When VCE=0; IC=VCC / RC and we get a point B. (2)
 The output characteristics of a common emitter configuration with point A and B, and line drawn
between them. The line drawn between points A and B is called d.c. load line. The ‘d.c.’ word
indicates that only d.c. conditions are considered, i.e input signal is assumed to be zero.

Common Emitter output characteristics with d.c. load line

The d.c. load line is a plot of I C versus VCE. For given value of RC and given level of VCC. Thus it
represents all collector current levels and corresponding collector emitter voltage that can exist in the
circuit knowing any one of IC, IB, or VCE, it is easy to determine the other two forms of load line. The
slop of the d.c. load line depends on the value of RC. It is negative and equal to the reciprocal of RC.
VCC – IB RB –VBE = 0
IB RB = VCC – VBE
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The intersection of curves of different values of IB with d.c. load line gives different operating points.
For different values of IB, we have different intersection points (quiescent point or Q point) such as P, Q
and R. (5)

13.(a) The circuit of BJT amplifier is shown on Fig. Draw d.c. load lines. Also find the Q-point.
Assume VBE=0.7 Volts. (T1:1.14-1.15) (7)
A

Solution:
Step1: Obtain ICQ, VCEQ, point A and point B
Applying KVL to the base circuit we have,
VCC - IBRB - VBE = 0
Therefore

= 51.36 µA (3)

ICQ = βIB = 100 X 51.36 µA = 5.136 mA

Applying KVL to the collector circuit we have,

Therefore, = = 12- 5.36 X 10-3 X 1000 = 6.864 V

Thus Q-point is ICQ, = 3.424 mA, 6.864 V (2)
Step 2: Mark axes intersection points
Point A : VCE = VCC = 12 V at IC = 0

Point B : IC = = = = 12 mA

Step 3: Draw d.c. load line

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(2)

(b) For the emitter bias network shown in figure, determine IB, IC, VCE, VC, VE, VB and VBC. (6)
(M/J-09) (T1:1.53-1.54)
A

= 40.125 μA

(3)
REGULATION: 2017 ACADEMIC YEAR: 2019-2020
20V

430k 2k
1 2 Vo
10u
Vin 1 2

10u
2

1k 40u
1

(3)
The voltage between base and collector is ,13.2411
14.(a) Explain in detail about selection of operating point. (T1:1.18) (N/D-16) (13)U

Selection of operating point

(4)
 The operating point can be selected at different positions on the d.c. load line: near saturation
region, near cut-off region and at the center, i.e in the active region. The selection of operating point
will depend on its application. When transistor is used as an amplifier, the Q point should be
selected at the center of the d.c. load line to prevent any possible distortion the amplified output
signal
Case 1: (3)
 Biasing circuit is designed to fix a Q point at a point P, as shown. Point P is very nearer to the
saturation region. As shown in figure the collector current is clipped at positive half cycle. So,
eventhough base current varies sinusoidally, collector current is not a useful sinusoidal waveform.
i.e. distortion is present at the output. Therefore point P is not a suitable operating point.
REGULATION: 2017 ACADEMIC YEAR: 2019-2020
(3)
Case 2:
 Biasing circuit is used to fix a Q point at a point R. Point R is very nearer to the cut-off region. As
the collector current is clipped at the negative half cycle. So point R is also not a suitable operating
point.
Case 3: (3)
 Biasing circuit is designed to fix a Q point at a point Q. The output signal is sinusoidal waveform
without any distortion. Thus point Q is the best operating point.
15. Define bias compensation and discuss various types of bias compensation in detail. (T1;1.64-1.68)
(13)(N/D 10,12 A/M- 13)R
 The biasing circuit provides stability of operating point in case of variation in the transistor
parameters such as ICO, VBE and β. The collector to base bias and the voltage follower bias use the
negative feedback to do the stabilization action. This negative feedback reduces the amplification of
the signal. If this loss in signal tolerance is intolerable and extremely stable biasing conditions are
required, then it is necessary to use compensation techniques. (3)
 This refers to the use of temperature sensitive devices such as diodes, transistors,
thermistors, etc, which provide compensating voltages and current to maintain the operating
point stable.
Thermistor compensation:
this method of transistor compensation uses temperature sensitive elements, thermistors rather than
diode or transistors.(3)

(2)

The transistor compensation technique connecterd \between emitter and vcc to minimize the
increase in collector current due to changes in Ico,VBE,

(4)
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(3)

16. Define thermal stability and derive the condition for thermal stability.(1.70-1.73) (13)U
(N/D-08, A/M 13)
Thermal stability is a heat property and a measurement of a temperature difference by which an object
or material resists a heat flow (heat per time unit or thermal resistance). Thermal resistance is
the reciprocal of thermal conductance.
 Thermal runaway refers to a situation where an increase in temperature changes the conditions in a
way that causes a further increase in temperature, often leading to a destructive result. It is a kind of
uncontrolled positive feedback. (4)
 The Leakage current increases significantly in bipolar transistors (especially germanium-based
bipolar transistors) as they increase in temperature. Depending on the design of the circuit, this
increase in leakage current can increase the current flowing through a transistor and thus the power
dissipation, causing a further increase in collector-to-emitter leakage current (4)
 Since IC0 is temperature dependent, Collector current IC increases with increase in
temperature. IC0 doubles for every 10°C rise in temperature. Increase in IC increases power
dissipation at Collector junction. This increases the junction temperature causing further rise in IC.
This cumulative process or the phenomenon due to self-heating, in which rise in temperature and
current chase each other resulting in increased power dissipation (PC) is called Thermal runway and
can be prevented by proper biasing for low-power circuits and by using heat sinks for Transistors
operating at large powers.
The condition to prevent thermal runaway is

<

On differentiating,
Tj – TA = PD

1=

=
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On substituting we get,

<

This is because IC0 doubles for every 10°C rise in temperature. In other words, IC0 changes by 7% = 0.07
per °C for both silicon and Germanium transistors. (5)

17. Discuss in detail about biasing of E-MOSFET common –source circuit. (T1:2.16-2.17) (13)
(N/D-13) U
Common - source biasing circuit for E-MOSFET

 Biasing circuit for enhancement type common source NMOSFET amplifier without source
resistor
Gate voltage VG= VGS =VDD (R1/R1+R2)
Drain current ID = k [ VGS - VTh]2
Assuming Gate-to-Source voltage VGS is greater than the Threshold voltage VTh, biasing of the
enhancement type MOSFET is carried in the saturation region, where (4)
VTh = Threshold voltage is the minimum voltage required for device conduction and K is the

Conduction parameter.
From the above equations, Drain Current ID at Q can easily be calculated. (4)
VDS(Q) can be calculated from the following equation

Drain to source voltage VDS = [VDD - IDRD] Volts.

Potential-divider biasing for Enhancement type MOSFET with source :

Biasing of enhancement MOSFET

 MOSFET device can be biased in two different types of environments for the device to work as an
Amplifier: (1) Discrete type and (2) VLSI circuit environments. Methods of biasing are different in
these environments. While designing discrete version of MOSFET circuits, biasing resistors are used.
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Whereas, in integrated MOSFET circuit design, other MOSFET devices are used for resistors, so that
the circuit is totally built using MOS devices and VLSI scaling can easily be achieved.

 If the MOSFET device is a DMOSFET, Gate-to-Source voltage VGS can be positive or negative. Zero
bias of DMOSFET is unique and it will not work with EMOSFET, FET or a bipolar device (BJT). Self-
Biasing and Current Source-Biasing techniques can also be used with DMOSFET. The Depletion
MOSFET (DMOSFET) devices can be operated as EMOSFET devices also. Enhancement mode of
operation increases the conductivity of the channel, resulting in more Drain Current ID for a given VGS.
Because of simpler construction and smaller size, EMOSFET devices are quite useful while designing
VLSI circuitry. It has advantages over all other amplifying devices in their bias.(5)

18.(a) For the circuit shown in figure assume that R1 = 30kΩ, R2 = 10kΩ, RD = 30 kΩ, VDD= 10V, VT =
1V, VGS = 2V and K = 0.1mA/V2. Find ID and VDS. (T1:2.18-2.19) (6) A

Solution:
Step 1: Calculate VG
From the circuit shown in fig we have, (2)

VG = VGS = ( VDD

=( = 2.5 V
Step 2: Calculate ID
Assuming the MOSFET is biased in the saturation region, the drain current is, (2)
ID = Kn ( VGS – VT)2= (0.1) (2 -1 )2
=0.1 mA
Step 3: Calculate VDS
VDS = VDD – IDRD = 10 – (0.1) (40) = 6V
Validity of assumption: Since VDS = 6 V > VDS(sat) = VGS - VT = 2 – 1 = 1V, the MOSFET is indeed
biased in the saturation region and our calculations are correct. (2)
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(b) For the Circuit in the Figure, draw the AC load line and determine the maximum output
swing without distortion. (N/D 12) (7)

 Once Q point is found, take the I CQ value and IC sat value. Compare them and see which of the
following is less-> Difference between ICQ and IC sat value or ICQ value and 0 (corresponds to x
axis point on load line with VCE=VCC).
(2)
 ICQ = 2.64mA and ICsat = 4mA. Thus we find that difference between them ie 1.36mA is less
than difference between ICQ(2.64mA) and 0.
 VCE=0.7V (the minimum we have decided to go) and calculate the corresponding IC value
 load line. (12-.7) /3K =3.7666mA
 The maximum swing we can take is 1.12mA or base swing as 6.25uA. The maximum base
current would correspond to maximum base voltage. So maximum base current is 14.69uA+
6.25uA = 20.925uA We are now adding a AC source for this additional base current that the
design can faithfully amplify. Let this voltage be Vext (3)
Using the initial equation for calculating base current
Ib = (4+Vext-0.7)/(7.33 +181*1.2)k where Ib is 20.925uA so Vext =1.398 V.

19.(a) Discuss the operation of thermistor compensation. (T1:1.67-1.69)(A/M- 10)(6) U

Thermistor is a device which is having negative temperature coefficient

If the temperature increases
 Thermistor resistance decreases.
 Current flowing through RT increases.
 Since the voltage drop across RE increases in the direction, it reverse biases the transistor Base –
Emitter junction which reduces IB and keeps IC constant.
 Thus RT compensates the increase in IC
 Thus the temperature sensitivity of RT provides compensation to the increase in collector current IC
due to rise in temperature T.
 The same result is obtained if the transistor RT is placed in the base circuit across R2 instead of in
collector circuit.
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(b) Design a collector to base bias circuit to have operating point of (10V, 4mA). The circuit is
supplied with 20V and uses a silicon transistor of hFE = 250. (T1:1.29-1.30)
S (7)

Solution:
IB I /β
= C

= 4 m A / 250
=16µA (2)
We know that for collector to base bias circuit,
VCE= VCC – (IB+ IC)RC
Thus we can write ,
RC =VCC - VCE/ (IB+ IC)
= 10 - 0.7 / ( 16µA +4mA) (2)
Applying KVL to the input circuit we have,
VCC -IBRB –VBE = 0
RB = VCE - VBE /IB
= 10 - 0.7/ 16µA

The base resistance RB = 581.25KΩ (3)

20. (a)Discuss in detail about biasing of D-MOSFET common –source circuit. (T1:2.30-2.32) U
(7)
The amplifier circuit consists of an N-channel JFET, but the device could also be an equivalent N-
channel depletion-mode MOSFET as the circuit diagram would be the same just a change in the FET,
connected in a common source configuration. The JFET gate voltage Vg is biased through the potential
divider network set up by resistors R1 and R2 and is biased to operate within its saturation region which
is equivalent to the active region of the bipolar junction transistor. (2)

Unlike a bipolar transistor circuit, the junction FET takes virtually no input gate current allowing the
gate to be treated as an open circuit. Then no input characteristics curves are required.
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(2)
D-MOSFET amplifier with gate bias
Governing equations are shown in brief along with performance parameters.
 Normally on device
 Gate Bias used
ID = IDSS (1 – VGS / VGS(off) )2
VDS = VD = VS
gm = gmo (1 – VGS / VGS(off) )
AV = gm rd,
Zin ≈ RG
Zout ≈ RD
Common Source JFET Amplifier Characteristics Curves (3)
The DC load line for the common source JFET amplifier produces a straight line equation whose
gradient is given as: -1/(Rd + Rs) and that it crosses the vertical I d axis at point A equal to Vdd/(Rd + Rs).
The other end of the load line crosses the horizontal axis at point B which is equal to the supply voltage,
Vdd.
The actual position of the Q-point on the DC load line is generally positioned at the mid center
point of the load line (for class-A operation) and is determined by the mean value of Vg which is biased
negatively as the JFET is a depletion-mode device. Like the bipolar common emitter amplifier the
output of the Common Source JFET Amplifier is 180o out of phase with the input signal.

(b) Explain about the FET as Switching Circuit with neat diagram. (7)U

 FET can be used as a switch by operating it in two regions, they are cutoff and saturation region.
When the VGS is zero the FET operates in saturation region and maximum current flows through it.
REGULATION: 2017 ACADEMIC YEAR: 2019-2020
Hence it is like a fully switched ON condition. Similarly, when the VGS applied is more negative
than the pinch off voltage, FET operates in cutoff region and doesn’t allow any current flow through
the device. Hence FET is in fully OFF condition.
Ohmic Region (VDS> 0 and VDS < VP) (2)

 The VDS value is greater than zero and less than VP so there is no pinch off of the channel and the
current ID increases. When we increase the gate source voltage VGS, the channel conductance falls
and the resistance is increased. Therefore, the depletion regions will spread more that makes a
narrow channel. The channel resistance changes generally from 100 ohms to 10K ohms and
obviously controls the voltage. Hence transistor acts as voltage controlled resistor in this region
Saturation Region (VDS > VGS – VP ) (2)
FET Used as a Shunt Switch

 The VGS applied is zero the FET is turned ON by operating in saturation region and its resistance is
very small nearly 100 ohms. The output voltage across the across the FET is VOUT= Vin * {RDS/
(RD + RDS (ON))}. Since the resistance RD is very large, the output voltage is approximately
considered as zero.
 When we apply the negative voltage which is equal to the pinch off voltage at the gate, FET operates
in the cutoff region and acts as a high resistance device and the output voltage is equal to the input
voltage.

FET Used as a Series Switch

 FET acts as a series switch. It acts as a closed switch if the control voltage is zero and open
switch if control voltage is negative. When the FET is ON, the input signal will appear at the
output and when it is OFF the output is zero.

 the gate terminal makes current to flow through the LED because FET is in saturation mode.
Therefore, the LED becomes ON.With a sufficient negative voltage on the gate terminal (about
3-4 volts), JFET drives into cutoff mode so the LED becomes turned OFF.
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(3)

PART -C

1. Design a circuit silicon transistor with β = 50 , VCC =20 V , RC =5K is used in self bias . It is desired
to establish a Q point at VCE= 11.5V, IC=1.5mA and stability factor S< 3. Find RE. A
Solution:
Step 1:To find Base current
IB = IC/ β =1.5 mA/ 50 =30µA
Step 2: To find Emitter current
IE =IB +IC =1.53mA
Step 3: To find Emitter voltage
VE= VCC –ICRC –VCE
= 20 – (1.5mA x 5K) -11.5
= 1V.
Step 4: To find emitter resistance
RE = VE / IE = 1/1.53 mA =653.59Ω
Step 5 : To construct the circuit diagram

2. Design a voltage divider bias circuit for the specified conditions VCC =12V, VCE = 6V, IC = 1mA,
S=20, β = 100 and VE =1V. A
REGULATION: 2017 ACADEMIC YEAR: 2019-2020
Step 1:To find Base current
IB = IC/ β =1 x10 -3 /100
=10µA.
Step 2 :To find Emitter current
IE = IB + IC = 10µA + 1mA
=1.01mA.
Step 3:To find Emitter resistance
RE = VE / IE =1V/ 1.01 mA
= 990Ω
Step 4: To find Collector resistance
RC=VCC –VCE – Ve / Ic = 12-6-1/ 1mA
=5KΩ
Step 5 : Construct the circuit diagram

3. Design the values of IB and RC for 10V, 3mA the circuit is supplied with 20V and uses a silicon
transistor of hFE= 250. A

Step 1:Apply KVL to the Collector circuit.

Step 2:To find Collector Resistance

Step 3: To Find Base Current

Step 4 : Construct the circuit diagram

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4. Design the emitter bias network RB=430KΏ, RE=1K, RC=2K, VCC=20V. Determine IB, IC, VCE, VC.
A
Step 1: To Find IB

= 40.125 Μa
Step 2: To Find IC

Step 3: To Find IE

Step 4: To Find VCE

Step 5: To Find Vc

STEP 6: To Construct the circuit diagram

5. Design a voltage divider bias circuit when hFE =50, VCC=12 V, R1 =10K, R2=2K, RE =470Ω and
RC = 2K. A
Solution:
Step 1: T find V R1,R2:
VT =R2 / R1+R2 VCC
= 2 x103/ 10 x103+2 x 103 x 12
=2 V
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Step 2: TO find RB,R1,R2:
RB = R1 || R2:10k || 2K 1.67KΩ
Step 3 : Construct the circuit diagram
=

T1:A.P.Godse, U.A.Bakshi, “Electronics Circuits – I”, Technical Publications, 1ST Edition 2018.