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APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
INTRODUCTION The error amplifier noise, VN, is also multiplied by the same
Noise is a parameter that is extremely important to designers of factor, resulting in an output noise that increases in proportion
high performance analog circuits. This is especially true for to the programmed output voltage.
high speed clocks, analog-to-digital converters (ADCs), digital- When output voltages are less than a factor of two times the
to-analog converters (DACs), voltage controlled oscillators reference voltage, there is only a modest increase in the output
(VCOs), and phase-locked loops (PLLs). The key to reducing the noise. This modest increase, however, can be unacceptable for
output voltage noise is keeping the ac closed-loop gain close to many sensitive applications.
unity without compromising the ac performance and dc closed- DC OUTPUT
12644-001
ADJUSTABLE LDO NOISE VRN
Rev. 0 | Page 1 of 8
AN-1329 Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1 LDO PSRR......................................................................................5
Revision History ............................................................................... 2 Improving PSRR ............................................................................6
Noise in LDOs ................................................................................... 3 Transient Load Improvement ......................................................7
Reducing LDO Noise ................................................................... 3 Effect on Start-Up Time ...............................................................7
Examples of LDO Noise .............................................................. 4 Summary ............................................................................................8
Noise Reduction Network ............................................................... 5
Design Example of Using the Noise Reduction Network with
the ADP7142 ................................................................................. 5
REVISION HISTORY
10/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
Application Note AN-1329
NOISE IN LDOS
GAIN
The major sources of intrinsic noise in LDOs are the internal
reference voltage and the error amplifier.
Modern LDOs operate with internal bias currents of a few OPEN-LOOP
GAIN
hundred nanoamperes to achieve quiescent currents of 15 μA or
less. These low bias currents require the use of large value bias
CLOSED-LOOP
resistors, up to 1 GΩ in value. Operating at low bias currents GAIN
results in a noisier error amplifier and noisier reference voltage
circuits in comparison to their discrete counterparts.
A typical LDO uses a resistive voltage divider to set the output 0dB
voltage. Therefore, the ac closed-loop gain is equal to the dc
12644-003
closed-loop gain plus one. The noise gain of the error amplifier
is also equal to the ac closed-loop gain.
f0dB FREQUENCY
REDUCING LDO NOISE UNITY-GAIN
FREQUENCY
There are two major methods for reducing the noise of an LDO. Figure 3. LDO Closed-Loop and Open-Loop Gain Frequency Response
Filter the reference Reducing the noise gain of the error amplifier can result in an
Reduce the noise gain of the error amplifier LDO whose output noise does not significantly increase with
output voltage. Unfortunately, reducing the output noise is
Some LDOs allow the use of an external capacitor to filter the
generally not possible for fixed output LDOs because there is no
reference. In fact, many ultralow noise LDOs require the use of
access to the feedback node. Fortunately, the feedback node is
an external noise reduction capacitor, usually denoted as CBYP in
readily accessible in adjustable output LDOs.
the application schematic, to achieve their low noise specifications.
GAIN
The drawback of only filtering the reference is that the error
amplifier noise and any residual reference noise are amplified
by the closed-loop gain, resulting in noise that is proportional OPEN-LOOP
GAIN
to the output voltage.
Figure 2 shows the noise spectral density of the ADP125 set to
CLOSED-LOOP
output voltages of 500 mV, 1 V, 2.5 V, and 4 V. The results indicate GAIN
12644-004
1V
NOISE SPECTRAL DENSITY (nV/√Hz)
2.5V
1k 4V
fZERO f0dB FREQUENCY
NOISE REDUCTION UNITY-GAIN
NETWORK ZERO FREQUENCY FREQUENCY
1
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Rev. 0 | Page 3 of 8
AN-1329 Application Note
1VDC 100k
DC CNR UNITY GAIN (500mV)
SOURCE 1µF 3V
RFB2
100kΩ 1k
ERROR 100
12644-005
AMPLIFIER
VREF = 500mV
10
Figure 5. Reducing Noise Gain in an Adjustable LDO
12644-007
Figure 5 shows a 1 V output adjustable LDO where RFB1 and RFB2 1
set the output voltage. Reducing the noise gain of the error 1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
amplifier is accomplished with RNR and CNR. Some LDOs have a
low phase margin or are not stable at unity gain; therefore, RNR Figure 7. Noise Spectral Density of the ADP171 Adjustable LDO
is arbitrarily chosen to set the high frequency gain of the 100k
UNITY GAIN (500mV)
amplifier to approximately 1.1. The value of RNR can be adjusted 3V
12644-008
spectral density is evident. In all cases, there is a significant 1
1 10 100 1k 10k 100k 1M 10M
reduction in noise performance between 20 Hz and 10 kHz and FREQUENCY (Hz)
even up to 50 kHz for some LDOs.
Figure 8. Noise Spectral Density of the ADP1741/ADP1753/ADP1755
The noise spectral density of the adjustable LDOs in unity gain Adjustable LDOs
is also plotted on the same graphs for comparison. Above the 10k
zero created by RFB1 and CNR, it is clear that the noise UNITY GAIN (1.22V)
9.3V
characteristic of the adjustable LDOs with the noise reduction
NOISE SPECTRAL DENSITY (nV/√Hz)
10k
4V
UNITY GAIN (500mV)
NOISE SPECTRAL DENSITY (nV/√Hz)
1k
10
100
12644-009
1
1 10 100 1k 10k 100k 1M 10M
10 FREQUENCY (Hz)
1
1 10 100 1k 10k 100k 1M 10M Note that the noise spectral density curves, with and without
FREQUENCY (Hz) the noise reduction network, converge above 20 kHz. This is
Figure 6. Noise Spectral Density of the ADP125 Adjustable LDO because the closed-loop gain of the error amplifier meets the open-
loop characteristic of the amplifier, and no further reduction in
noise gain is possible.
Rev. 0 | Page 4 of 8
Application Note AN-1329
where RPAR is a parallel combination of RFB1 and RNR. 12V NOISE REDUCTION
12V NO NOISE REDUCTION
12644-010
GND
10
Figure 10. Noise Reduction Modification
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Based on the component values shown in Figure 10, the 1
1 10 100 1k 10k 100k 1M 10M
ADP7142 circuit has the following characteristics: FREQUENCY (Hz)
• DC gain of 10 (20 dB) Figure 11. ADP7142 6 V and 12 V Output Voltage with and Without Noise
• 3 dB roll-off frequency of 1.75 Hz Reduction Network
• High frequency ac gain of 1.099 (0.82 dB) LDO PSRR
• Theoretical noise reduction factor of 9.1 (19.2 dB)
PSRR is a measure of how well a circuit suppresses or rejects
• Measured rms noise of the adjustable LDO without noise
extraneous signals (such as noise and ripple) appearing at the
reduction of 70 µV rms
power supply input, which keeps these unwanted signals from
• Measured rms noise of the adjustable LDO with noise corrupting the output of the circuit. The PSRR of a circuit is
reduction of 12 µV rms
• Measured noise reduction of about 15.3 dB VE IN
PSRR = 20 × log
(3)
VEOUT
Note that the measured noise reduction is less than the
theoretical noise reduction. Figure 11 shows the noise spectral where VEIN and VEOUT are the extraneous signals appearing at
density of an adjustable ADP7142 set to 6 V and 12 V, with and the input and output, respectively.
without the noise reduction network. The output noise with the For most circuits, such as ADCs, DACs, and amplifiers, this
noise reduction network is approximately the same for both PSRR applies to the pins that supply power to the inner
voltages, especially for frequencies above 100 Hz. workings of the circuit. However, an LDO input power pin
The noise of the 6 V and 12 V outputs, without the noise supplies power to the internal circuitry and the load current of
reduction network, can differ by a factor that ranges from 2 kHz the regulated output voltage.
to approximately 20 kHz. If the noise is above 40 kHz, the
closed-loop gain of the error amplifier is limited by its open-
loop gain characteristic. Therefore, the noise contribution from
Rev. 0 | Page 5 of 8
AN-1329 Application Note
IMPROVING PSRR 0
NO NOISE REDUCTION
Another benefit of using a noise reduction network to reduce NOISE REDUCTION
the output noise of an adjustable LDO is that the low frequency –20
PSRR (dB)
1/(RFB1 × CNR). It also has a pole at approximately 1/(RNR × CNR).
The lead lag network acts as a feedforward function in the
–60
feedback loop, which improves the PSRR of the LDO. For
frequencies below the point where the LDO closed-loop gain
and open-loop gain converge, the amount of PSRR improvement, –80
in dB, is approximately
12644-013
R –100
20 × log 1 + FB1 1 10 100 1k 10k 100k 1M 10M
RNR
FREQUENCY (Hz)
Figure 13. PSRR of the ADP171 Adjustable LDO With and Without a Noise
Figure 12 to Figure 15 show the effect of the noise reduction Reduction Network
network on the PSRR of several adjustable LDOs. The PSRR 0
improvement for frequencies that range from 10 Hz to about NO NOISE REDUCTION
20 kHz is between 15 dB and 20 dB. For example, Figure 15 NOISE REDUCTION
compares the PSRR of a 9 V adjustable LDO, one with the noise –20
CNR = 1 μF. The zero created by RFB1 and CNR is about 2.5 Hz and
is evident by the improvement in the PSRR that is above 10 Hz.
–60
The overall PSRR improvement is about 17 dB, when the fre-
quency ranges from 100 Hz to 1 kHz. The PSRR improvement
decreases until about 20 kHz, which is when the LDO open- –80
12644-014
0 –100
NO NOISE REDUCTION 1 10 100 1k 10k 100k 1M 10M
NOISE REDUCTION FREQUENCY (Hz)
–20 Figure 14. PSRR of the ADP1741/ADP1753/ADP1755 Adjustable LDO With
and Without a Noise Reduction Network
0
–40
PSRR (dB)
NO NOISE REDUCTION
NOISE REDUCTION
–20
–60
–40
PSRR (dB)
–80
12644-012
–60
–100
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
–80
Figure 12. PSRR of the ADP125 Adjustable LDO With and Without a Noise
Reduction Network
12644-015
–100
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Rev. 0 | Page 6 of 8
Application Note AN-1329
TRANSIENT LOAD IMPROVEMENT is about 600 μs. Adding a noise reduction network with CNR =
The noise reduction network can also improve the transient 10 nF increases the start-up time to 6 ms. With CNR = 1 μF, the
load response of the LDO. Because RFB1, RNR, and CNR (see start-up time is 600 ms. The increase in the start-up time is not
Figure 5) perform a feedforward function in the feedback loop an issue for applications that do not switch the LDO off and on
of the LDO, high frequency components of the transient load after the circuit is fully powered.
are fed to the error amplifier without attenuation. This allows T
12644-018
CH2 1.00V B
W M 200µs A CH2 1.20V
1
T 12.40%
2
12644-016
12644-019
CH2 1.00V B
W M 1.00ms A CH2 1.20V
T 12.40%
1
Figure 19. Start-Up Time of the ADP125 Adjustable LDO with a Noise
Reduction Network, CNR = 10 nF
2
12644-017
Rev. 0 | Page 7 of 8
AN-1329 Application Note
SUMMARY
In general, the noise, the PSRR, and the transient load architecture when used in adjustable mode. However, these
performance of an adjustable LDO can be greatly improved LDOs set the error amplifier in unity gain and make the
with the addition of a simple RC network. Noise sensitive reference voltage equal to the output voltage, which ensures that
applications, such as high speed clocks, ADCs, DACs, VCOs, the output noise is nearly independent of output voltage. When
and PLLs, can benefit from the use of adjustable LDOs with an using these LDOs in adjustable mode, it is best to select a fixed
added noise reduction network. output voltage version that is somewhat less than the desired
This technique only works for adjustable output voltage LDOs voltage to ensure that the dc gain of the error amplifier is kept
with architectures similar to the one shown in Figure 5. A as close to unity as possible.
defining characteristic of this architecture is that the output Ultralow noise LDOs, such as the ADM7150, ADM7151,
noise scales with the output voltage. This is evident in Figure 5 ADM7154, and ADM7155, do not benefit from the use of a
because both the reference voltage and the error amplifier noise noise reduction network. Their architecture places the LDO
are increased by the ratio of approximately R1:R2. error amplifier in the unity gain, which means that the reference
Older adjustable LDOs, such as the ADP123, ADP125, voltage is equal to the output voltage, much like the newer
ADP171, ADP223, ADP323, ADP1741, ADP1753, ADP1755, LDOs mentioned previously. The error amplifier in these
ADP7102, ADP7104 and ADP7105, share this general designs has very low noise and an internal filter with a pole well
architecture and benefit greatly from the use of a noise below 1 Hz heavily filters the reference voltage. The combina-
reduction network. tion of these two design elements virtually eliminates noise at
the output of the LDO.
Newer LDOs, such as the ADP7118, ADP7142, ADP7182,
ADM7170, ADM7171, and ADM7172, share a similar
Rev. 0 | Page 8 of 8