MODUL 1

Hardware Design

Test Project document

LKS_2018_HWD_EN
Submitted by:
Name : LKS Jateng Team
Member Country : Indonesia
Type : Close Project
Time : 8 Hours
Point : 45 Points

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 Contents
This Test Project proposal consists of the following documentation and files:
1. LKS_2018_HWD_EN.doc

Introduction
This Hardware Design Project will access each competitor’s skill and capacity.
1. Competitor can design a circuit of product based on the given drawing and
instruction.
2. Competitor can design Printed Circuit Board using Altium Designer CAD tool (Altium
designer 16/17/18).
3. Competitor can complete his product with enough functions.

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 Description of project and tasks
a) Part1: Circuit Design and Schematic Capture
You are to complete 7 designs. Please complete the designs according to the
requirements. Use only components from the parts list for your designs. You may not
need all the components in the parts list.
Competitors can’t use Simulation tool.
Competitors can read component data sheet that is provided with only personal
computer which contains Data sheet pack. The data sheet pack should be provided
by Committee. The hard copies brought by competitor can’t be used, but competitors
can read the hard copies provided with committee. When you have completed your
designs you are to submit your answers on the provided Answer Sheets to the expert.
You cannot do this until the 1st hour has passed. You will then be given the schematic
solution for schematic entry into Altium. You cannot start your PCB design in this
phase of the test project.

b) Part2: Design of Printed Circuit Board,

 Design printed circuit board of PCB using Altium Designer CAD tool.
 Complete the designs, save PCB in the Desktop
File folder : LKS_HWD_NoTable
File Project name : LKS_HWD_NoTable
- Please use track widths (including necked track) of 0.3 mm (11.811mil)
minimum for signal and 0.6 mm (23.622) minimum for power and a minimum
clearance of 0.3mm (11.811mil), Minimum pad 1.5 mm.
 There must be clearly difference size of track for both signal and power.
 Board dimension of 100 x 160 mm is to be used
 Follow the following design rules:
- Design rule: Pad – Pad clearance is 0,4mm
- Design rule: Pad – Trace clearance is 0,3mm
- Design rule: Trace – Trace clearance is 0,3mm
 You are to place the components as shown in Figure 2 (page 6).
 Compelete the design, save the following PCB Gerber file in the USB stick.

- PCB Top Layer. pdf (scale 1:1)

- PCB Bottom Layer.pdf (scale 1:1)
- Component Placement Side bottom overlay.pdf (scale 1:1)
- Component Placement Side top overlay.pdf (scale 1:1)
- All schematics. pdf

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 c) Transfer PCB, Etching, Drilling PCB
• Transfer PCB sistem manual/automatic.
• Etching PCB.
• Driling PCB sistem manual/automatic.

d) Build and Test Hardware design project

 Assemble PCB, and check its operation.
 Completing the project, submit all the product and documents.

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 Instructions to the competitor

This circuit is the control speed motor simulation. This circuit has 4 speed control and Motor
is simulated using led bit 8. Speed of rotating led, according to the speed shown on display
seven segment. See table below for description of speed and condition of display seven
segment:
Seven
Speed Led Move
Segmen
0 Stop
1 4,25 Hz
2 8,5 Hz
3 34 Hz

There are three buttons for operating this circuit:

Up button to increase motor speed, down button to decrease motor speed, and stop button
to turn off motor.

Block diagram

Figure 1. Block diagram

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 Pcb design 100x160 mm

Size ± 0,2 mm

Figure 2. PCB Place

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 Parts List

NO Qty. Value / Tipe Part Information

1 1 IC NE555 DIP
2 2 IC 7408 DIP
3 1 IC 7432 DIP
4 1 IC 7493 DIP
5 2 IC 4027 DIP
6 1 IC 74193 DIP
7 1 IC 4511 DIP
8 1 IC 74138 DIP
9 2 IC 7404 DIP
10 8 LED GREEN 5mm DIP
11 3 Push Button Push Button 2 Pin
12 1 Terminal Block Terminal Block 2 Pin
13 3 7 Segment 0.56" Common Catode DIP
14 17 100nF Monocap
15 Standard Capasitors DIP
16 8 1 KΩ ¼ Watt 1%
17 1 470 Ω ¼ Watt 1%
18 2 10KΩ ¼ Watt 5%
19 1 1K8 ¼ Watt 1%
20 Standard Resistors ¼ Watt 1%
21 4 Spacer 10 mm

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 OTHERS
Answer Sheet
Name Competitor Competitor Table No. Approval by Jury

ASSIGNED NO. / CODE

To be written by Juri for Marking

purpose

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 #DESIGN 1
Calculate to determine R1, R2, and C1 for square wave generator circuit below to generate
a signal with 37,42ms ± 1ms of period and duty cycle of 59,26% ± 1%.

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 #DESIGN 2
Design controller circuit based on the function table below.
(Suggested component: 4027)

IN OUT
LABEL CLOCK CLK_1 CLK_2 CLK_3
VALUE 68 Hz 34 Hz 8,5 Hz 4,25 Hz

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 #Circuit 3
Design controller circuit based on the function table below.
(Suggested component: 7408 and 7432)

OUT
LABEL EN_3 EN_2 EN_1 CLOCK_SEL
0 0 1 CLOCK_SEL = CLK_1
VALUE 0 1 0 CLOCK_SEL = CLK_2
1 0 0 CLOCK_SEL = CLK_3

0= LOW Level, 1 = HIGH Level,

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 #DESIGN 4
Design controller circuit based on the function table below.
(Suggested component: 7404 and 7408)

LABEL Q1 Q0 EN_1 EN_2 EN_3

0 0 0 0 0
0 1 0 0 1
VALUE
1 0 0 1 0
1 1 1 0 0

0= LOW Level, 1 = HIGH Level,

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 DESIGN 5
Design controller circuit based on the function table below.
(Suggested component: 7493 and 7404)

IN OUT
CLOCK_SEL RESET A2 A1 A0
↑ 1 0 0 0
↑ 1 0 0 1
↑ 1 0 1 0
↑ 1 0 1 1
↑ 1 1 0 0
↑ 1 1 0 1
↑ 1 1 1 0
↑ 1 1 1 1
X 0 0 0 0

↑ = LOW-to-HIGH CP transition
0= LOW Level, 1 = HIGH Level, X = don’t care

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 #DESIGN 6
Design controller circuit based on the function table below.
(Suggested component: 74138, LED (8), Resistor (8))

IN OUT
A2 A1 A0 LED 8 LED 7 LED 6 LED 5 LED 4 LED 3 LED 2 LED 1
0 0 0 OFF OFF OFF OFF OFF OFF OFF ON
0 0 1 OFF OFF OFF OFF OFF OFF ON OFF
0 1 0 OFF OFF OFF OFF OFF ON OFF OFF
0 1 1 OFF OFF OFF OFF ON OFF OFF OFF
1 0 0 OFF OFF OFF ON OFF OFF OFF OFF
1 0 1 OFF OFF ON OFF OFF OFF OFF OFF
1 1 0 OFF ON OFF OFF OFF OFF OFF OFF
1 1 1 ON OFF OFF OFF OFF OFF OFF OFF

0= LOW Level, 1 = HIGH Level,

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 #DESIGN 7
Design controller circuit based on the function table below.
(Suggested component: 74193, 4511, Seven segment, resistor)

IN OUT
UP DOWN RESET SEVEN SEGMENT
↑ 1 1 COUNTER UP If value display > 3, then value display = 0
1 ↑ 1 COUNTER DOWN If value display <= 0, then value display = 0
↑ 1 0 RESET value display = 0
1 ↑ 0 RESET value display = 0

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 Additional schematic

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 1 2 3 4 5 6 7 8

VCC VCC VCC VCC VCC VCC

R1
??
U1A
1
Q0 3
U2 2 EN1

9
7
9
7
7 8 Q1
A DISC VCC U3A U3B U4A U4B A
4 10 15 6 1 10 15 6 1 7408
R2 6 RST J SET Q J SET Q J SET Q J SET Q
THR U5A
?? 2 3 13 3 13 3 U1B
TRG OUT CLK CLK CLK CLK 1 2 4
6
1 5 5 EN2
GND CVOLT 11 14 5 2 11 14 5 2
K RST Q K RST Q K RST Q K RST Q 7414
7408
NE555 U5B
4027 4027 4027 4027 U1C

4
4
3 4 9

12
12
C1 8
?? 10 EN3
7414
CLK1 CLK2 CLK3 7408

GND GND

U6A
GND 1
CLK1 3
2
EN1
U7A
7408 1
3
2
U6B U7B
4 4
CLK2 6 7432 6
5 5 CLKSL
EN2
7408 7432
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U6C
9
CLK3 8
10
EN3
7408
VCC
2
B 1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 B
TB1 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
R3
VCC VCC VCC
1K
D1 R4
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
U5E
U8 1K
11 10 2 5
RST R0(1) VCC D2 R5
3
R0(2) U9
7414 4 16
LE VDD
14 12 1K
CKA QA
1 9 1 15 D3 R6
CLKSL CKB QB A0 Y0
8 2 14
QC A1 Y1
10 11 3 13
GND QD A2 Y2 1K
12
S1 S2 S3 S4 Y3 D4 R7
7493 6 11
OE1 Y4
5 10
OE2 Y5
9 1K
Y6
8 7 D5 R8
GND Y7
GND
74138
1K
VCC VCC VCC D6 R9
GND GND GND GND
Spacer Spacer Spacer Spacer
GND 1K
D7 R10
C R11 R12 C
10K 10K SW1 C16 VCC VCC 1K
100nF D8
VCC
Q1
Q0
U10
11 16
RST LD VDD U
4 5 16
DWN DOWN LE VDD
5 13 4
UP UP BORROW BI
14 12 3 13 7 8
CLR CARRY LT a a C
12 6 3
b b C
15 3 7 11 4
A QA A c c
1 2 1 10 2 R13
U11A U11D B QB B d d
10 6 2 9 1 470
1 2 9 8 C QC C e e
UP 9 7 6 15 9
D QD D f f
14 10
7414 7414 8 8 g g
GND GND 5
R14 DP
SW2 C17 SW3 C18 U11B U11E 74193
1K5 4511 DS1
100nF 100nF 3 4 11 10
DWN
GND
7414 7414
U11C
5 6 GND
RST GND
7414
D GND GND GND D

Title

Size Number Revision

A3
Date: 28/09/2018 Sheet of
File: D:\LKS Jateng 2018 Drawn By:
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