IEEE Transactions on Power Apparatus and Systems, Vol. PAS-98, No.

3 May/June 1979 795

THE DESIGN AND TEST OF A DIGITAL RELAY FOR TRANSFORMER PROTECTION

R. R. Larson, Student Member, IEEE A. J. Flechsig, Member, IEEE E. 0. Schweitzer, Member, IEEE
Western Gear Corporation Electrical Engineering Dept. Electrical Engineering Dept.
Everett, WA Washington State University Ohio University

ABSTRACT tions or determine F2/Co by left-shift and

The inrush current-detection algorithm for the perhaps some addition operations.
protection of transformers presented in [3] was coupled 4. If F2 > g0Fl, then declare inrush conditions
with a differential overcurrent algorithm and imple- exist; otherwise do not block the fault
mented on a popular eight-bit microcomputer system. declaration.
Multiplication and division was avoided, enabling the
use of relatively low-cost processing hardware. A DIFFERENTIAL OVERCURRENT ALGORITHM
hardware model centered around a transformer generated
current data for the data acquisition system. This Before this inrush current-detection algorithm can
be invoked during a particular sample period, it must
system translated the time-continuous analog data into
be determined whether the differential current is large
the time-discrete digital input data for the algorithms
resident in the microcomputer. The algorithms, oper- enough to indicate the possibility of a fault. Under
ating in real time, provided outputs correctly, indi- normal operating conditions, the transformer primary
current is approximately equal to the secondary cur-
cating the presence of either inrush, fault, or low
rent, appropriately adjusted by the turns ratio. Thus,
differential current conditions.
the difference between these currents is small. If a
INTRODUCTION fault internal to the transformer occurs, then these
currents are no longer equal and a large differential
Digital protection of transformers has been imple- current results. The differential current can be
mented by several research groups on a test basis. compared to a threshold which is a function of the
Most schemes have required the use of a fast processor magnitudes of the primary and secondary currents. If
incorporating hardware for multiplication. This paper the differential current exceeds the threshold, then an
reports an implementation of transformer differential internal fault may exist; if the differential current
protection which blocks tripping during inrush using is less than the threshold, then it can be concluded
the economical Motorola MC6800 microprocessor and that the transformer is operating normally.
supporting system, without a hardware multiplier. When the transformer is energized, large differ-
Theoretical development and testing via computer simu- ential currents may exist. Thus, the inrush current-
lation for the inrush current detection algorithm used detection algorithm is employed when the differential
in this implementation was given in [3].
current exceeds the threshold mentioned above to deter-
A summary of the algorithm is as follows. mine if the differential current is due to an internal
1. Calculate the digital filter outputs using fault or to inrush current.
time-discrete differential current samples, The variable threshold is used to prevent tripping
im, sampled N times per cycle: on differential currents resulting from the magnetiza-
k-N/2 tion current, from current transformer (CT) dissimilar-
ities, or variable ratios of transformation (e.g., tap
S1(k) = I [im im+N/2 (1)
changing transformers).
m=k-N+l
One error source is the linearity of the CT's. If
k-3N/4 the primary and secondary CT's are not well matched in
Cl(k) = I [im -
(i m+N/4 + im+N/2) im+3N/4 linearity, then a substantial differential current may
m=k-N+l result. Suppose the linearity is expressed as ±lOOe%,
k-3N/4 and assume the primary current Ip equals the secondary
s2(k) =

m=k-N+l
[im -
im+N/4 + im+N/2 im+3N/4 current Is. Then the maximum differential current,
IDMAX, may be expressed as
k-7N/8 IDMAX = (1 + e)Ip - (1 -
e)IS (5)
C2(k) =
k mN+l ( m+N/8 + im+N/4 ) m+3N/8
when no internal fault is present.
m+N/2 ( m+5N/8 m+3N/4) m+7N/8] ) If a variable-ratio transformer is considered, and
if the relay has no knowledge of the tap setting, then
where the filter outputs are calculated at the k-th an additional source of error is incurred. Let 1/(1 +
sample period. a) be the per-unit turns ratio of the transformer.
Equation (5) is easily modified to include this source
2. Set
denotes
F1 =
the
max(ISl,1ClI),
larger of a
where
and b.
max (a,b)
Set F2 = of error:
max(IS21 IC21)C DMAX (
(+ -(l -e)
P (1 + a) S
2e +a +ea1 6
1 + a P
3. Using the inrush current criterion threshold,
of Furthermore, the measured value of the sum of the cur-
60, determine tOF1 by a small number
right-shift and perhaps some addition opera- rent magnitudes, IE, is
(1+eI1
=(l+ )p +1l-e+ a 2 +a +ea1
a p (7)
Therefore,
2e + a + ea I
I
DMAX
=

2 + a + ea Z (8)
F 78 688-4. A paper reccmnended and approved by
the IEEE Pcwer System Relaying Cawuittee of the IEEE As an example, suppose a high-quality CT with a
Pcoer Engineering Society fcr presentaticn at the IEEE 2.5% linearity to 20 times rated current is used with a
PES Sunmer Maeting, Los Angeles, CA, July 16-21, 1978 ±10% tap ratio transformer. Then e = 0.025 and a = 0.1
Manuscript submitted February 8, 1978; made and
available for printing April 25, 1978. IDMAX =
.0725IE = 0.139Ip (9)

0018-9510/79/0500-795$00.75 1979 IEEE

796
As currents through the CT's increase, eventually
one or both saturates. Serious differential current
measurement errors result if they do not saturate
simultaneously.
In general, let the primary CT saturation current
level be IpS, and the secondary CT saturation level be
Iss. Assume IPS > Iss and Ip = Is. Then the differ-
ential current ID may be expressed:

For IpP < ISSS

= I - IS= For ISS < Ip IPS
=
IPS ISs - For Ip > IPS' (10)
Thus, when neither CT is saturated, the differential
current is zero; when one CT is saturated, the differ-
ential current is proportional to the current provided
by the other CT; and when both CT's are saturated, the
differential current is constant and equal to the
difference in saturation levels of the two CT's.
One more normal source of differential current
must be considered. Under full load conditions, the Fig. 1. Flowchart for Differential
magnetization branch current, IM, is typically about 3% Overcurrent Algorithm.
of the primary current, and contributes very little to
the differential current. However, if the transformer Figure 2 shows the differential current character-
is unloaded, then the differential current equals IM. istic actually used in this implementation. In this
Thus, the minimum possible value of a threshold against
which the differential current can be compared is IM.
IM constitutes the true differential current under
normal conditions. Thus, the only difference in phase
or magnitude of Ip and Is is the normally small current
IM. When IM is not small, inrush conditions exist,
with the attendant higher harmonics.
The differential algorithm presented here was I.,.
proposed by Rockefeller [5] and was used to allow for
the measured differential current due to conditions
described above (i.e., that not caused by an internal
fault or inrush current). ID is compared with IE ac-
cording to a two-piece piecewise-linear threshold
characteristic, which can be positioned arbitrarily
close to the maximum error boundaries on the ID,IE
plane. Furthermore, in a digital computer implementa-
tion, the two segments can be readily adjusted to match IT lIpl+ I, pw wut
the CT characteristics of any given application by
minor software modifications. Fig. 2. Differential Overcurrent Algorithm Trip Char-
acteristic as Used in Transformer Algorithm
Assume that the first straight line segment is Test.
employed for ID 4< Il, where I1 is the value of differ-
ential current at the breakpoint between the two de- case, Io
0.25 p.u., I1 = 0.625, I2 = 14.0 p.u., k1 =
=
sired line segments. Let the slopes of the first and 0.25, and
= 0.50. k2Great allowance was made for
second line segments be kl and k2, respectively, with dissimilar CT saturation and other measurement errors.
The characteristic could be made much more sensitive to
k, < k2. Then the equation for the first line segment lower current faults by reducing kl and increasing Il,
is
involving simple software changes.
ID = klI (11)
where In computer application, the data must be sam-
a
IE = il
p +I S I). pled. If the sampling is performed without regard to
the phase of the currents, then some error in the
When ID = I, I = Il/kl; thus, the equation for estimation of the peak current values is incurred. The
the second line segment is error depends on the sampling rate. For a sampling
rate of eight samples per cycle, the samples are spaced
I1
ID = k2(I -j ) + 450 apart. The maximum angular separation between the
D 2 k1) 1 (12)
(2 peak current and the closest sample to the peak is
therefore 22.50. The estimate of the peak could be as
A flowchart for the algorithm is shown in Fig. 1. low as 0.924 of the true peak. This is not a serious
The differential current is first compared with the error, although it must be taken into account when the
minimum fixed threshold Io. If it is above IO then it positions of the boundaries, such as Io in the dual-
is tested to determine if instantaneous tripping is slope algorithm, are chosen.
required. If ID < I2, then ID is compared to the
appropriate boundary (11) or (12). If ID is above one HARDWARE TEST SYSTEM
of the boundaries, then the inrush algorithm is in-
voked to determine if the apparent fault current could A hardware system was designed and constructed to
have resulted from inrush current. facilitate testing of the transformer protection algo-
rithms. Figure 3 is a general block diagram of the im-

Thresh
of Transformer Algorithm
Fig. 3. Block Diagram
System.
plemented system. There are three major elements: the
transformer, processor (computer and data-conversion
subsystem), and controller.
Transformer Model
To provide inrush current and fault current data
for testing the algorithm, a model system was con-
structed as shown in Figure 4. A 500 VA isolation
Controller,
Test
Transformer Triac; Test
To 0o
Channel I Channel 2
Fig. 4. Model System for Inrush and Fault
Current Data.
transformer is provided with low-resistance current-
measurement shunts on its primary and secondary.
During inrush tests, the transformer is energized by
the 120 VAC power line when the triac in the Controller
is fired. The Controller allows energization at any
desired voltage angle. Faults are applied using the
triac in the Controller so that faults at selectable
voltage angles can be studied. External faults are
simulated by applying faults to the load side of the
secondary shunt, while internal faults are simulated by
faulting directly across the secondary terminals.
Processor
The heart of the processor is a computer supplied
by Bonneville Power Administration in which the algo-
rithms are implemented. The processor provides isola-
tion from the power system, analog signal conditioning,
and analog to digital conversion of the conditioned
inputs. This portion of the system was designed and
constructed by the authors.
Analog Signal Conditioning
Isolation and Amplitude Conversion: Resistive
shunts were used to provide amplitude conversion from
the transformer model currents to the processor analog
signals. Isolation was needed to prevent the potenti-
ally high model voltages from damaging the processor
electronics. A printed circuit card was designed and
constructed to provide up to ±2500V isolation. The
module modulates the input, passing the result through
a transformer, then synchronously demodulates and
filters the output. An operational amplifier on this
card scales and buffers the output.
Sample Clock: A sampling frequency of 480 Hz
(N=8 samples per cycle) was chosen to satisfy digital
processing considerations for the transformer algo-
rithm. The criteria for choosing the sampling rate
included the need to (1) attenuate all signals greater
than the Nyquist frequency, (2) minimize attenuation of
797
the highest frequency used in digital analysis, 120 lIz
(for a 60-Hz power system), and (3) allow adequate
transformer algorithm execution time.
Nyquist's sampling theorem requires that the
sampled signal be band-limited to one half the sampling
frequency, or 240 Hz, to avoid aliasing. A frequency
component at 240 + £ Hz appears as a 240 - £ Hz compo-
Fault Relay nent in the samples. In order to implement real-time
Controller protection for a single-phase power system model, the
Test transformer algorithm must be executed once during each
However, to allow for
sample period of 1/60N seconds.
implementation for a three-phase system, the sample
period must be long enough to allow at least three
successive executions of the single-phase algorithms.
With N=8 and with the microcomputer hardware (using a
1-MHz clock) described subsequently, the maximum trans-
former algorithm execution time is 597 psec, (less than
one-third of the sample period, 694 psec). Hence there
is adequate time between samples to execute a three-
phase version of the algorithm. A greater sampling
frequency would increase the execution time required,
because the execution time of the digital filter por-
2 tion of the transformer program is proportional to N.
At the same time, the sample period is reduced, preclu-
ding real-time protection for N>8. It was computed
that for N=12, the clock rate on the microprocessor
would have to be increased to at least 1.55 MHz.
Low-Pass Filter: Data on only the 60 Hz and
120 Hz components of the differential current are de-
sired for the transformer algorithms, and a sampling
rate of 480 Hz allows the use of a low-pass filter with
a cutoff frequency greater than 120 Hz. Thus, the
difficulty in processing data for N>8 is not warranted.
A four-pole Chebychev low-pass filter was implemented
to attenuate signals that would cause aliasing. Op-
erational amplifiers were utilized to provide 3 dB
attenuation at 167 Hz with 20.9 dB attenuation at
240 Hz compared to the gain of 4 V/V at DC.
Sample and Hold: The signals being digitized must
be held constant during the conversion process. An
impulse sampler with a voltage holding circuit was
used to meet this requirement for each channel.
Multiplexer: Two current samples, primary, ip(t),
and secondary, is(t), are sampled simultaneously during
each sample period. The two current signals are multi-
plexed to eliminate the need for two relatively expen-
sive A/D converters. This is accomplished using FET
analog switches controlled with bipolar logic.
Analog To Digital Converter
An A/D converter is used to give a 12-bit resolu-
12-bit
tion output from a ±1OV analog input range.
resolution satisfies the requirement that round-off
error in the current samples would not cause an errone-
ous output from the inrush current-detection algorithm.
The converter output is in complemented two's comple-
ment form and is complemented again using exclusive or
gates, so that the computer input ports receive the
data in standard two's complement form. Conversion is
accomplished in 20 psec for 12 bits. Operating se-
quence for the converter is described briefly in con-
junction with the computer description.
Microcomputer
The microcomputer is designed around the Motorola
It consists of six printed
MC6800 microprocessor.
circuit boards which plug into a motherboard, a power
supply, and a teletype.
CPU Module: The CPU module contains the micro-
processor, the system clock, and buffers on one board.
798
ROM Module: A single 8k/16k
byte AROM/ROM (Read Only Memory)
Amp
Module is used (1 byte = 8 bits).
The ROM used in the relaying ap- Channel 1
plication described contains the
MICRO-bug Firmware Program. MI-
CRO-bug provides execution con-
trol for debugging programs Channel 2
stored in RAM.
RAM Modules: Two 2k Static
RAM Modules provide a total of 4k
bytes of random-access memory lo-
cated at the bottom of memory. 480HZ
instruction
Eachcated data in
using memory.
at the bottom of ~~~~~Clock
the first 256 locations can be
executed in one less clock cycle
and requires one less program Fig. 5.
memory byte than usual, thus sav-
ing considerable execution time
and memory space. All temporary data storage for the
program are in these locations. In this relay applica-
tion, the program (466 bytes) and data were stored in
RAM so that modifications and debugging could be easily
accomplished. During development these advantages out-
weigh the disadvantage that the RAM is volatile.
program is reloaded via paper tape and the teletype
each time the computer is powered on. In a field ap-
plication, the program would be stored in ROM.
ACIA Module: One ACIA (Asynchronous Communica-
tions Interface Adapter) Module is used to provide an
interface between the teletype and the computer. The
ACIA is used in conjunction with the firmware to allow
bi-directional serial asynchronous data transfer be-
tween the teletype and the MC6800.
Input/Output Module: An Input/Output Module
provides a total of four bytes of I/O between the
computer and external hardware. Two Peripheral Inter-
face Adapters (PIA) are used. Each PIA contains two 8-
bit ports, two control registers, and two data direc-
tion registers. These registers determine the direc-
tion of data transfer and the manner in which the PIA
interacts with the peripherals and the CPU.
Input/Output Control Logic: The A/D converter
output is connected to the two bytes of I/O lines of
one PIA. The control lines (Data Received and Data
Ready in Fig. 5) are programmed to be compatible with
the hardware requirements of the A/D subsystem and with
the software requirements of the algorithm. Two ports
are programmed to provide 16 lines of data input from
the A/D converter to the computer. These lines are
connected to provide correct two's complement represen-
tation of the 16-bit data.
The control sequence for transferring the A/D
converter data to the computer is initiated by a posi-
tive-going transition of the sample clock. At this
time the filtered current signals are sampled and
500 nsec later, the A/D conversion of Channel 1 is
started via the Convert line in Fig. 5. When the con-
version is complete, 20 psec later, a pulse is sent via
the Data Ready line, indicating that the data is avail-
able for processing. When the CPU reads the data from
the PIA ports, a pulse on the Data Receive line causes
the multiplexer to select the Channel 2 current sample
and process it as with Channel 1.
ASR-35 Teletype: The ASR-35 is used as a program
and data I/O device. It connects directly to the ACIA
module and provides keyboard or paper tape input as
well as hard copy and paper tape output.
S/H
LPF: Low-Pass Filter MPX: Two-Channel Multiplexer
S/H: Sample-and-Hold Amplifier A/D: Analog-to-Digital Converter
Processor System for Algorithm Testing.
Controller
A controller was designed and constructed which
provides precisely timed switch closures. It controls
the angle of fault initiation or transformer energiza-
The tion with respect to the voltage applied to its input
terminals. The range is 2.90 to 2300. Two switching
outputs are available, a solid-state triac and a mer-
cury-wetted relay. The triac, capable of handling
40 amp RMS continuously with a 200 amp surge rating,
was used in the transformer tests.
The timer starts timing at the first positive-
going voltage zero at the input following the trigger
pushbutton contact closure. At the end of the timing
interval the triac conducts (delayed 0.1 msec) and the
relay contacts close (delayed 1.2 msec). The relay
contacts trigger an oscilloscope monitoring processor
inputs and outputs. Another timer is used to cut off
the triac trigger after 400 msec, and the triac ceases
conducting at the next current zero, if the auto clear
toggle switch is set to AUTO CLEAR.
Microcomputer Transformer Protection Software
The software stored in the RAM module includes
current data handling routines, differential overcur-
rent and inrush current-detection algorithms.
Figure 6 outlines the software development proce-
dure. After the operations required for the algorithm
are organized via a flowchart, they are coded in MC-
6800 source code mnemonics. The source code becomes
input for the cross-assembler resident in an IBM-360
computer. Hexadecimal object code (descriptive print-
out and paper tape with condensed code format) results.
The microcomputer program is loaded into RAM using the
object code on the tape. Utilizing the MICRO-bug mon-
itor ROM, the program is executed. If it does not per-
form satisfactorily, the object code is altered and
tested. When the debugged program performs success-
fully, the computer system can be used for hardware
testing of the protection algorithms.
Figure 7 gives an overview of the program execu-
tion. Once each sample period, the computer reads the
latest current samples, determines whether the point
(IE,ID) the
lies in the differential overcurrent trip zone
(using algorithm shown in Fig. 2) and if it does,
determines whether the differential current is inrush
or fault current.
After indicating flags are reset, the computer
waits for the control line signals indicating that the
primary and secondary current data are available. This
data is used to calculate ID and IE, which is used in
the differential overcurrent algorithm (see Fig. 1).
 799

I Flowchart or List Operations Desired

Code in Motorola Mlnemonics <

/ Motorola 6800
Input to
Cross-Assembler /

I F ~TAPE
Hex Source
Code and Con ense s Format
Input Print ex Source Co

TTY Input to
M6800 MicroDrocessor

Test rom Program

Operati on s

crogram tiot in
Final Form;
Debug;iM!odi fy lip
/ < Program with TTY

/ erfr °
tSuccessfullue Put Program in
Fi nal Form

a Rrogr de of t e o
Fig. 7. Overview of Transformer Program Operation.
W tihnal Fodo, the signs of S1 and C1 and then either adding or sub-
Program Ready a i
tracting C1 from S1 and comparing the result to zero.
for Ooeration ( a r t s

This requires more code, but eliminates the relatively

time-consuming absolute value operation for two-byte
Microcomputer Program Implemeantation
Fig. 6. numbers. The larger of and IS21 IC21
is similarly
Cycle. determined.
Execution time was saved by storing differential Finally, the estimate of the second-harmonic
current values, ID, to be used in the inrush current- component of the differential current, MAX(1S21,1C21)
detection algorithm, in two redundant eight-zone soft- must be compared to Eo times the estimate of the funda-
ware shift registers, in RAM. The effect is to arrange mental component of the differential current, MAX(1S11,
the latest eight values of ID in an unbroken series of
adjacent RAM locations, in order of their occurrence. IC11), to determine whether the differential current
waveform is due to inrush current or internal fault
When the digital filter outputs Sl, Cl, S2 and C2 are current. The value MAX(1S21,1C21), is shifted to the
calculated, indexed addressing is used to add up the left, saved and added to the results of subsequent
series of locations (with appropriate sign changes as shifting, in effect multiplying MAX(1S21,1C21) by l/Eo.
required by the SAL and CAL filter convolution calcula- Many values of Eo between 0.00 and 0.50 can be found
tions). No testing is required after each addition At least
that require shifting or adding operations.
operation to determine whether the limits of the shift 17 values of Eo in this range can be found that require
register locations have been reached, as would be re- less than or equal to 38 psec to perform this shifting
quired if only a single shift register had been used. and adding. The threshold Eo = 0.25 worked well for
Thus, the elimination of test and branch instructions the tests described in the following; no inrush current
here saves considerable execution time (at least 128 resulted in a value of C less than 0.25, and no inter-
psec per pass), at the expense of adding a few more nal fault current, i, stayed above 0.25. Only two
temporary data storage RAM locations. Without this
shift operations were required in the second-harmonic
time reduction, the program would not be able to pro- estimate.
vide real-time operation.
the filter outputs, advantage is
In calculating
If MAX(IS21,1C21) > EoMAX(IS11,IC1I),
indication, a computer output in the second PIA is set.
the inrush
taken from the fact that Si and Cl (and S2 and C2) have If MAX(1S21,1C21) < MAX(IS1I,IC1I), the fault indica-
similar partial sums. Designating ID1, ID2, ..,ID8 tion computer output, which can be used to initiate a
as the latest eight differential current values, circuit-breaker trip, is set.
Si
S1
=
(I
(DlD
+
IDD2 IDD5 IDD6)) + (I
D3
D
+
ID
D4 IDD7 ID8
D8
TRANSFORMER ALGORITHM IMPLEMENTATION AND TESTS
C1 =
(IDl+ ID2- ID5 -ID6) -
(ID3+ ID4 -
ID7- ID8). Using the microcomputer system, signal condition-
ing hardware, and model transformer, the inrush current
detection algorithm and the differential current algo-
s2 (IDl ID3 D5 D7) ( D2 D4 D6 D8 rithm were implemented and tested. The tests are
categorized into four groups: inrush current only,
ID7) (ID2 ID4 ID6 ID8). internal fault current only, simultaneous inrush and
c2 = (I Dl- ID3 + ID5 - - - + -
fault current, and external fault current.
Next the larger of 1S11 and 1C11, (Max 1S11,1Cl1) The tests were performed to determine: (1) a
must be found. Execution time is saved by determining of coding the algorithms on a micropro-
practical way
800
cessor for real-time protection; (2) the length of time programmed so that it is impossible to declare fault
required for the algorithms to process the current data and inrush simultaneously.
and indicate no fault, fault, or inrush; and (3) deci-
sion validity. Current Input Display
Differential current is displayed on Channel 1 of
Power System Model the oscilloscope. It is produced by subtracting the
The four categories of tests were performed using output of the Channel 2 isolation amplifier from the
five different test configurations (Fig. 4). The output of the Channel 1 isolation amplifier. This
source feeds the test transformer through a shunt. The subtraction is performed by a differential amplifier in
shunt voltage is the ip(t) signal. A shunt in series the oscilloscope.
with the secondary provides the is(t) signal. The
triac is connected to properly implement the appropri- Transformer Algorithm Tests
ate test case. During fault tests, an inductor is Inrush Current Only
connected in series with the source to simulate source
impedance and limit fault current. The performance of the digital protection system
was tested during the heavy currents often present when
Signal Processing and Calibration the transformer is energized. Figure 4, test 1, shows
the configuration of the model power circuit used to
The ip and is signals derived from the shunts perform this test. Under inrush conditions, the abso-
enter the data acquisition system via Channel 1 and 2.
They are isolated, filtered, sampled and converted to
lute value of the flux,
core saturation flux.
141,
can increase beyond the
As a result, the relative per-
12-bit two's complement binary numbers, which are read meability (and hence shunt reactance) decreases from a
into the computer. The two data channels are simulta- large value to nearly po. The average relative permea-
neously sampled at a rate of 480 samples/second. The
bility of the core of the small test transformer is
phase between the sampling waveform and the input quan- estimated to be about 850 at 120 VAC.
tities is not controlled. The amplitude scaling of the
input quantities is given in Table 1. The ratio of the Test Procedure: The unloaded transformer was
Channel 2 to Channel 1 A/D outputs is (0.0372/0.0358) = energized with the switching angle, X, controlled by
1.04 = n1/n2 of the test transformer. the fault controller. Switching angles from 30° to
2100 in intervals of 300, and 2.50 and 2300 were tested.
Table 1. Analog Data Scale Factors for Transformer
Tests The inrush waveform depends upon the switching
angle, circuit impedances, and the remnant flux, fR.
Hexadecimal For a particular AC voltage across the primary, the
Computer In- controller leaves the transformer with one of two equal
put Given but opposite values of remnant flux when the circuit is
Transformer interrupted. Since the triac interrupts the current
A/D Con- only at a current zero, the flux is left at one of the
Shunt V/ Iso Amp Out- verter V/ Current
two points where the major hysteresis loop crosses the
Transfor- put V/Trans- Transfor- 100 i=0 axis.
Data mer Amps former Amps mer Amps 1 Amp Amp
Inrush Test Data: Table 2 lists data taken from
nel l- 0.0654 0.00939 0.0358 $0007 $02DC the oscilloscope traces of the inrush input waveforms
Table 2. Inrush Test Cases, Partial Listing.
Chan- 0.0842 0.00977 0.0372 $0007 $02F9
nel 2
Time to Amplitude
Switching Remnant First of First Base Algorithm
Since the 12-bit converter has 4096 codes in Angle, X, Flux Peak Peak Width -Output
binary two's complement form, the,change of the least
significant bit represents a change in voltage of Degrees cR*
R msec amp msec
(20V/4096) = 4.88 mV.
2.6 +R 8.3 - 3 5 No inrush or
fault
Full scale is defined as 16.0 p.u. current in the
application of the differential current algorithm. The
1.0 p.u. current corresponds to $080 in the computer
2.6 -4Rl 7.1 -109 8.0 Inrush
and 17.46 amp on the primary of the test transformer 60 +4 Rl
R1
14 + 2 --- No inrush or
(assuming secondary current to be zero). The lower fault
bound of the differential algorithm, 0.25 p.u., corre-
sponds to $020 out of the A/D converter and 4.36 amp 60 -4Rl 5.3 - 43 6.4 Inrush
primary current.
120 +Rl 11.0 + 47 7.4 Inrush
Display of Test Parameters and Results
Fault and Inrush Indication
120 -4Rl --- - 1 --- No inrush or
fault
The inrush and fault outputs of the algorithm are
brought out of the microprocessor via a PIA and TTL
180 +R 7.5 +114 8.0 Inrush
inverters to drive two LED's. These outputs are also
used as inputs to Channel 2 of a differential amplifier
180 -Rl 8.5 + 3 3.0 No inrush or
fault
on a storage oscilloscope. If the differential current
algorithm does not sense current samples in its trip 230 +R 5.4 + 54 6.6 Inrush
zone, the inrush algorithm is not invoked, and neither
inrush nor fault is indicated. If the current samples 230 -R 14.1 - 2 1.5 No inrush or
fault
are in the differential algorithm trip zone, and if the
inrush algorithm declares inrush, the Channel 2 trace P (i=0) on 120 VAC, 60-Hz hysteresis loop.
is high. If the inrush algorithm declares a fault, the fR, =

Channel 2 trace is below zero. The inrush algorithm is

 801
and the inrush indication output from the computer. current of 8 amp and a pulse duration of 5.0 msec.
Figure 8 illustrates how the differential current
waveform data were obtained from the oscilloscope In the case of maximum inrush current, the inrush
algorithm was called upon during each sample period
except for those near a current zero, as shown in the
bottom trace of Fig. 9. In the cases where the differ-
ential current barely exceeded the 4.36 amp lower
bound, the inrush algorithm was invoked only near the
current peaks. In all cases where the inrush algorithm
was employed, there was never a false fault declara-
tion; inrush was always declared. Each case listed in
Table 2 was tested at least ten times and the algorithm
output observed for 400 msec after energization. No
Inrush Current Definitions inrush current remained at that time.
iC IF
m c to_
Tests with Fault Current Only
2nd peak
The fault response time of the differential inrush
msec to algorithms was tested for internal transformer faults
Ist peak
after the transformer had been energized for more than
one second.
T Z
og
a's Xh t
Test Circuit Configuration: Figure 4, test 2,
shows the configuration used for the tests. In order
to restrict fault currents below the ratings of the
triac in the controller, a variable autotransformer was
Internal Fault Current Defntions used to reduce the input voltage to 28.5 VAC. Air-core
Fig 8. Measurement of Waveform inductance was added in series with the transformer
Characteristics.
primary to raise the X/R ratio to 2.86. The triac in
the fault controller was connected across the secondary
traces. Figure 9 is a copy of the inrush waveform for of the transformer, inside of the secondary current
X = 1800. measurement shunt, so that the differential current was
essentially the same as the fault current.
In Table 2 for each switching angle X, data are
presented for positive and negative remnant flux. To Test Procedure: Internal fault tests were carried
characterize each waveform, the amplitude and base out with variable switching angle, X. The waveform was
width of the first inrush pulse were measured. This characterized by measuring the amplitude of the first
gives an indication of core saturation. The data shown and second current peaks after the fault was initial-
were taken with an inrush criterion threshold of go = ized and the steady-state peak fault current. The
0.25. method of measurement is shown in Fig. 8. The fault
response time was measured for five trials of each case
shown in Table 3A. Figure 10 is a copy of the X = 900
.2'
case. The top trace is the differential current signal
1 v at the output of the isolation amplifier card. The
bottom trace is zero when the sample current is not in
the trip zone of the differential algorithm; the trace
I I I is high when the inrush algorithm declares inrush, and
msec 10 20 30 40 is low (below zero) when the inrush algorithm declares
a fault.

Test Results: The test results for internal

Fig. 9. Top: Inrush Cur- Fig. 10. Top: Fault Cur- faults only are summarized in Table 3A. The fault re-
rent only, X = 1800. Bot- rent only, X = 900. Bot- sponse time is given as a range of the minimum to maxi-
tom: High--inrush indica- tom: High--inrush indica- mum time required in five trials. In every case, the
tion; zero--not in differ- tion; zero--not in differ- inrush algorithm blocked tripping by declaring inrush
ential trip zone. ential trip zone; below for a short time, then declared a fault in about one
zero--fault indication. cycle after fault initialization. The minimum fault
Analysis of Inrush Only Test Data: In no case did response time was 12.6 msec for X = 900; the maximum
inrush current ever result in a fault declaration from was 19.1 msec for X = 300. The average trip time for
the inrush current detection algorithm. Inrush was all cases was 16 msec after fault initialization. The
always declared and hence E > 0.25 whenever the current tests correlated fairly closely to the FORTRAN simula-
was in the trip zone of the differential algorithm. tion results performed earlier.
During the time intervals when inrush was not declared,
the differential current was not in the trip zone of Simultaneous Internal Fault and Inrush Tests
the differential algorithm. The possibility exists that tripping for an inter-
nal fault may be blocked for longer than one cycle by
Peak inrush currents always occurred on the first the inrush algorithm due to simultaneous inrush. This
inrush pulse after energization. They ranged from a may occur if a fault occurs upon energization of the
low of 1 amp at X = 1200 (also 30°), to a high of transformer. This situation was tested using the test
114 amp at X = 1800. Duration of the initial inrush system.
pulses varied from 2 msec (430) for the smallest inrush
current to 8.0 msec (1730) for the largest inrush Test Circuit Configuration: The test circuit for
current. Since the lower bound for the differential simultaneous inrush and fault current, Fig. 4, test 3,
current algorithm is 4.36 amp, the peak inrush current was similar to that used for inrush, except a heavy
had to be greater than this value for the inrush algo- load (induction motor) was connected across the sec-
rithm to be executed. The smallest waveform that ondary to simulate an internal fault with a small fault
caused execution of the inrush algorithm had a peak impedance. The fault and inrush currents are initiated
802
Table 3. Test Cases
(A)--Fault Only Cases
(B)--Simultaneous Fault and Inrush Cases with Motor Fault Impedance
(C)--Simultaneous Fault and Inrush Cases with Resistor Fault Impedance

Switching First Peak Time to Second Peak Time to Steady-State* Fault Response
Angle, X Amplitude First Peak Amplitude Second Peak Peak Amplitude Mean Range
(degrees) (amps) (msec) (amps) (msec) (amps) (msec) (msec)
(A) Fault Only Cases
2.6 + 9.1 3.6 - 17.6 11.1 15.3 17.7 17.6-18.1
30 + 5.3 2.6 - 18.1 9.6 15.3 18.1 15.6-19.1
90 - 20.0 7.0 + 14.7 15.7 15.3 13.1 12.6-13.9
120 - 17.6 5.7 + 14.9 15.3 15.3 17.9 17.0-18.3
180 - 10.6 3.5 + 17.0 11.3 15.3 17.7 17.1-18.3
230 - 1.1 1.2 + 14.9 8.3 15.3 14.5 14.1-15.5
(B) Simultaneous Fault and Inrush Cases with Motor Fault Impedance
2.6 - 87 7.0 + 38 13.5 37 20.1 19.0-20.5
60 - 38 3.0 + 37 11.0 37 17.2 16.0-18.0
120 - 17 2.3 + 38 8.0 37 19.8 18.5-21.0
180 + 70 7.5 - 37 14.0 37 22.4 20.5-28.0
210 + 61 5.5 - 36 12.5 37 17.7 16.0-19.0
(C) Simultaneous Fault and Inrush Cases with Resistor Fault Impedance
Resistance
(ohms)
180 +115 8 16.0 12.8 48 35 - 63
180 +117 7 32.0 6.9 81 73 - 99
30 - 13 4 16.0 12.8 16.3 16 - 17
30 - 7 4 32.0 6.9 16.7 16 - 17
*
Steady-state current during first 0.2 second (high rotor slip).

when the triac in the controller first conducts. Dur-
ing the first few cycles of fault, the induction motor
slip is almost 1 and the equivalent variable resistance
negligible compared to the fixed impedances. The motor
reaches full speed in about 0.3 sec, at which time the
equivalent variable resistance reaches 22.5Q. The
inrush decays well before the fault current decreases
significantly, due to motor speedup.
Test Results: Table 3B summarizes the results of
the simultaneous fault and inrush test using the induc-
tion motor. Inrush was significant only during the
first two cycles after energization, and it was fairly
small compared to the fault magnitude even during the
second cycle. Fault declaration was delayed only
slightly by the inrush. The largest inrush occurred at
= 2.60. By comparing the fault response time at this
angle with the fault response time at X = 2.60 for
fault only current in Table 3A, this delay is seen to
have a mean of 2.4 msec. At X = 1800, another heavy
inrush case, the mean delay was 4.7 msec. The overall
mean fault response time for simultaneous fault and
inrush was 18.2 msec, 3 msec longer than the mean for
fault only.
Alternate Circuit Configuration: An additional
test of the inrush algorithm was made for the most
difficult condition to detect: a small internal fault
with simultaneous inrush. To test this, the low-
impedance motor of the circuit just described was
replaced with a higher-impedance variable resistor set
to 16 ohms, and 32 ohms. A few selected switching
angles were used, with five trials at each angle. The
test results are summarized in Table 3C. With X = 180°
and the fault impedance set to 16 ohms, the peak inrush
current was nine times the steady-state peak fault
current. The fault response time ranged from 32 msec
to 62 msec, with a mean of 47 msec. With the variable
resistance set to 32 ohms, inrush current peaked at
18 times steady-state fault current, and the algorithm
required between 72 and 98 msec to detect this tiny
fault. With X = 300, there was very little inrush, and
the fault response times were about one cycle.
Thus, only very small faults were substantially
delayed during simultaneous inrush. Fault current of
greater than 6 amps was always declared as a fault in
less than 0.1 sec, despite the large inrush currents.
External Fault Tests
To make sure the differential algorithm does not
respond to external faults, low impedances were at-
tached in series with the secondary of the transformer,
Fig. 4, test 5. Each time when the transformer was en-
ergized, the differential algorithm did not declare a
possible fault unless there was inrush current, in
which case the inrush algorithm declared inrush.
Transformer Algorithm Execution Time
The whole data acquisition process and algorithm
execution time was less than one-third of the time
between samples, 2.08 msec. The time between the
transition of the sample clock and an output of the
microcomputer was measured on the oscilloscope. At the
sample clock transition, the signal level is held in
the sample and hold, and the A/D converter begins its
20-psec conversion almost immediately. Subsequently,
the microprocessor reads the data and initiates the
second conversion while starting computations. At the
completion of the differential algorithm and the inrush
algorithm (if it is used), the processor output is
changed, if necessary. When the differential current
is not in the trip zone, the time between sample clock
transition and processor output change was measured as
180 psec. This time interval increased to a maximum of
570 psec when the inrush algorithm was used. The
maximum possible time for this interval is 630 pisec

based upon the maximum program execution path and the
1.000 MHz clock used for microprocessor timing.
The differential and inrush current detection
algorithms executed correctly in every case tried with
a simple model power system. The algorithms were
executing in real time in the processor and were oper-
ating on data obtained through the signal-processing
system described.
CONCLUSIONS
The differential and inrush current-detection
algorithms executed correctly in real time on an inex-
pensive microcomputer system for every test case pro-
vided by the simple model power system. At no time was
a fault declared during inrush current only tests. The
internal fault trip was initiated a maximum of 19.1
msec after fault initiation when inrush current was not
involved. Even inrush current simultaneous to fault
current did not greatly lengthen the fault response
time unless the fault current was small. Hardware
required to pre-process the analog current data is not
cumbersome or expensive. Thus, it is evident that the
transformer protection presented here economically
provides quick fault response times coupled with the
advantages of programmable digital processing. The
economy of the system makes possible the use of several
autonomous digital processors in a substation rather
than the use of a single minicomputer to provide all
the protection functions. Reliability could easily be
enhanced as a result. Each function could be handled
with similar hardware with the function characteristics
being provided via software.
ACKNOWLEDGEMENTS
This work was partially supported by the Bonne-
ville Power Administration under Contract No. 14-03-
6509N.
REFERENCES
[1] Richard R. Larson, "Test and Evaluation of a
Digital Algorithm for the Protection of Power
System Transformers," M.S. Thesis, Washington
State University, 1978.
[2] E. 0. Schweitzer, "Development, Testing, and
Evaluation of Algorithms for the Protection of
Electric Power Systems Using Digital Computers,"
Ph.D. Dissertation, Washington State University,
1977.
Richard R. Larson, born in Seattle, Washington
in 1950, received his B.S.E.E. degree from the
University of Washington in 1973.
From 1973-1976 he was employed by the
central engineering department of Weyerhaeuser
Company, Tacoma, Washington. In 1977 he
received the M.S.E.E. degree from Washington
State University where he participated in the
development and hardware implementation of
digital power system protection algorithms. Mr.
Larson is presently employed by Western Gear Corporation, Everett,
Washington, working with industrial applications of microprocessors.
803
[3] E. 0. Schweitzer, R. R. Larson, A. J. Flechsig,
Jr., "An Efficient Inrush Current-Detection Algo-
rithm for Digital Computer Relay Protection of
Transformers," Paper A 77 510-1, IEEE Power Engi-
neering Society Summer Meeting, Mexico City, 1977.
[4] E. 0. Schweitzer, A. J. Flechsig, Jr., "An Effici-
ent Directional Distance Algorithm for Digital
Computer Relaying," Paper A 77 725-5, IEEE Power
Engineering Society Summer Meeting, Mexico City,
1977.
[5] G. D. Rockefeller, "Fault Protection with a Digi-
tal Computer," IEEE Trans. on Power Apparatus and
Systems, Vol. PAS-88, No. 4, pp. 438-464, April,
1969.
[6] J. W. Horton, "The Use of Walsh Functions for
High-Speed Digital Relaying," Paper A 75 582-7,
IEEE PES Summer Meeting, San Francisco, Califor-
nia, 1975.
[7] J. A. Sykes, I. F. Morrison, "A Proposed Method of
Harmonic Restraint Differential Protection of
Transformers by Digital Computer," IEEE Trans. on
Power Apparatus and Systems, Vol. PAS-91, No. 3,
pp. 1266-1272, May/June 1977.
[8] A. R. Van C. Warrington, Protective Relays,
Vols. 1 and 2, Chapman and Hall, London, 1971.
[9] G. Valderrama R., "Power Transformer Protection
Using a Digital Computer," Master's Thesis, Wash-
ington State University, 1975.
[10] J. Berdy, W. F. Kaufman, K. Winick, "A Disserta-
tion on Power Transformer Excitation and Inrush
Characteristics," Presented at the Third Annual
Western Protective Relay Conference, October 19-
21, 1976, Spokane, Washington.
[11] N. Ahmed, K. R. Rao, Orthogonal Transforms for
Digital Signal Processing, Springer-Verlag, New
York, 1975.
[12] T. R. Specht, "Transformer Inrush and Rectifier
Transient Currents," IEEE Trans. on Power Appar-
atus and Systems, Vol. PAS-88, No. 4, pp. 269-
276, April 1969.
[13] Motorola Semiconductor Products, Inc., M6800
Microprocessor Application Manual, Phoenix, 1975.
Alfred J. Flechsig, Jr. (S'67, M'69) was born in
Tacoma, Washington on October 16, 1935. He
received the B.S. and M.S. degrees in Electrical
Engineering from Washington State University,
Pullman, Washington, in 1957 and 1959, respec-
tively. In 1970, he received the Ph.D. degree in
Electrical Engineering from Louisiana State
University, Baton Rouge, Louisana.
He is an Associate Professor of Electrical
Engineering at Washington State University,
where his area of interest are power system pro-
tection and housing process identification.
Edmund 0. Schweitzer, IH, member of IEEE, was born on October 31,
1947. He received the B.S. and M.S. degrees in Electrical Engineering
from Purdue University, Lafayette, Indiana in 1968 and 1971, respec-
tively. In 1977, he received the PhD. degree in Electrical Engineering
from Washington State University, Pullman, Washington.
He is presently an Assistant Professor at Ohio University, Depart-
ment of Electrical Engineering, Athens, Ohio, where his areas of in-
terest are signal processing and power systems.
804
Discussion
R. E. Dietrich (Bonneville Power Administration, Portland, Oregon):
Although this paper presents little new information on transformer dif-
ferential protection, it does provide a digital "relay" using a
microprocessor.
Microprocessors, because of their small size and cost, have the
potential of making cost-effective, equipment-dedicated, digital relay-
ing systems feasible. Further, the proposed algorithm is particularly at-
tractive because of the relatively simple software (no multiply or divide
requirements).
In most digital systems, one of the burdens on computing time is
data processing. It would appear that a three-phase transformer with
three windings might impose restrictions on computing time unless data
processing is done concurrently with algorithm execution. For example,
using a sampling rate of 8 per cycle or 2.08 msec between samples and 9
data inputs per sample (three phases, three windings), the time to ac-
quire data at 20 psec per sample is 180 jsec. Three algorithm executions
at 597 psec, plus data, makes a total of 1970 t4sec, which appears tight.
Would the authors comment.
An important part of any digital control (relay) system are fail-safe
requirements. For example, should a momentary power fail occur dur-
ing the execution of the algorithm, all outputs should block. When
powered up again, the system would initialize and restart the algorithm.
Have the authors considered fail-safe requirements?
Manuscript received August 10, 1978.
R. R. Larson, A. J. Flechsig and E. 0. Schweitzer: The authors wish to
thank Mr. Dietrich for his interest and his comments about our paper.
In the "relay" described in this paper, most of the data processing
takes place simultaneously with algorithm execution once the first input
has been received by the computer. Initial computation and data handl-
ing is performed on each input while the processor waits for the next in-
put. Thus much less than 180 ,usec, about 30 psec, of data processing
time is added to the algorithm execution time in the case of the three
winding, three phase transformer.
It must be noted that three winding transformers would require ad-
ditional calculation time in the differential overcurrent routine. This
adds about 140 ,usec sample period for additional processing desired for
a particular application, microprocessor system clock frequency can be
increased above 1 MHz with readily available inexpensive hardware.
Routines to satisfy the failsafe requirements of this digital "relay"
have not been developed yet. However, a field implementation of this
digital relay should include power down and power up routines trig-
gered by power supply voltage sensing devices via interrupts. As the
power supply voltage falls below a certain value, above the minimum
required by the processor, all outputs would be set to the failsafe,
blocking condition during the remaining milliseconds of operation. The
power up routine should also immediately produce a blocking output
until valid current data is present.
Manuscript received October 17, 1978.