2009 IEEE International Symposium on Radio-Frequency Integration Technology

Issues in “Ahuja” Frequency Compensation Technique

Uday Dasgupta

MediaTek Singapore, Singapore 139964

Email: uday.dasgupta@mediatek.com

Abstract — This paper provides accurate analysis for the Secondly, the open-loop transfer functions of the two do
so-called “Ahuja” frequency compensation technique not have exactly the same form. This is because, in Fig. 1,
explaining why it performs poorly in certain cases. Analyses the feedback compensation signal is added to the signal
for two circuit variations are provided. From the
understanding gained of the analyses, ways to improve the current from the first stage at the drain of compensation
performance are looked into and finally the improvements transistor MP3A. However, in Fig. 2, this addition is done
claimed are verified by calculations and simulation results. at the source of compensation transistor MN3A. It will be
Index Terms — Frequency compensation, integrated shown later that expression wise the zeros of the two
operational amplifiers, Miller compensation, Cascode circuits are different though the poles are the same.
compensation, Ahuja compensation, poles and zeros, In [2], the transconductance gm3 of the compensation
frequency stability.
transistor was assumed to be infinite. The transfer function
has two widely separated poles and no zeros under such
I. INTRODUCTION an assumption. It was pointed out later [3] that, in
practice, there would be a left half plane zero and a high-
Miller compensation has been used extensively in the
frequency pole too. The expressions for those were found
frequency compensation of integrated operational
in [4] assuming gm3 to be unrealistically high.
amplifiers and related circuits since the introduction of
The simulated open-loop gain and phase responses of
μA741 by Fairchild in 1968. An alternative form of
Figs. 1 and 2 are shown in Figs. 3 and 4. The small-signal
compensation was proposed by R. Read and J. Wieser as
parameters are given in section V, part B. As can be seen,
early as in 1982 [1][2]. Nevertheless, it took some time for
these results do not look good around the unity-gain
it to be accepted by the industry and the academia and as
frequency and this cannot be explained adequately with
several of its benefits over the Miller compensation
the analyses presented in [2][3][4].
became slowly apparent, it quietly secured its place as an
important alternative for on-chip frequency compensation.
Although the authors of [1] named it “Cascode” VBP1 VDD
MP4B MP6 MP4A
compensation, it is widely known today as “Ahuja” VBP MP2
compensation after the author of [2] who provided the MP3B MP3A
VBP2
very first analysis, implementation and measurement data.
IN- MP1B MP1A CC
The benefits of “Ahuja” compensation over Miller OUT
compensation are several such as better PSRR [1][2], IN+
higher unity-gain bandwidth using smaller compensation MN2
MN3B
capacitor [2] and ability to cope better with heavy
MN1B MN1A MN3A
capacitive [3] and resistive [4] loads. One of the
objectives of this paper is to highlight that despite the
improvements, the technique is associated with a problem: Fig. 1. Original version of “Ahuja” compensation circuit.
clean Miller-like compensation may be difficult to achieve
sometimes. The other objectives are to show why such
VDD
difficulties are faced and look into possible ways to VBP
MP6 MP4B MP4A
MP2
overcome them. MP1B MP1A
IN-
IN+ MN3B MN3A
II. REVIEW OF THE “AHUJA” COMPENSATION TECHNIQUE
OUT
VBN1 CC
A single-supply adaptation of the implementation in [2]
and a more practical as well as popular version are shown VBN MN2
in Figs. 1 and 2 respectively. Devices with subscripts A MN1B MN1A
and B are identical unless indicated. There are a few
essential differences between the two. Firstly, the circuit
in Fig. 2 can provide higher DC gain than that in Fig. 1. Fig. 2. Popular version of “Ahuja” compensation circuit.

978-1-4244-5032-9/09/$26.00 ©2009 IEEE 326

 g m1 g m3
A0 = g m1 g m 2 r1r2 , s p1 = − , sz = − ,
150 A0CC σC C
Phase (deg.)

100
g m 2 g m3 1 C1 g m3 ⎛ C2 ⎞
50 ωn = , ζ = ⎜1 + ⎟⎟ ,
0 ρC1C2 2 ρC2 g m 2 ⎜⎝ CC ⎠
C3 C3 C3 g m1
75 σ = 1+ , ρ = 1+ + , ω0 = .
50 CC CC C 2 CC
Gain (dB)

25
0
-25 And:
-50
10 1
10 2
10 3
10 4
10 5
10 6
10 7
10 8
⎛ s2 ⎞
⎜ − 1⎟
Freq. (Hz) ⎜s 2 ⎟
Fig. 3. Simulated gain/phase plots for circuit in Fig. 1. A2 ( s ) = A0 ⎝ z1, 2 ⎠ (2)
⎛ s ⎞⎡ s 2
⎛ 2ζ ⎞ ⎤
⎜ + 1⎟ ⎢ 2 + ⎜⎜ ⎟⎟ s + 1⎥
⎜s ⎟⎢ω
⎝ p1 ⎠⎣ n ⎝ ω n ⎠ ⎦⎥
150
100 Where:
Phase (deg.)

50
0 g m 2 g m3
-50 s z1, 2 = ±
-100 C1CC
75
50 The rest of the parameters are the same as those in (1).
Gain (dB)

25
0
-25 B. Discussion
-50 1
10 102 103 104 105 106 107 108
As shown above, expressions of the low-frequency pole
Freq. (Hz) sp1 and the second-order high frequency pole-pair sp2,3
Fig. 4. Simulated gain/phase plots for circuit in Fig. 2.
with natural frequency ωn = 2πfn and damping factor ζ
are the same for the circuits in Figs. 1 and 2. However, the
III. REALISTIC ANALYSIS OF THE “AHUJA” COMPENSATION latter circuit has a pair of L.H.P. and R.H.P. zeros sz1,2 (
|sz1,2| = ωz1,2 = 2πfz1,2 ) as opposed to a single L.H.P. zero
A. Analysis sz ( |sz| = ωz = 2πfz ) for the former. The parameters σ, ρ
are close to unity, modeling the effect of C3.
We shall assume C1 and C2 to be the net capacitances
For usual values of the circuit parameters, ζ is less than
loading the output resistances r1 and r2 of the first and
unity implying that the pair sp2,3 is complex and not real as
second stages with transconductances gm1 and gm2
in [4]. The small valued capacitor C1 can be seen to be
respectively for the circuits shown in Figs. 1 and 2. The
present in the expressions of both ωn and ζ. This helps ωn
compensation transistor has a transconductance gm3 and a
to be sufficiently high but results in small values of ζ at
parasitic gate-source capacitance C3. Small-signal analyses
the same time. Complex non-dominant poles with small
of the above circuits yield results (1) and (2) for the open-
damping factors are undesirable because those can cause
loop transfer functions A1(s) and A2(s) respectively after
loss in phase and/or gain margins, poor transient behavior
suitable approximations. A0 and ω0 = 2πf0 are the DC gain
and, in extreme cases, instability. If C1, C2 and gm2 are
and the unity-gain bandwidth respectively.
decided based on other factors then, for large values of ζ,
gm3 needs to be high and/or CC small. A value of ζ close to
⎛ s ⎞ 0.5 will be adequate in most cases. It is easy to show that
⎜⎜ + 1⎟⎟
A1 ( s) = A0 ⎝ sz ⎠ (1) ωn is expression-wise equal to magnitude of the non-
⎛ s ⎞ ⎡ s 2 ⎛ 2ζ ⎞ ⎤ dominant pole described in [2] when ζ = 0.5.
⎜ + 1⎟ ⎢ 2 + ⎜⎜ ⎟⎟ s + 1⎥ The zero in the circuit of Fig. 1 is usually located just
⎜ s p1 ⎟ ω
⎝ ⎠⎣ n ⎝ ω n ⎠ ⎦ before the complex poles and the resulting magnitude
curve shows pronounced peaking after the unity-gain
Where: crossover, sometimes popping over the unity-gain line
again, if ωn and ζ are small. The phase response also
shows a rise because of the zero. The circuit in Fig. 2 has

327
zeros with mirror-symmetry on the left and right half C. Practical considerations
planes at higher frequencies compared to the complex
We shall look into the effects of bandwidth limitation of
poles and, therefore, do not contribute much to the shapes
the auxiliary amplifier in this subsection. We assume that
of gain and phase characteristics near the unity-gain
the amplifier has a single pole at frequency ωp for this
frequency. That, therefore, is decided mostly by the
purpose. Then the second-order factor in the denominator
complex non-dominant poles.
of either (1) or (2) modifies to a third-order one. For all
the roots of this modified denominator to be in the left half
IV. TRANSCONDUCTANCE OF COMPENSATION TRANSISTOR plane one can show, applying Routh-Hurwitz criterion, the
following should hold:
A. Direct transconductance enhancement
As expected, (1) and (2) show that a large value of gm3 ⎛g ⎞ ⎛ C ⎞
ω p > ⎜⎜ m 2 ⎟⎟ where C a = C1 ⎜⎜1 + 2 ⎟⎟ (3)
improves the compensation in an all-round manner by ⎝ Ca ⎠ ⎝ CC ⎠
shifting the non-dominant poles and zeros to higher
frequencies and increasing the damping factor of the It can be noted that gm2/Ca is the magnitude of the non-
complex poles. The simplest way to do this is to choose a dominant pole as given in [2]. According to (3), the –3-dB
large bias current and a large aspect ratio for the bandwidth of the gm3 amplifier must be larger than that.
compensation transistor. This method is suitable for the Otherwise, the complex pole-pair of the modified open-
circuit in Fig. 1. But it cannot be applied conveniently to loop transfer function could be located in the right half
the circuit in Fig. 2 because the bias current of the plane. It can be shown that the same restriction applies to
compensation transistor needs to be duplicated. In any the closed-loop transfer function too. Thus (3) imposes an
case, this method will consume a lot of power if additional requirement for stability with active gm3
substantial increase in gm3 is required. multiplication. It is clear now that the auxiliary amplifier
needs to be a wide-band one indeed.
B. Active transconductance multiplication
Indirect enhancement of gm3, as shown in Fig. 5, may be V. EXPERIMENTS, RESULTS AND DISCUSSION
employed if large values of gm3 are required with
reasonable amounts of power consumption. An auxiliary A. Circuit modifications for improvement
amplifier with gain A amplifies vs, the small-signal For the circuit in Fig. 1, the m-multipliers of MP4A,
voltage at the source of MP3, and this appears at the MP3A and MN3A were increased to M times those of MP4B,
latter’s gate as –Avs. The small-signal gate-source voltage MP3B and MN3B respectively. This, in effect, multiplied
of MP3 is then –(1+A)vs and the resulting drain current id the transconductance gm3 of MP3A by a factor M. For the
is –(1+A)gm3vs. Thus, gm3 appears to be multiplied by a circuit in Fig. 2, the transconductance gm3 of MN3A was
factor (1+A). There is something more that we need to multiplied using an auxiliary amplifier formed by MN5A
consider. The increase in gate-source voltage of MP3 by a with transconductance gm5 and identical load resistors RAA
factor (1+A) increases the current through C3 and the and RAB as shown in Fig. 6. The bias current supplied by
effect, therefore, is equivalent to a magnification of C3 by MP3 split equally between MN5A and MN5B because of
the same factor. Consequently, σ and ρ increase adversely symmetry in the circuits around them. In this case, one
affecting the increase in ωz, ωn and ζ but not that of ωz1,2, can work out M = 2(1+gm5RA), where RA stands for the
according to (1) and (2). However, this effect is noticeable value of any one of the resistors.
only for large values of C3 and/or A.
MP4B MP4A VDD
MP6 MP3
vs VBP
VDD C3 CC MP2
IBIAS MP3 MP1B MP1A
A gm3 IN-
-Avs
VBIAS IN+ RAB
id MN3B MN3A RAA
OUT
INN IBIAS OUT
MN5B MN5A CC
A1 A2 VBN
INP C2 MN2
C1
MN1B MN1A

Fig. 5. Concept of active transconductance multiplication. Fig. 6. Active transconductance multiplication for Fig. 2.

328
B. Experimental results and discussion
The circuits in Figs. 1, 2 and 6 were designed using the 150

Phase (deg.)
3-V transistors of UMC 65-nm CMOS process. The 100
circuit parameters for Fig. 1 were: gm1 = 70.36μS, gm2 = 50
766.88μS, gm3 = 124.33μS, C1 = 0.11pF, C2 = 10pF, C3 = 0
0.007pF and CC = 1.0pF. Those for Fig. 2 were: gm1 =
70.41μS, gm2 = 717.27μS, gm3 = 140.65μS, C1 = 0.23pF, 75
C2 = 5pF, C3 = 0.002pF and CC = 1.0pF. For Fig. 6, gm5 = 50

Gain (dB)
137.30μS and RA = 10kΩ are to be added to the latter set. 25
0
Figs. 7 and 8 show the improvements over Figs. 3 and 4 -25
respectively using the abovementioned modifications. The -50 101 102 103 104 105 106 107 108
simulation results depicted in Figs. 3 and 7 are compiled Freq. (Hz)
and compared with the corresponding calculated values in Fig. 7. Simulated gain/phase plots for Fig. 1 (high gm3).
Table I. Likewise, the results for Figs. 4 and 8 are
summarized in Table II. While doing simulations, pole-
zero analyses were conducted to find the high frequency
150
poles and zeros. IB in the tables is the total bias current fed 100

Phase (deg.)
to the compensation circuitry and auxiliary amplifiers. Gm 50
0
and φm stand for gain and phase margins respectively. -50
-100
TABLE I
RESULTS FOR CIRCUIT IN FIG. 1 75
50
Parameter Normal Normal High High
Gain (dB)

25
gm3 gm3 gm3 gm3 0
(sim.) (cal.) (sim.) (cal.) -25
-50
M 1.00 4.00 101 102 103 104 105 106 107 108
IB (μA) 10.00 40.00 Freq. (Hz)
f0 (MHz) 13.56 11.20 11.48 11.20 Fig. 8. Simulated gain/phase plots for circuit in Fig. 6.
φm (Deg.) 105.80 - 87.60 -
Gm (dB) 20.51 - 31.14 - VI. CONCLUSION
fz (MHz) 19.30 19.79 78.86 79.12
fn (MHz) 46.21 46.65 92.91 93.30 In this paper we have attempted to provide more insight
0.25 0.23 0.48 0.47 into some aspects of “Ahuja” compensation applied to
ζ
practical situations. We have also shown ways to improve
TABLE II the compensation at circuit level and verified the results
RESULTS FOR CIRCUITS IN FIG. 2 AND FIG. 6 with simulations and calculations. Good matches between
Parameter Fig. 2 Fig. 2 Fig. 6 Fig. 6 simulated and calculated parameter values validate the
(sim.) (cal.) (sim.) (cal.) accuracy of the analysis presented in the paper.
M 1.00 4.75
IB (μA) 20.00 40.00 REFERENCES
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Gm (dB) 9.43 - 16.82 - Circuits, vol. 17, no. 6, pp. 968-982, December 1982.
fz1,2 (MHz) 105.21 106.57 231.97 232.27 [2] B. K. Ahuja, “An improved frequency compensation
technique for CMOS operational amplifiers,” IEEE Journal
fn (MHz) 48.48 47.66 104.50 103.88
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