2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 103

Design of Low Power 12-bit Magnitude Comparator

Dwip Narayan Mukherjee Saradindu Panda Bansibadan Maji

Department of Electronics &
Communication Engineering
Bankura Unnayani Institute Engineering
Bankura, India
dwipnarayan@gmail.com
Department of Electronics &
communication Engineering
Narula Institute of Technology
Kolkata, India
saradindupanda@gmail.com
Department of Electronics &
communication Engineering
National Institute of Technology
Durgapur, India
bmajiecenit@yahoo.com

Abstract--In the advanced technology low power, speed and of logic circuit that thinks about the relative magnitudes of
size play a significant role specifically in the field of magnitude these two variables. The block diagram of magnitude
VLSI circuits. In this paper small power dissipation and less comparator appears in Fig 1. The result of magnitude
area over conventional 2- bit comparator is proposed and using comparator is determined by three variables that
this comparator a new style 12-bit comparator is proposed. The demonstrate whether A>B, A<B, or A=B.
main objective of this paper is to design and implement of
magnitude comparator using different logic techniques and
compared in terms of power consumption, propagation delay
and transistor count. The results of this paper are simulated on
the EDA tanner tool realized in 45-nanometer technology at
0.7v supply voltage.

Keywords-- Magnitude Comparator, Transmission Gate Logic

Technique, Half Adder Logic Technique, Power Dissipation,
Propagation Delay, Transistor Count.

I. INTRODUCTION
The power consumption is a vital issue in magnitude
CMOS circuits, where different techniques and technologies
are used to design circuits for low power dissipation with
small size and high-speed interface applications are
developed.
Circuit size relies on upon the quantity of transistors and Fig. 1. Block diagram of magnitude comparator.
their sizes and on the wiring complexity [1]. The wiring
intricacy is dictated by the quantity of associations and their The first phase in the comparison processor of the two-bit
lengths. Therefore, the wiring complexity may fluctuate magnitude comparator is to check the greatest bit A0 and B0.
significantly from one logic style to another and On the off chance that greatest bit of both inputs are
consequently, the legitimate decision of logic style is critical distinctive, e.g. assume the greatest bit of A is more
for circuit execution [2]. prominent than B in that case A>B and if the greatest bit of
Magnitude comparator has several utilities like those are B is more prominent than A at that moment A<B. In the
utilized as a part of microprocessor and embedded systems. event, that greatest bit of both inputs is equivalent after that
In this paper, magnitude comparator is designed using go for next step. The second step is to check the following
different techniques with the low power consumption and relating bits A1 and B1 of both the inputs. On the off chance
higher packing densities in 45-nanometer technology at 0.7v that next comparing bit of A is more noteworthy than B at
supply voltage. that moment A>B and if information condition is switch,
subsequently A<B. In the event that, both inputs are same
II. TWO-BIT MAGNITUDE COMPARATOR
subsequently A=B [7]. Equation (1), (2) and (3) is given to
In magnitude logic system, the traditional method of control the outputs of the two-bit magnitude comparator.
comparison of two variable A (A0, A1) and B (B0, B1) of a
two-bit binary number is a logical operation that figures out
whether A is less than B, A is greater than B and A equal to
B [3], [4]. Therefore, the magnitude comparator is such type
978-1-5090-4724-6/17/$31.00 ©2017 IEEE
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 104

TABLE I TRUTH TABLE OF TWO-BIT MAGNITUDE III. TRANSISTOR IMPLEMENTATION OF TWO-

COMPARATOR
BIT MAGNITUDE COMPARATOR USING
CONVENTIONAL CMOS LOGIC STYLE
Inputs Outputs
CMOS logic technique consists of two networks, one is
A0 A1 B0 B1 A>B A<B A=B NMOS pull-down network and another is PMOS pull-up
network. The CMOS logic circuit is outlined in a way that
0 0 0 0 0 0 1
stands out system is directing at once.
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 0 1 0 0 1
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 0 1 1 0 1 0 Fig. 3. Transistor implementation of a conventional two-bit magnitude
comparator.
1 1 0 0 1 0 0
CMOS logic style is really an extension of CMOS
1 1 0 1 1 0 0
inverters to multiple inputs [5]. Fig 3 shows the Transistor
1 1 1 0 1 0 0 implementation of conventional 2-bit magnitude
1 1 1 1 0 0 1
comparator.

IV. TWO-BIT MAGNITUDE COMPARATOR

: USING THE TRANSMISSION GATE LOGIC STYLE
(1) The transmission gate logic gives high speed and less power
: dissipation than conventional CMOS for the reason that of
(2) the small transistor stack height, the least number of
: transistors is required and no complementary input signals
are required. The transmission gate comprises of one NMOS
A EX NOR B A EX B (3) and PMOS transistor, which are associated in parallel. The
graphical symbol of the transmission gate appears in Fig 4.
The gate implementation of a two-bit magnitude
comparator appears in Fig 2.

Fig. 4. Graphical symbol of the transmission gate.

It will act as a switch which selectively block or pass a

signal from the input to the output by biasing the control
gates in a complementary way according to the demand. The
truth table of the transmission gate logic is shown in Table
Fig. 2. Gate implementation of a two-bit magnitude comparator. 2.
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 105

TABLE II TRUTH TABLE OF THE TRANSMISSION GATE LOGIC

Control Input(g) Input Output

High logic level High logic level High logic level

High logic level Low logic level Low logic level

Low logic level Don’t care(x) High Impedance

If the voltage on node g is a high logic level (g=1), after

that, both transistors are ON and give a low impedance path
between input and output, so a signal can easily pass from
input to the output. If the voltage on node g is a low logic
level (g=0), after that, both transistors are OFF and give the
high impedance path between input and output, therefore, no
signal can pass from input to the output.
The existing transmission gate logic based two-bit
Fig. 6. Two-bit magnitude comparator using the transmission gate logic
magnitude comparator shown in Fig 5 which consists of 74 technique.
transistors [6]. Due to a large number of transistors, it will
consume more power and lower packing density. But in
nowadays as the power, speed and area are the significant
V. TWO-BIT MAGNITUDE COMPARATOR
factors in magnitude VLSI circuit. As a result, this designed
USING THE HALF ADDER LOGIC STYLE
is not considered for superior performance. Consequently,
this paper concentrated on modified transmission gate based In this proposed designed technique a magnitude comparator
two-bit magnitude comparator designed which consists of 30 has been designed using half adder and basic logic gates.
transistors only. In this proposed design the power Implementation of the design procedure using hardware
consumption is reduced with larger packing density and requires two sub-block one is half adder block and another is
higher speed. In the proposed design each transmission gate comparison block. Half adder and logic gate implementation
act as an AND gate which is used in conventional gate of two-bit magnitude comparator is shown in Fig 7. Half
design of the two-bit magnitude comparator. Subsequently, adder block performs single bit comparison and gives output
the circuit required the least number of transistors. The through Sum and Carry.
proposed transmission gate based two-bit magnitude Sum (SM) = (AM EX-NOR BM)
comparator appears in Fig 6. Carry (CM) = AM' BM = AM' (AM EX-OR BM), Where M= 0,
1.

Fig. 5. Schematic of the existing two-bit magnitude comparator using the

transmission gate logic.
Fig. 7. Half adder and logic gate implementation of two-bit magnitude
comparator using half adder logic technique.
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 106

If both A, B input bits are equal, then sum takes a value of

logic 1. If both bits are unequal (A<B), carry takes a value
of logic 1. For 2-bit comparison 2 numbers of half adder
blocks are required. Comparison block needs 2 channels of
transistors for performing the A<B and A = B operations.
Channel-1 generates of output A<B and channel-2 generates
of output A=B.
A<B → C0 + S0 C1
A=B → S0 S1
If any bit pair is unequal (A<B), then the carry output of
corresponding half adder is at logic 1. This logic 1 pass
through the corresponding PMOS in the channel-1 to the
output A<B and logic 0 pass to the output A=B in channel-2.
If all bit pairs are equal, then all NMOS are ON state in
channel-2 and gives high logic level at output A= B. In
channel-1, C0 (logic 0) pass to the output A<B.
In this proposed design the power consumption is reduced
with larger packing density and higher speed. The proposed
logic technique consists of 20 transistors only, so this circuit
required the least number of transistors. Using half adder
and channel 1 and 2 based 2-bit comparator is shown in Fig
8 which is determined whether A is less than or equal to B.
Design of half adder logic based N-bit comparator is shown Fig. 9. Design of N-bit magnitude comparator using proposed half adder
in Fig 9. logic technique.
The number of transistors required to design a N-bit
magnitude comparator is-
N *Inverter + N* Half Adder + Channel-1+ Channel-2 +
Level-2 VI. TWO-BIT MAGNITUDE COMPARATOR
USING THE X-E LOGIC
= N*(1p+1n) + N*(2p+2n) + (N-1)*(1p+1n) + (N-
1)*(1p+1n) + (2p+2n) In this proposed designed technique a magnitude comparator
= 10*N (4) has been designed using X-E block. Each X-E block has two
output one is ‘E’ which will give the equality of two single
bit signals and other one is ‘X’ which represents the one
signal is less than the other signal or not. X-E blocks and
three chain of transistors are used for performing less and
equal operation. For N-bit of comparasion-
EM = (AM EX-NOR BM)
XM = AM' (AM EX-OR BM), Where M= 0,1,2,….,(N-1).
Design of N-bit comparator using X-E block and transistor
is shown in Fig 10. Chain-1 and 2 generates output A
lessthan B and chain-2 and 3 generates A equal to B. When
X0 =1, E0 = 0, then E0 breaks rest of chain-1 by setting the
transistor T2 to OFF mode and E0 set the transistor T0 to
ON mode, which set logic 1 on node N1. When all E are
logic 1, then all the transistors in chain-2 are in ON states
Fig. 8. Two-bit magnitude comparator using the half adder logic technique. and at the same time chain-3 pass a strong 0 to node N2
either from ground or from X0. This type of design is used to
reduce the power consumption by using stack effect.
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 107

VIII. SIMULATION RESULTS

The simulation result is measured by the EDA Tanner tool
in 45 nanometer technology at 0.7v supply voltage. The
schematic circuit configuration of CMOS logic, transmission
gate logic based two-bit magnitude comparator, two-bit
magnitude comparator using half adder logic, two-bit
magnitude comparator using X-E logic are appearing in Fig
12, 13, 14 and 15 respectively. The layout of the proposed
two-bit magnitude comparator using half adder logic is
shown in Fig 16. The schematic and layout of 12-bit
magnitude comparator using half adder logic technique is
shown in Fig 17 and 18. The power consumption of this half
adder logic based 12-bit magnitude comparator is 0.61
microwatt. The simulation result is abridged in Table III.

Fig. 10. Design of N-bit magnitude comparator using X-E logic technique.

VII. 12-BIT MAGNITUDE COMPARATOR USING

THE HALF ADDER LOGIC STYLE
The implementation of 12-bit comparator using half adder
logic style is shown in figure below. It has inputs (A11,B11
A10,B10 and so on up to A0,B0) and 12 half adder block is
required to get output S and C for each single bit comparison
and this outputs are connected to channel-1 and channel-2 in
comparison block. Design of 12-bit magnitude comparator
using half adder logic technique is shown in Fig 11.

Fig. 12. Schematic of the two-bit magnitude comparator using the CMOS
logic technique.

Fig. 13. Schematic of the two-bit magnitude comparator using transmission

Fig. 11. 12-bit magnitude comparator using the half adder logic technique. gate logic technique.
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 108

Fig. 14. Schematic of the two-bit magnitude comparator using half adder
Fig. 17. Schematic of 12-bit magnitude comparator using half adder logic
logic technique.
technique .

Fig. 18 . Layout of the optimized half adder logic based 12-bit magnitude
comparator.

Fig.15. Schematic of the X-E logic based two-bit magnitude comparator. TABLE III PERFORMANCE COMPARISON OF TWO-BIT
MAGNITUDE COMPARATOR
Paramete Conven Transm Propose Half X-E Half
rs -tional ission d adder logic adder
2-bit Gate Transmi logic based logic
compar logic[6] ssion based 2-bit based
ator Gate 2-bit comp 12-bit
logic compar arator comp
based 2- ator arator
bit
compara
tor
Power
0.12
consumpt 0.62 0.47 0.28 0.33 0.61
ion (µW)
Number
of 54 74 30 20 25 120
transistor
Propagati
7.63
on delay 8.40 8.49 6.87 7.96 3.13
(n-sec)
Power
delay 0.82 1.90
5.20 3.99 2.13 2.62
Fig. 16. Layout of the optimized half adder logic based two-bit magnitude Product
comparator. (µ-nJ)
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 109

IX. CONCLUSIONS
To enhance the performance of a magnitude comparator we
have designed magnitude comparator using different logic
techniques. After simulation of all kinds of outline
strategies, the last results are gotten for Power Consumption,
Delay and Power Delay Product. Power utilization of the
half adder logic based two-bit magnitude comparator is
0.12µW which is almost 74.46% less than existing
transmission gate logic based two-bit magnitude
comparator[6]. It has been found that the transistor count is
less in the proposed transmission gate logic circuit which is
almost 69.69% less than existing transmission gate logic
based two-bit magnitude comparator, subsequently that the
overall area is minimized. According to this half adder logic
technique a 12-bit magnitude comparator is designed which
has 0.61 microwatt power consumption and 3.13
nanosecond propagation delay.

References
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[2] A. Bellaouar and Mohamed I. Elmasry, “Low Power Magnitude VLSI
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[3] S. Salivahanan and S. Arivazhagan (2004): ‘Magnitude Circuits and
Design’ (2nd Ed).
[4] M.Morris Mano: ‘Magnitude Design’ (Pearson Education Asia. 3rd
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