IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO.

6, NOVEMBER/DECEMBER 1983 1057

Generalized Structure of a Multilevel PWM Inverter

PRADEEP M. BHAGWAT, MEMBER, IEEE, AND V. R. STEFANOVIC, SENIOR MEMBER, IEEE

Abstract-A generalized structure of a multilevel voltage source

thyristor inverter is proposed. The multilevel concept is used to de-
crease the harmonic distortion in the output waveform without de-
creasing the inverter power output. A simple uniform PWM control of
the output voltage is seen to be sufficient to practically remove all
remaining harmonics. Harmonic analysis of n-step waveform is given,
and the experimental results obtained on a three-step inverter are
presented.
INTRODUCTION
THE CURRENT shift to variable-frequency ac drives with
associated emphasis on improved performance and in-
creased power ratings is again focusing attention to the prob-
lem of inverter harmonic distortion. The distortion is particu-
larly of concern in drives above 50 hp where power transistors
cannot be applied so easily and the pulsewidth modulation
(PWM) control becomes less attractive. In fact, an adjustable-
voltage adjustable-frequency inverter operating with essentially
square-wave output voltage can be viewed as a generator of
higher harmonics [1]. Presently, three basic methods for
harmonic reduction exist.
1) Multilevel Waveforms: In the past, multilevel operation
was achieved by summing the outputs of several inverters
operating in parallel through phase shifting transformers [2].
Obviously, this technique is no longer attractive for most
applications due to the large reactive elements used. Recently,
a transistor inverter with a multilevel voltage waveform was
proposed [3], [4]. Although the inverter provides an efficient
reduction of harmonic distortion, due to the existing transistor
technology its use is limited to low-power applications.
2) Sinusoidal PWM [5].- By chopping the output waveform
and by appropriately controlling the width of the resulting
voltage pulses, one can successfully eliminate all dominant
harmonics. The problem here is that the scheme results in the
voltage derating of the inverter.
3) Pulsewidth Control: By producing several pulses during
each half-period of the output waveform and by controlling
their position and width, selected harmonics can be eliminated
from the inverter output [6]. However, the voltage control is
limited, while the inverter is still derated with this technique.
The proposed inverter shown in Fig. 1 is conceptually sim-
ple and can be easily implemented by using power transistors.
If a higher power output is desired, the use of thyristors will
be required. It will be shown that, in the multilevel inverter,
Paper IPCSD 82-9, approved by the Static Power Committee of the monics from the motor
IEEE Industry Applications Society for presentation at the 1980 In-
dustry Applications Society Annual Meeting, Cincinnati, OH, Septem-
ber 29-October 3. Manuscript released for publication April 2, 1982.
This work was supported in part by the National Research Council of
Canada and the Department of Education, Province of Quebec.
P. M. Bhagwat is with Black and Decker Co., 701 East Joppa Rd., A. Optimization Techniques
Towson, MD 21204.
V. R. Stefanovic is with General Electric Company, POB 8106,
Charlottesville, VA 22906.
0093-9994/83/1100-1057$01.00 © 1983 IEEE
T
Fig. 1. Schematic of half-bridge multilevel inverter.
the use of conventional commutation circuits will result in a
complex firing control. The new versatile commutation cir-
cuit [7] has the capability of instantaneously commutating
any conducting thyristor and therefore is ideally suited for the
multilevel inverter. This flexibility permits a PWM control of
the inverter output voltage.
The harmonic analysis of an inverter with n voltage levels
is given, and a number of necessary semiconductor switches
is specified. The circuit implementation of such an inverter is
described, and the concept is illustrated by considering a three-
level inverter which has been actually designed and con-
structed in-the laboratory. Voltage control of this type of in-
verter is then discussed, and the harmonic analysis of a three-
level PWM inverter is presented. It is seen that, with ten
uniform pulses per half-period of the output waveform, all
harmonics below the twenty-third are reduced to less than or
equal to ten percent of the fundamental harmonic. Experi-
mental results, corresponding to the theoretical calculations
are given in Fig. 13. The proposed inverter structure is be-
lieved to offer the following advantages when applied to vari-
able-frequency ac drives.
1) The voltage contiol below the motor base frequency can
be obtained by a very simple uniform PWM control while
reducing practically all harmonics from the motor input
voltage.
2) For maximum voltage output (constant power operation
above the motor base frequency), the inverter full power can
be used, while at the same time reducing all dominant har-
input voltage.
II. HARMONICS IN THE OPTIMIZED
STEPPED WAVEFORMS
There is a considerable complexity in trade-offs when
choosing the number of voltage steps [8] . Considering Fig. 2,

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1058 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

Fig. 2. Generalized stepped waveform.

three possible optimization techniques exist to reduce the low- where 0 = ir/2p and Vk = V1 (cos Ok/cos 01). For waveforms
order harmonics: 1) assuming equally spaced steps, step of this type, the harmonics will occur as follows:
heights are optimized; 2) assuming the steps of equal heights,
their spacing is optimized; 3) optimizing both height and hn = 4pn ± 1
spacings.
The Fourier expression for the-waveform in Fig. 2 is where n = 1, 2, 3 -e. Therefore, for the optimized 12-step
waveforms with p = 3, the first low-order harmonic will be
4 the eleventh.
e=- z (V1 cosn01 + V2 cosn02 +--
7f n=odd B. Harmonic Reduction in the Three-Level Inverter
sin (nct) In practice, however, a trade-off has to be made between
+vcos n0p) nn
(1) the required number of steps and the design complexity.
Harmonics can be reduced as required through PWM voltage
4 p sin (nwt) control, but harmonic reduction becomes impossible when
=_7r 1
n=odd k=l
2(Vk cos nOk)
n
(2) the inverter is delivering its full output, at which time the
harmonic content of the output waveform is that of a typical
square wave, with the absence of triplen harmonics.
where p denotes the number of steps in a quarter-cycle, 0kk Fig. 3(a) shows the multilevel inverter schematic with a
ir/2 and a quarter-wave symmetry in the waveform is assumed. minimum number of voltage references, which are a) positive
For equally spaced steps with no dwell at zero voltage, i.e., reference, b) negative reference, and c) zero reference.
0 1 = 0, (2) becomes Fig. 3(b) shows a typical waveform of a half-bridge inver-
ter. From (1), it can be seen that a specific duration of a zero
4 interval can eliminate any one specific harmonic. Rewriting
e =- z [V1 + V2 cos n± +V3 cos 2nO +
XT n=odd (1) for Fig. 3(b),

sin nO
+ Vp cos (p-l)nO] X n
e=-TV1
irn
cosn01 sin ncot (5)

where V1 = 0.5 Ed =0.5 V

4 .p sin nO
=- z z
7T n=odd k=1
(Vk cos ((k-l )nO)) n (3) * if 01 = 18°, the fifth harmonic will be zero,
* if 01 = 12.850, the seventh harmonic will be zero, etc.
where 0 = ir/2p and Vk = 2V1 cos (k - 1) 0. Fig. 3(c) shows the typical line-to-line voltage waveform ob-
For equally spaced steps with dwell at zero voltage such tained in the proposed multilevel inverter. This waveform can
that 01 = a/2, 02 = 3a/2, 03 = 5a/2, Ok = (2k - I)a/2, be optimized by any one of the techniques discussed before.
(2) becomes The harmonics of this waveform can be expressed as

4 p nO An= V cos (nO0) + V2 cos (nO2). (6)

e=- Y4 Vk cos((2k- l)nO) sin- (4)
7f n=odd k=1 n As this waveform is the difference between any two phase

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BHAGWAT AND STEFANOVIC: GENERALIZED STRUCTURE OF MULTILEVEL PWM INVERTER 1059

(a)

0
eil I
I
_rrr
- ---

(b)

(c)
Fig. 3. (a), (b) Schematic of three-level inverter and output waveform. (c) Typical phase and line voltages in three-level
inverter.

voltages, V1 should be equal to V2 and 0 1 should be equal to where

((iT/3) -02) Vt rms value of the stepped wave,
Vf rms value of the fundamental,
..A =0.5Ed 02) + cos](n2)1
[cosn (- (7) for the waveform shown in Fig. 3(c):

02 can be selected so as to eliminate any particular harmonic 2V

or to reduce the total harmonic distortion. Eliminating only Vf = [0.5Vcos01 + 0.5Vcos 02 ]
one particular harmonic will not significantly improve the
waveshape; therefore, reducing the total harmonic distortion =- V(cos01 +COS02) (8)
(THD) may be desirable.
and
C. Minimizing the Total Harmonic Distortion
V2 02 2 fr/2
Total harmonic distortion can be expressed as V2_ (o.v 7)2 dO+-J v2 do

IVt 2V2 - _
THD percent = 100 - - 1 =-~-2 - 0.7502 - 0.250, (9)

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1060 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

and simplifying,
-..- - 0.7502 - 0.2501]
.vt2 (10) Cos (-02) + COS 02
vf (COS 0 + COS 0-)2
2 =0.
dO (3
As sin 02 -)sin -02

7r
0 1=3-02
3
Numerical solution gives 02 = 0.79068 rad 45.3030. =

Thus 02 = 450 and 01 = (ff/3) 02 = 150. Table I shows

-

and the harmonic amplitudes for the two waveforms. From Table
I it can be seen that significant reduction occurs in the total
iT
<02 ir/3. harmonic distortion from 31.08 percent in the conventional
6 waveform to 16.86 percent in the proposed waveform. At the
same time, the dominant fifth and seventh harmonics are also
Substituting 01 and 02 in (8) and (9), reduced from 20 percent to 5.35 percent and 14 percent to
3.82 percent, respectively. Fig. 3(c) shows that the proposed
waveform and a conventional line-to-line voltage waveform
Vf = 7 os (-02) + COS 02] (11) have the same average value. This means that this harmonic
reduction is achieved by maintaining the same average power
output as that of a conventional PWM inverter.
Vt2 =-[- --0.7502-0.25 (- -02)] III. GENERALIZED METHOD OF COMMUTATION IN
A MULTILEVEL INVERTER
2V2 A. Classification of the Commutation Types
= ~
- - 0.502 (12)
ir -12 Fig. 4 shows the generalized single phase of a half-bridge
multilevel inverter where A denotes the output terminal.
Vt2 2V2 57T 2V2 \ Current IA through node A is defined as positive when it
Vf 7
-
2 -0502 /72 COS 3-2
flows from node A to the load. Current IA is defined as nega-
tive when it flows from the load to node A. From these
v 2 IT 12 7T 32°0 definitions, it may be observed that if IA is positive, any one
of the semiconductors having its cathode connected to termi-
iT1 nal A can conduct for a given time. If IA is negative, then any
+ COS
[COS(7r/3-02)
02j * (13) one of the semiconductors with its anode connected to termi-
Co02

nal A can conduct for a given time.

To minimize the total harmonic distortion the term Vt2/Vf2 Under normal operation due to di/dt restrictions during
should be minimum. Let commutation, two semiconductors will conduct simultane-
ously until a current transfer from one semiconductor to the
_ _ other is completed.
t2 Xr 2-°0502 Using these definitions, one can identify four types of
commutations: commutation of a thyristor when current is
positive and is transferred from any semiconductor to a
[cos (-02) + COS 02] semiconductor at a) a higher potential or b) a lower potential;
commutation of a thyristor when current is negative and is
transferred from any semiconductor to a semiconductor at c) a
minimizing y, higher potential or d) a lower potential.
From Fig. 4 it is interesting to note that thyristor com-
.-=o= [cos (-02) +cos02][-0.5]
mutation is automatically achieved for cases a) and d) when
the desired current transfer is done. This is due to the fact that
when a current transfer is made, the previously conducting
thyristor automatically gets reverse biased, and therefore
[I1 2.* 2] [cos (C-02) ±CO2] special forced commutation is not required. For cases b) and
c), special forced commutation is required to turn off the
conducting thyristor.
sin 02-sin ( -0 2) It is also interesting to note that if a positive current is
freewheeling in the freewheeling diode at the extreme nega-

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BHAGWAT AND STEFANOVIC: GENERALIZED STRUCTURE OF MULTILEVEL PWM INVERTER 1061
TABLE I voltage, one would need two conventional commutation
An., An% circuits for each inverter phase. The reason is as follows: with
a conventional circuit, the commutation capacitor has to be
-Harmonic Conventional Optimized charged with correct polarity before any given thyristor can be
Number Waveform Waveform turned off. Thus with a PWM control, when the same thyristor
al 127.3 122.9 is repeatedly switched on and off during each half-cycle, while
a3 0.000 0.000 the load current is not changing the direction, one has to call
20
for redundant (negative current) commutation, although no
a5 5.35
thyristor is conducting and the load current is freewheeling
a7 14.2 3.82 through a diode. This commutation is necessary to recharge
a 0.000 0.000 the commutation capacitor with a correct polarity for the next
a11 9.09 9.09 thyristor commutation. Such an approach-is not practical with
a PWM-controlled multilevel inverter with a zero-reference
a13 7.69 7.69
switch Sz (Fig. 3), since one would have to know in advance
al5 0.000 0.000
the pattern of the load current switching, including the op-
a17 5.88 1.57 eration at zero voltage across the load. As a result, if a pre-
a19 5.26 1.41 charged commutation capacitor is used, two commutation
0.000 0.000 circuits (one for the upper and one for the lower thyristor
a21 groups) would be necessary.
a23 4.34 4.34
The ideal commutation circuit for this application would be
a25 4.0 4.0 the one where the charge on the commutation capacitor is
827 0.000 0.000 zero before and after the commutation process. In that case,
829 3.44 0.92 the circuit becomes "impartial" to the commutation in the
THD 31.08: [ 16.86% upper or lower thyristor group, being able to follow any
switching sequence. Detailed description of such a circuit is
given in [7] and is briefly discussed here.
Fig. 5. shows a half-bridge multilevel inverter with the com-
mutation circuit. In Fig. 5, thyristor T-1 and diode D-1 are
connected to the positive voltage reference, thyristors TZ1
and TZ2 are connected to the zero reference level, and thyris-
tor T-2 and diode D-2 are connected to the negative reference
level. Note that in an N-level multilevel inverter, T-1, D-1 and
T-2, D-2 will be at the extreme positive and negative references,
respectively. TA-1 and TA-2 are the auxiliary thyristors, and
DA-1 and DA-2 are the auxiliary diodes. Thyristors TD-1 and
TD-2 are discharge thyristors. Assuming that the load current
is substantially constant during commutation and that thyris-
tor T-1 is conducting, commutation of T-1 is achieved by
triggering thyristor TA-2 at t = to. (Fig. 6.). An oscillatory
Fig. 4. Semiconductor arrangement in generalized multilevel inverter. current will flow from the dc source, through LD, thyristor
T-1, inductance L, commutation capacitor C, and thyristor
tive voltage level, it can be transferred to any required voltage TA-2 to charge the capacitor to the voltage = 2ED, (t = t1).
level without any commutation process. Similarly, a negative At t = t1, the capacitor current reverses, and the energy
current can be transferred to any voltage level if it is free- stored on the capacitor is fed back to the source through diode
wheeling in the diode at the extreme positive voltage level. The D-1, inductance L, LD, source, and the diode DA-2. As the
following approach illustrates how the commutation process capacitor current increases, the current in thyristor T-1 will be
may be simplified for cases b) and c). reduced to zero at t = t2, thus transferring the total load cur-
The first step during commutation is to trigger a thyristor rent to the capacitor C. Excess commutation current ic - IL
at the extreme positive or negative reference for cases b) and will flow through diode D-1 which will reverse bias thyristor
c), respectively. This will transfer the positive or negative T-1 and turn it off. After reaching the commutation peak,
current automatically to the extreme positive or negative capacitor current will sinusoidally decrease to the load cur-
voltage reference. The second step is to turn off the triggered rent IL (t - t3). After t = t3, the capacitor will be discharged
thyristor and to transfer the current to the freewheeling diode at a constant current IL with the rate of discharge given by
at the complementary reference. The third step is to transfer d V/dt = IL /C. At t = t4=h2r/(LD + L)C the thyristor pair
the current to a desired thyristor. TD-1 and TD-2 is triggered to ensure a complete discharge of
If the PWM switching is used to control the inverter output the commutation capacitor. Load current will be in fact trans-

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1062 1IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983
TABLE II
TRIGGERING SEQUENqCE
CURRENT TRANSFER POSITIVE NE GATI VE
CURRENT CURRENT
Positive to Zero T-1,TA-2,*,TZ1,TZ2 TZ1,TZ2
Reference
-Positive to Neg- T-1,TA-2,*,T-2 T-2
ative Reference
Zero to Positive T-1 T-2,TA-1,*,
Reference T-1

Fig. 5. One phase of three-level inverter with commutation circuit. Zero to Nega- T-1,TA-2,*,T-2 T-2
tive Reference
Negative to zero TZl ,TZ2 T-2,TA-1,*,
Reference TZI,TZ2
Negative to Posi- T-1 T-2,TA-l,*,
CAPACITOR CURRENT tive Reference T-1

= Force commutation process is required. All

remaining transfers may not call -for the
commutation.
* Trigger after commutation delay, which also
includes triggering of TD-1 and TD-2 to
ensure complete discharge of commutation
t2 t3 t4 capacitor.

rent transfer will be

t=
IL *OLD
ED
(a)
In conclusion, it appears that zero commutation voltage on
a commutation capacitor gives the flexibility of programming
any commutation sequence. As a result, any voltage reference
level can be applied to load at any instant, regardless of the
current direction. Also, it can be seen that any particular
reference pair (or all pairs except extreme positive and nega-
CAPACITOR VOLTAGE
Vp=2ED tive) can be eliminated from the programmed sequence, by
blocking the pulses to thyristors, when the current is trans-
/ ferred to either extreme positive or negative reference.
When all such pairs are blocked the inverter will behave like
--II i~~~~ a conventional voltage source inverter. Table II shows the
(b) triggering strategy for the proposed inverter.
Fig. 6. Commutation current and voltage waveforms.
IV. PWM OF A THREE-LEVEL WAVEFORM
ferred to diode D-2 when the capacitor becomes unable to A. Symmetrical Pulsewidth Modulation of a Three-Level
maintain it constant. Under ideal conditions, the capacitor will Waveform
be discharged to zero before TD-1 and TD-2 are triggered.
At t = 27T\/(LD ±r L)C + RDC any required thyristor can be A three-level waveform of a single-phase half-bridge inverter
triggered to transfer a current from diode D-2 to the required is shown in Fig. 3(c). To obtain a voltage control, symmetrical
thyristor. The total time to transfer current from one thyristor or uniform PWM technique can be applied to such a waveform
to another can be given as follows: if certain constraints are followed. It is well-known that with
a sufficient number of switches per cycle, the harmonic con-
tent of a modulated waveform approaches that of the base
t= 27r\(LD+L)C +RDC+ E
ILLD
(14)
d envelope [6].
Fig. 7 shows how the uniform PWM scheme can be applied
An exception for this equation is the time required to transfer to the three-level inverter. The basic constraint followed is to
current to the thyristors at extreme positive and negative ref- have an odd quarter-wave symmetry in a line-to-line voltage
erences; for these cases, the transfer time is 2ir /(LD + L)C waveform. To have this symmetry and uniform pulsewidths,
s.

If no commutation is called, the time for any appropriate cur- the 150° conduction period is divided into five equal seg-

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BHAGWAT AND STEFANOVIC: GENERALIZED STRUCTURE OF MULTILEVEL PWM INVERTER 1063

AAAAAtAAAAAAAAAAAA/

o~~onnnnn
TE~~~~~~~~~~~o n nuul
u~~~~~~L
d u
.r.f.r.f.rd
U0 c J
It
*(I 1) *
2 U.Uuuu,uu
5m pub"

Fig. 7. PWM of three-level inverter.

ments. Ideally, each segment can have any number of equal Analysis of a generalized line-to-line voltage with 5m
width pulses. number of pulses per half-cycle will be divided into two
If m is any integer 1, 2, 3, , m, then to have the quarter- parts: a) when m is odd and b) when m is even.
wave symmetry in an L - L waveform, the chopping fre- From Fig. 1,
quency of the fixed amplitude triangle carrier should be 12
mf, where f is the frequency of the output waveform. With 4 12( )+2
this condition satisfied, it follows that a) the number of pulses A -- O.5Ed sin (nct)(dct)
in the half-cycle of a phase voltage waveform will be 6m; b) 7r Jl2( 1+ m)6
the number of pulses in the half-cycle of a line voltage will be
5m; c) the spacing between the center of each pulse will be
4 Xlm)+6m6
7r/6m rad; d) there will be 2m number of pulses with ampli- +- f I)6 - O.5Ed sin (ncot) (dcot) +
tudes equal to 0.5 ED; e) the number of pulses with the ampli-
tude equal to ED will be 3m; f) the first pulse will be spaced at
7T 2 (1+_m)+_;T
(7/ 12) + (ir/ 1 2m) rad from the reference axis; h) If 6 is the
variable pulsewidth of a pulse, the theoretical maximum pulse- 4 12(+m)+(P-1) v+6
width will be A = iT/6m rad. +- 05 sin (nwt) dwt
OSEd
7TJ7(+ -+p)6m 2
2 m

B. Harmonic Analysis of the Three-Level PWM Waveform

ir r
4 12m+2
6
The Fourier expression for a waveform with an odd quarter-
wave symmetry is
+6- Ed sin (nct) (dwt) +--
17r2
+ 6
-4
4
2m 2
00

e(cot) = z A, sin nuc.t 7r+1Tr +(P-1)6 +r 6

(15)
n=l +_ Ed sin (nwt) (dwt)
4+ 1 2mT+(p_ 1)67 6

where n is an odd number and

4 7ri/2 I4
+- Ed sin (ncwt) (dcot).
An = 7r f(c,t) sin (ncwt) d(wt). (16) 7T .7r_ 5)
2 2

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 1064 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

-=[(
cos 2P-1)[m 6]]
4Ed I~/2- 12F F/
I r
-cos n Icosn 12 ---
m=
- cos n + 3_+_
nt _m
p=L 12L m
2_ 12 2
- 2p-1 )I1 6]]

4Ed /Tr f5
+ cosn 1-- (17)
nir \2 2/
4EdFm //r /2p-1
sin ()
/n5\
RELATIVE PULSE WIUTH
(a)
Isin )
+t2 (sin (-2+ 3
-

n+
± (si (
\
+) n
12\
\ m (2)) I1

(18)
m =I

Similarly, when n is even, .ni

=)-
.5
nrr t /2p- 1 (2
A= ~ (in + i sin
n7r
Lp \2 m
\2
1. m / n- ( 2p l) sin6 ))]
± F, (sin -
m2
Isin (19)

For the specific when m RELATIVE PULSE WIDTH

case, = 1, (18) becomes (b)
Fig. 8. Harmonic amplitude versus relative pulsewidth, m - 1.
4Ed n7r n8 n7t n6
A = sin -sin -+ 2 sin -sin-
nrr 6 2 3 2
C. Discussion
nit n6 The set of Figs. 8(a)-10(b) illustrates the fundamental
+ sin-sin-.- (20 ) and odd harmonics up to the twenty-ninth plotted against the
2 2
relative pulsewidth for three different values of m. It can be
If K is the relative pulsewidth 6/A where A = -r/6m, seen that for m = 1, the eleventh and thirteenth harmonics
can reach up to 37 and 31 percent of the fundamental, while
4Ed nKrr niT
the twenty-third and twenty-fifth harmonics attain up to 17s8
niT nT1
An = sin [sin-+2sin-+sin- (21 and 16.3 percent, respectively. For m = 2, both the eleventh
niT 12 6 3 2 and thirteenth harmonics are reduced below ten percent while
the twenty-third and twenty-fifth harmonics may reach up to
and form = 2, substituting 6 = KA =TKr/6m, (9) becomes 35 and 32 percent, respectively. With m = 3, the twenty-third
and twenty-fifth harmonics are further decreased, and finally,
4Ed nKr 3nTr 5niT 7n7r 9niT the harmonics of a PWM waveform will approach those of the
An = sin- sin- sin 2sin-±2
base envelope. With a properly designed logic circuit, the
nn' 24 24 24 24 24
value of m can be changed automatically as any of the har-
lin1 monics increase to, say, more than ten percent. Thus with a
+ 2sin 242 (2TJ relatively simple modulation scheme, all harmonics including
the fifth and seventh can be kept below ten percent through-

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BHAGWAT AND STEFANOVIC: GENERALIZED STRUCTURE OF MULTILEVEL PWM INVERTER 1065

1'

m=2 m=3
LJ

CL.

11 th
,5/
.1 '.2 .3 .
RELATIVE PULSE WIDTH
(a) (a)

m=3
m=2

5/

-i

/ _
~ ~ ~ 2"9th 1u19th
0 .2 .1
.3.
RELATIVE PULSE-WIDTH RELATIV PULSE WIDTH
(b) (b)
Fig. 9. Harmonic amplitude versus relative pulsewidth, m = 2. Fig. 10. Harmonic amplitude versus relative pulsewidth, m = 3.

out the range of voltage control. Therefore, compared to the the laboratory to deliver a peak load current of 275 A from a
conventional PWM inverter, significant harmonic reduction is 250-V dc bus. A comnmutation circuit was designed to obtain
achieved by a relatively simple modulation scheme. 400 A of peak capacitor current. The following list gives the
designed parameters.
V. EXPERIMENTAL SETUP AND RESULTS Commautation Circuit: C = 25 gF, L = 9 pH, RD = 1.5 2.
First, a simulation of the proposed circuit was performed Power semiconductors: all thyristors GE 365m, all diodes
using digitally controlled analog switches. Three such switches GE A397m.
were used, one connected to positive reference and two others Filter Capacitors: Two 20 000-,F electrolytic capacitor
to the zero and negative references, respectively. Fig. l1(a) banks in series.
shows the waveforms of two phase voltages of a three-phase Fig. 13(a) shows. the line voltage and line current of the
system, while a typical line-to-line voltage is shown in the third designed inverter, when operating with three voltage levels and
trace. Fig. 1l(b) shows the traces of two phase-to-neutral supplying current to the purely inductive load. Fig. 13(b)
voltages. Fig. 1 l(c) shows simulated PWM scheme for m = 2: shows the phase-to-neutral voltage and current for the same
the first two traces show the modulated phase voltages; a load. Fig. 13(c) shows the phase-to-neutral voltage and current
typical PWM line-to-line voltage is shown in the third trace. when the inverter was operated as a six-step inverter. Com-
Fig. 12 shows the spectrum of the third, fifth, seventh, ninth, paring Fig. 13(b) and (c), reduction in the current distortion
and eleventh harmonics for a conventional square-wave in- can be clearly seen.
verter and the proposed three-level inverter. Fig. 14 shows the motor current waveforms of the 5-hp
An actual three-phase multilevel inverter was constructed in three-phase induction motor. Fig. 14(a)-(c) show the no load,

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1 066 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

(a) (a)

(b) (b)

(c) (c)
Fig. 11. (a) Simulated phase and line voltages. (b) Simulated phase- Fig. 12. Harmonic amplitudes. (a) Square-wave inverter phase volt-
to-neutral voltages. (c) Simulated PWM phase and line voltages, age. (b) Three-level inverter phase voltage. (c) Three-level inverter
m = 2. line voltage.
BHAGWAT AND STEFANOVIC: GENERALIZED STRUCTURE OF MULTILEVEL PWM INVERTER

(a)

(b)

(b)

(c)
Fig. 13. (a) Line voltage and current of proposed inverter (100 V/div,
20 A/div). (b) Phase-to-neutral voltage and current of proposed in-
verter (100 V/div and 20 A/div). (c) Phase-to-neutral voltage and
current, when operating as conventional inverter (100 V/div, 20
A/div).

50-percent, and full-load current when the motor was con-

nected to the utility three-phase power lines. Fig. 1 5(a)-(c)
show the same when the motor was connected to the conven-
tional three-phase inverter. The distortions in the motor
current are evident. Fig. 16(a)-(c) show the same when the
motor was connected to the three-level inverter. The distor-
tion in the motor current is clearly reduced.
VI. CONCLUSION
The generalized structure of a inultilevel inverter is de-
scribed. The number of steps, their heights, and widths can be (c)
selected for a given design either to elirninate the specific Fig. 14. Current waveforms of three-phase 5-hp induction motor.
(a) No load. (b) Fifty-percent load. (c) Full load. Power source is
harrnonics or to minimiiize the total harmonic distortion. three-phase utility lines. Scale: 5 A/div for (a), (b); 10 A/div for (c).
1068 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 6, NOVEMBER/DECEMBER 1983

(a) (a)

(b) (b)

(c) (c)
Fig. 15. Current waveforms of three-phase 5-hp induction motor. Fig. 16. Current waveforms of three-phase 5-hp induction motor.
(a) No load. (b) Fifty-percent load. (c) Full load. Power source is (a) No load. (b) Fifty-percent load. (c) Full load. Power source
three-phase six-step inverter Scale: 5 A/div. is three-phase multilevel inverter. Scale: 5 A/div.
BHAGWAT AND STEFANOVIC: GENERALIZED STRUCTURE OF MULTILEVEL PWM INVERTER
A generalized method of thyristor commutation in a multi-
level inverter is also described. For a positive load current, any
thyristor is naturally commutated by gating the thyristor at
the extreme positive reference. After this thyristor is force-
commutated, the load current is transferred to a freewheeling
diode. From then, any desired voltage reference is applied to
the load by triggering the appropriate thyristor. With the
negative load current, an analogous sequence is used in the
lower thyristor group. In order to implement the necessary
commutation sequence, a new versatile commutation circuit
is proposed. The circuit can turn off any thyristor and transfer
the load current to any voltage reference without a need to
precharge the commutation capacitor.
The implemented three-level inverter reduces the harmonic
distortion in the unmodulated line voltage from 31.08 percent
in conventional inverter to 16.86 percent, without sacrificing
the average power. It also significantly reduces the dominant
fifth and seventh harmonics.
In order to achieve voltage control of the proposed three-
level inverter, a simple uniform PWM scheme is described with
the properly selected carrier-to-fundamental frequency ratio.
This scheme limits all harmonics to less than ten percent of the
fundamental throughout the voltage control range. The pro-
posed inverter was designed and tested in the Concordia
University Power Electronics Laboratory. The inverter was
found to perform satisfactorily under all operating conditions.
It is believed that the described multilevel inverter structure,
which does not use any large reactive elements, will signifi-
cantly improve the motor performance and will be suitable for
high-power motor drives and uninterruptible power system
applications.
ACKNOWLEDGMENT
The authors wish to thank the General Electric Company
for providing the thyristors and Professor P. D. Ziogas for the
useful discussions.
REFERENCES
[I] K. E. Dahlberg et al., "Advancing the state-of-the-art-in variable
speed controls," in Conf. Rec. IEEE IAS Annu. Meeting, Oct.
1979, pp. 917-921.
[2] C. W. Flairty, "A 50 KVA adjustable-frequency 23-phase con-
trolled rectifier inverter," presented at the AIEE Industrial Elec-
tronics Symp., Boston, MA, Sept. 20-21, 1961.
[3] R. H. Baker, "Synthesizer circuit for generating three-tier wave-
forms," U.S. Patent 4 135 235 (assigned to Exxon Research and
Engineering Co.), Oct. 31, 1977.
[4] -, "Waveform synthesizer," U.S. Patent 4 137 570 (assigned to
Exxon Research and Engineering Co.), Oct. 31, 1977.
[5] A. Schonung and D. Stemmler, "Static frequency changers with
1069
subharmonic control in conjunction with reversible variable speed
ac drives," Brown Boveri Rev., Aug./Sept. 1964.
[6] H. S. Patel and R. G. Hoft, "Generalized techniques of harmonic
elimination and voltage control in thyristor inverters; Part II-
Voltage control techniques," IEEE Trans. Ind. Appi., vol. IA-10,
pp. 666-673, Sept./Oct. 1974.
[7] P. Bhagwat and V. R. Stefanovic, "New versatile commutation
circuit for PWM inverters," in Conf. Rec. 1980 IEEE IAS Conf.,
pp. 774-784.
[8] P. D. Corey, "Methods for optimizing the waveform of stepped-
wave static inverters," AIEE Paper, cp. 62-1147, Denver, June
1962.
Pradeep M. Bhagwat (S'78-M'81) was born in
Bombay, India. He received the B.E. degree with
honors in electrical engineering from the Univer-
sity of Bombay, India, in 1974, and the M.Eng.
degree from McGill University, Montreal, PQ,
Canada in 1977.
In 1977 he joined Concordia University, Mon-
treal, to work towards the doctorate degree in
electrical engineering where he also helped in
developing the Power Electronics Laboratory.
Since 1981 he has been with the Advanced Elec-
tronics Laboratory of Black and Decker Company as a Senior Engineer.
His current interests include development of the advanced static power
converters and microprocessor applications to power electronics.
V. R. Stefanovic (S'70-M'75-SM'79) was born
in Belgrade, Yugoslavia. He received the Dipi.
Ing. Degree in electrical engineering from the
University of Belgrade in 1964 and the M.Eng.
and Ph.D. degrees from McGill University, Mon-
treal, PQ, Canada in 1969 and 1975, respec-
tively.
After arriving in Montreal in January 1966 he
joined Canadian General Electric, working on
electric drives for steel, paper and cement in-
dustries. In September 1969 he started with
undergraduate teaching at Loyola College, Montreal. When the college
became part of Concordia University in 1974, he developed there a grad-
uate program and a Research Laboratory in Power Electronics and Indus-
trial Drives. He became Assistant Professor in 1970 and Associate
Professor in 1978. In 1979, he joined the University of Missouri as a
Professor of Electrical Engineering while continuing the research activity
in static converters and drives at Concordia University. During the same
time he served as a Consultant to Eaton/Cutler-Hammer, Allen-Bradley,
Teledyne-Inet, General Electric, Etc. In August, 1981 he joined the
Industrial Electronics Development Laboratory, General Electric Com-
pany, Charlottesville, VA, as the Manager of Power Conversion Systems.
Dr. Stefanovic was Chairman of the Industrial Drives Committee, In-
dustry Applications Society, in 1978 and 1979, Chairman of the Motor
Controls Committee, Industrial Electronics Society, 1979-1983, and
Chairman, Industrial Power Conversion Systems Department, Industry
Applications Society, 1981 and 1982.