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13.1 Components
13.2 Theory
Flip-flops are the basic building blocks of sequential circuits. The clocked FFs change
their o/p state depending upon i/p's at certain interval of time synchronized with the
clock pulse applied to it.
Different types of FFs are S-R, J-K, D& T. Their operations are described by the
respective truth tables. MSI chip 7476 incorporates two negative edge triggered Master–
Slave JK flip-flops. The J-K flip-flop can be converted to D & T flip-flop.
The clocked RS flip-flop is like an SR flip-flop but with an extra third input of a standard
clock pulse CLK.
Truth Table
Clk S R Q
0 X X
1 0 0
1 0 1
1 1 0
1 1 1
13.4 JK Flip-Flop
The JK flip-flop is an SRFF with some additional gating logic on the inputs which serve
to overcome the SR=11 prohibited state in the SRFF. A simple JKFF is illustrated below
The block symbol for a J-K flip-flop is a whole lot less frightening than its internal
circuitry, and just like the S-R and D flip-flops, J-K flip-flops come in two clock varieties
(negative and positive edge-triggered)
Truth Table
13.5 T Flip-Flop Using JK Flip-Flop
In case of T flip flop, if the T input is high, the T flip-flop changes state ("toggles")
whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous
value.
T Flip flop can be constructed using JK flip flop as shown in diagram below.
Truth Table
The delay flip-flop (DFF) is unique in that it only has one external input along with a
clock input. The logic symbol for this flip-flip is given below
D Flip flop can be constructed using JK flip flop as shown in diagram below.
Truth Table