Assignment II

Problem Bank 3
The assignment has three parts.
 Part I deals with Cache Memory Management,
 Part II deals with Pipeline Architecture and
 Part III deals with scheduling algorithm.
Resource for Part I : Webinar by Prof. Chandra Shekar and following are the video
links:

Part -1
https://wilp-bits-pilani.webex.com/wilp-bits-pilani/ldr.php?
RCID=b247c211c32ef1437dc48e435a96f82a

Part-2
https://wilp-bits-pilani.webex.com/wilp-bits-pilani/ldr.php?
RCID=5f24bcf08916c161c84eed3c1435ce56

Part-3
https://wilp-bits-pilani.webex.com/wilp-bits-pilani/ldr.php?
RCID=e66dd7d7ba4002bbaf05a2ac17701756

Resource for Part II: Webinar by Prof. Vaibhav and following are the video links:

COSS Webinar-P-1-->
https://dams.bits-
pilani.ac.in/download/715811658aa1643b0a326971305973a4bbfd5f56
COSS Webinar-P-2-->
https://dams.bits-
pilani.ac.in/download/0d9ca13b18c84bcdb317576438b6322dab4a6a8
5

Resource for Part III: Process Management

Use following link to login to “eLearn” portal.
https://elearn.bits-pilani.ac.in
Click on “My Virtual Lab – CSIS”
Using your canvas credentials login in to Virtual lab
In “BITS Pilani” Virtual lab click on “Resources”. Click on “Computer Organization and
software systems” course. Use labcapsule8-Process Management resource.
Submission:
Submission: You will have to submit this documentation file with the name of the file as
your batch number on or before 10th Mar 2019 in canvas only. File submitted by any means
outside CANVAS will not be accepted and marked.

In case of any issues, please drop an email to my TA, Ms. Michelle Gonsalves
(michelle.gonsalves@wilp.bits-pilani.ac.in). Please refrain from sending emails to center
coordinators or faculty who is teaching you.

Caution!!!

We expect you to submit your original work. You are not allowed to share document / other
details about your assignment with other batches implementing the same problem. Any
evidence of such practice will attract severe penalty. We will not distinguish plagiarism as
less or more.

Evaluation:

 The assignment carries 10 Marks

 Grading will depend on

o Contribution of each student in the implementation of the assignment

o Plagiarism or copying will result in -10 marks

 Part I: Cache Memory Management
The bubble sort algorithm implementation using Simulator Testing Language is as follows :

program BubbleSort
var a array(5) byte
a(0) = 5
a(1) = 4
a(2) = 3
a(3) = 2
a(4) = 1

var len byte

var temp byte
var x1 byte
var x2 byte

len = 5
l1 = len - 1

for i = 0 to l1
l2 = len - i - 1
for j=0 to l2
j1 = j + 1
x1 = a(j)
x2 = a(j1)
if x1 > x2 then
temp = a(j1)
a(j1) = a(j)
a(j) = temp
end if
next
for k =0 to 4
write(a(k)," ")
next
writeln("")
next
end

General procedure to convert the given program in to ALP:

 Open CPU OS Simulator. Go to advanced tab and press compiler button
 Copy the above program in Program Source window
 Open Compile tab and press compile button
  In Assembly Code, enter start addressand press Load in Memory button
 Now the assembly language program is available in CPU simulator.
 Set speed of execution to FAST.
 Open I/O console
 To run the program press RUNbutton.

Problem Statement: Consider a direct mapped cache.

Execute the above program by setting block size to 2, 4, 8, 16 and 32 for cache size = 16 and
32. Record the observation in the following table.
Block Cache Miss Hit Miss Comments ( Reason for decrease or
Size size ratio increase in Miss Ratio )

2 16 226 401 36%

4 16 221 406 35.2%

8 16 241 386 38.4%

16 16 171 456 27.2%

32 16 NA NA NA

2 32 135 492 21.5%

4 32 124 503 19.7%

8 32 150 477 23.9%

16 32 98 529 15.6%

32 32 95 532 15.1%

Plot the graph of Cache miss ratio Vs Block size with respect to cache size = 16 and 32.
Comment on the graph that is obtained.
Graph Comments

Initially the miss ratio increased with

increase in block size because of
below points below:

a. The larger the block size, the

less the number of entries in
the cache, and the more the
competition between
program data for these
entries.
b. The larger the block size, the
more time it takes to fetch
this block size from memory.
Increases miss penalty and
consumes more memory
bandwidth.

Later we observed with increase in

block size the miss ratio decreased

Part II: Pipeline Processor

Consider the following program:
MOV #10, R00
MOV #20, R01
MOV #30, R02
INC R02
DEC R01
ADD R00, R02
HLT

Execute the above program using non-pipelined processor and pipelined processor and
answer the following questions:

Non-pipelined Processor:
To enable non-pipelined processor, check “No instruction pipeline” check box in control
panel.

a) How many stages are there in non-pipelined processor? List them

b) Fill in the following table for the case “the execution of above program using non-
pipelined processor.
Clocks Instruction Count CPI Speed up Factor

Non Pipelined processor 39 7 5.57 0.9

c) What are the contents of Register R00, R01 and R02 registers after the execution of the
program?

10, 19, 41

Pipelined processor:
To enable pipelined processor, uncheck “No instruction pipeline” check box in control panel.

a) Fill in the following table with respect to pipelined processor execution of the above
program:

Pipelined processor Clocks Instruction CPI Speed up Data Contents of

conditions Count Factor hazard registers R00, R01
and R02

Check “Do not 15 7 2.14 2.34 0 10,19,11

insert bubbles”
check box

Uncheck “Do not 15 7 2.14 2.34 1 10,19,41

insert bubbles”

b) Is there a way to improve the CPI and Speed up factor? If so give the solution.

Solution:
Fill in the following table for the above solution.
Clocks Instruction Count CPI Speed up Factor
 Part III: Process Scheduling
Consider the following 4 source codes:
Source Code 1:
program My_Pgm1
i=1
for n = 1 to 10
x=i+n
next
end
Source Code 2:
program My_Pgm2
i = 10
for n = 1 to 8
x=i+n
next
end

Source Code 3:
program My_Pgm3
i = 10
for n = 1 to 15
x=i+n
next
end
Source Code 4:
program My_Pgm4
i = 10
for n = 1 to 5
x=i+n
next
end
Create 4 processes P1, P2. P3 and P4 from source codes 1, 2, 3and 4 respectively with
following properties. Fill up the following table:
Scheduling Algorithm : FCFS
Process Arrival Time Waiting time
P1 1
P2 5
P3 3
P4 6
Average waiting time
Scheduling Algorithm : Round Robin with time quantum 5
Process Arrival Time Waiting time
P1 1
P2 5
P3 3
P4 6
Average waiting time
Scheduling Algorithm : Round Robin with time quantum 10
Process Arrival Time Waiting time
P1 1
P2 5
P3 3
P4 6
Average waiting time
Out of three cases, which one is better and why?