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21‐Nov‐2012
Topology: Non‐Synchronous Buck Converter
Controller: Texas Instruments TPS40200
Contents
1. Introduction ...................................................................................................................................... 2
2. Controller .......................................................................................................................................... 3
3. Component Selection........................................................................................................................ 5
4. Efficiency ......................................................................................................................................... 12
5. Loop Compensation ........................................................................................................................ 15
6. Additional Topics............................................................................................................................. 20
7. Application Schematic..................................................................................................................... 23
8. Application BOM ............................................................................................................................. 24
1
1. Introduction
Due to the continuous reduction in voltage level demand for DSP core and I/O power supplies, efficient
conversion from existing bus voltages to newer and lower voltages is required. However, converting one
low voltage to a lower voltage provides a number of challenges to power supply design. Optimal designs
are those which offer high efficiency and fast transient responses, while remaining small in size and low
in cost.
Stepdown or Buck converters offer the most promising solutions. Despite being substantially larger and
noisier than their linear regulator counterparts, Buck converters typically offer much higher efficiency.
The converter operates by applying a pulse width modulator (PWM) waveform to an LC filter, the filter
then averages the PWM waveform resulting in a DC output voltage. (See figure 1.)
Figure 1: Simple Buck Schematic
This application report details the design process of a non‐synchronous stepdown Buck converter,
operating in continuous conduction mode (CCM). The report includes a discussion of trade‐offs and
methodology for the selection of the power stage components. The calculations of power stage losses
are included while an overview of Type 3 loop compensation is provided. Finally, comparisons are made
between experimental results and those obtained through mathematical calculations.
The table below details the Buck regulator design criteria:
Vin (min) 8V
Vin (max) 16V
Vin (nom.) 12V
Vout 5V
Iout 1A
Iripple 20%
Fsw 300KHz
Table 1: Design Criteria
2
2. Controller
The controller selected for the design was a TPS40200, which is a non‐synchronous controller containing
a built in 200mA driver designed to drive high speed P‐channel FETs up to 500kHz. The circuit utilises
voltage mode control and has feed‐forward input voltage compensation. This maintains a constant
PWM gain over the full input voltage range. The error amplifier is biased by a 700mV reference.
Figure 2: TPS40200 Typical Application
Figure 3: TPS40200 Internal Block Diagram
a. Switching Frequency
The operating frequency of the controller is determined by an external resistor RRC, which is connected
from the RC pin to VDD, and a capacitor CRC, which is attached from the RC pin to ground. A clock
frequency of 300KHz was chosen as a suitably high frequency, which allows for smaller capacitors and
inductors, while not resulting in excessive switching transistor losses.
RRC must be kept large enough that the current through it does not exceed 750µA when the internal
switch is discharging the timing capacitor.
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Required Values: RRC = 68.1KΩ
CRC = 470pF
b. Overcurrent Protection
The controller uses a low‐value current sensing resistor Rs in series with the input voltage and the power
FET’s source to detect switching current. When the voltage drop across this resistor exceeds 100mV the
part enters hiccup fault mode at about 2% operation frequency.
To avoid nuisance tripping due to noise pickup, a small RC filter is added to the current sensing network.
Required Values: Rs = 0.047Ω
RF1 = 1KΩ (From Datasheet)
RF2 = 1KΩ (From Datasheet)
CF = 100pF (From Datasheet)
c. SoftStart
The controller also incorporates a soft‐start feature where the output follows a softly rising soft‐start
voltage preventing voltage output overshoot. An external capacitor Css controls the soft‐start interval.
Required Value: CSS = 247µF
4
3. Component Selection
a. MOSFET Switch
The MOSFET breakdown voltage must be greater than the maximum voltage experienced at the switch
node. The maximum input voltage for the application is 16V, however switching the inductor causes
overshoot voltages which can equal this input voltages. Therefore a high breakdown voltage is required
to prevent MOSFET damage. On the other hand, since RDS(On) of the FET rises with breakdown voltage, a
FET with as low breakdown as possible is desirable to minimise conduction losses.
The selection of a suitable power MOSFET also requires knowing both the DC conduction losses and
switching losses in the application. A starting point for the FET selection is to allow 1% or 2% of the
output power for losses at the switch. The result is optimum where the two types of losses are
reasonable balanced.
The output power of the converter is 5W. Therefore the conduction and switching losses should be close
to 50mW each to account for 2% of the output power. This provides a limit for the RDS(On) for the
required MOSFET.
The equations above required knowing the Irms current at the switch. This value was obtained using
Power Stage designer to simulate a simple Buck topology. The equation below can be used to verify the
simulated value.
Due to the high requirements of silicon area for an integrated driver, a cost effective controller will have
a weak driver. This is a major limitation for FET selection. A MOSFET with a large gate charge would be
unsuitable for use with such a weak driver. Higher gate charge also results in higher driver losses.
The driver voltage for the TPS40200 is ‐8V while the driver current is 300mA (figure 4). It is important to
ensure that the relative strength of the driver and the gate charge of the FET are compatible. If the
driver is too weak and the gate charge is too high, switching losses increase.
5
Figure 4: MOSFET Gate Driver
Having considered the factors discussed previously, a Fairchild FDC 658AP SUPERSOT 6 MOSFET was
selected. The PMOS has a breakdown voltage of 30V and an RDS(On) which is below the limiting level.
Shown in the table below is the RDS(On) of the MOSFET for various gate voltages and drain currents.
Figure 5: MOSFET On Characteristics
Figure 6: MOSFET Drain to Source On Resistance
These values must be adjusted according to the specific values for the application. Using the graph in
figure 6, the RDS(On) value can be scaled according to the driver gate voltage of ‐8V and drain current of
1A.
The switching characteristics of the PMOS are shown in the table below.
6
Figure 7: MOSFET Switching Characteristics
Figure 8: MOSFET Gate Charge
The true gate charge, however, must be obtained using the graph in figure 8, using the controller’s gate
voltage of ‐8V and the drain source voltage of ‐12V.
The rise time and fall time values given are not applicable for a driver impedance of less than 6Ω. For an
estimated value, the following calculation is performed:
Shown below are the estimate power losses in the PMOS switch:
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b. Inductor
A good rule of thumb is to select an inductor that produces a ripple current of 10% to 30% of full load DC
current. In this application the device must deliver a maximum of 1A. This requires that the output
inductor’s saturation current to be above 1A plus half the ripple current produced during inductor
switching.
The advantage of lower inductances includes faster transient response, lower DCR, higher saturation
current, and a smaller less expensive part. Too low an inductor however, leads to higher peak currents
which ultimately are bounded by the overcurrent limit set to protect the output FET or by output ripple
voltage.
A low value inductor also has higher ripple current that contributes to ripple voltage across the
resistance of the output capacitors. Fortunately with low ESR ceramic capacitors on the output the
resulting ripple voltage for relatively high ripple currents will be small.
A 47µH inductor from Coilcraft was selected. The inductor has a DCR of 0.1099Ω. The following losses
were obtained using Coilcraft design tools for calculating winding and core losses.
c. Rectifier
Power dissipation is a major limiting factor when selecting a diode. The importance of power loss from
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the Schottky diode is determined by the duty cycle. For a low duty cycle application, the rectifier is
conducting for the majority of the time, and the current that flows through it multiplied by the forward
voltage can be the largest component of losses in the entire controller.
Voltage stress at the diode is typically the maximum input voltage. Additional overshoot caused by poor
layout and fast switching must also be considered. Therefore, to allow for these switching transients a
higher voltage rating must be selected. However, the higher the voltage rating, the higher the forward
voltage, leading to increased losses. A 30V rectifier was selected in this case.
Figure 9: Rectifier Forward Voltage
Where efficiency is paramount choose a diode with minimum forward drop. In this case, a 3A diode was
selected despite the output current being 1A, as the 3A diode offers a lower forward voltage than its 1A
counterpart.
d. Output Capacitor
The output capacitance is chosen to minimise output noise and to guarantee regulation during transient
loads. The capacitance and ESR of the output capacitor determines the magnitude of undershoot or
overshoot during a transient; large overshoots are caused by insufficient output capacitance, while large
voltage ripple is caused by insufficient capacitance as well as high ESR. This condition may be described
by realising that the energy in the stored inductor must be suddenly absorbed by the output
capacitance. Multilayer ceramic chip capacitors provide low impedance and ultra‐low ESR and highest
ripple capability of several Amperes.
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With the gain bandwidth of the TPS40200 being 1.5MHz..3MHz, a loop bandwidth of 10KHz..20Khz
could be expected. Standard designs are measured with 50% load step, and a common approach is to
ensure that output voltage swing is below 3%: 150mV.
In real life, for standard loads the estimated result could be divided by 4, or 2 for dynamic loads.
The output ripple is also dependent on ripple current and ESR of the output capacitor. The decision for
ripple current was taken earlier during the selection of the inductor. A common definition for the ripple
voltage at standard supplies is below 1% of the output voltage.
The influence of DC bias on capacitance must be taken into account. For example, a DC bias of 80%,
output voltage 5V, and rated voltage 6.3V decreases the effective capacitance to roughly 40% of the
initial value. Therefore Ceff = 40µF instead of the expected 100µF. This will have an effect on loop
compensation and requires more capacitors than expected.
Shown in the figure below is a graph of effective capacitance and ESR experienced at a specific DC Bias
and switching frequency. The combined ESR of the required output capacitors is approximately 0.6mΩ.
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Figure 10: DC Bias Influence on Impedance and ESR
e. Input Capacitor
Unlike the output capacitors, current stress on input is much bigger for Buck topology. If the impedance
of the source is large, reflected ripple to the load will occur, as well as conducted emission and EMI. If
the impedance of the source is low, use the same value and the same geometry as used for the output
capacitance. The best practice is to use low‐equivalent series resistance ceramic capacitors.
If the source impedance is large, add an optional bulk capacitor and electrolytic related to the
impedances. For highest current applications, no suitable electrolytes might be available. Insert a filter
inductor between bulk capacitor and MLCC to prevent the electrolytic from excessive pulsed currents
causing damage or poor MTBF.
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4. Efficiency
a. Estimated Efficiency
Losses @ 12V input and full load 1A: Typical Value (mW)
MOSFET Pcond 31
MOSFET Psw 46
MOSFET Pdrv 18.7
Inductor Pdcr 167
Inductor Pcore 17
Shottky Diode Pcond 220.5
Input Capacitors 2
Output Capacitors <1
Current Sense Resistor 20
Feedback Divider 1.24
Housekeeping TPS40200 18
Total Losses 552mW
Estimated Efficiency 88.9%
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b. Measured Efficiency
Vin (V) Iin (A) Vout (V) Iout (A) Pin (W) Pout (W) Eff %
12 0.469 4.96 1.02 5.628 5.0592 89.89339
12 0.424 4.96 0.94 5.088 4.6624 91.63522
12 0.38 4.96 0.84 4.56 4.1664 91.36842
12 0.336 4.96 0.74 4.032 3.6704 91.03175
12 0.284 4.96 0.62 3.408 3.0752 90.23474
12 0.241 4.98 0.52 2.892 2.5896 89.54357
12 0.198 4.98 0.44 2.376 2.1912 92.22222
12 0.155 4.98 0.34 1.86 1.6932 91.03226
12 0.105 4.98 0.23 1.26 1.1454 90.90476
12 0.062 4.98 0.13 0.744 0.6474 87.01613
12 0.04 5 0.08 0.48 0.4 83.33333
Vin (V) Iin (A) Vout (V) Iout (A) Pin (W) Pout (W) Eff %
8 0.693 4.96 1.02 5.544 5.0592 91.25541
8 0.66 4.96 0.97 5.28 4.8112 91.12121
8 0.561 4.98 0.84 4.488 4.1832 93.20856
8 0.495 4.98 0.74 3.96 3.6852 93.06061
8 0.419 4.98 0.62 3.352 3.0876 92.11217
8 0.353 4.98 0.52 2.824 2.5896 91.69972
8 0.289 4.98 0.44 2.312 2.1912 94.77509
8 0.226 4.98 0.34 1.808 1.6932 93.65044
8 0.152 5 0.23 1.216 1.15 94.57237
8 0.088 5 0.13 0.704 0.65 92.32955
8 0.057 5 0.08 0.456 0.4 87.7193
13
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5. Loop Compensation
High bandwidth with good phase margin is a solution with high efficiency. For stable systems, a good
practice is to target a phase margin of 60 degrees at the crossover frequency.
a. Error Amplifier Open Loop Limit
The gain bandwidth of the internal operational amplifier in the TPS40200 places limitations on the
bandwidth of the loop. The chosen switching frequency of the regulator also limits this loop bandwidth.
As can be seen in figure 12, the TPS40200 has an open loop gain of 60dB and a bandwidth of 3MHz.
Figure 11: TPS40200 Error Amplifier
b. Transfer Function of Power Stage
Figure 12: Output Power Stage
The output of the power stage consists of a second order low pass filter as shown in figure 13. The
transfer function of this power stage can be plotted using the Thomson equations below. The plotted
transfer function can be seen in the Bode plot in figure 15.
c. PWM Gain
The additional gain from the PWM must also be considered. The modulator gain is the input voltage
15
divided by the saw‐tooth amplitude, and requires the use of Voltage Feed Forward to keep a constant
ratio while the input voltage changes. As can be seen in figure 14 the modulator gain is fixed at 20dB.
Figure 13: TPS40200 PWM
d. System Analysis
The power stage gain and the modulator gain must then be added, and in theory the combination
creates a system that won’t be stable. Phase has to be boosted by two zeros, which have to be placed
below the LC corner frequency. On the other hand, two poles have to be positioned. To achieve a
reasonable bandwidth the poles should be placed a decade above the crossover frequency. If the poles
are placed too close to the switching frequency, the ripple will be amplified.
A suitable decision for crossover frequency has to be made. 1/10 of the switching frequency, so 30kHz is
the upper limit. However, the low gain of the error amplifier will not permit this as the gain bandwidth
boundary will be violated.
The Bode plot in figure 15 describes the overall system and includes the ‘Double‐Pole, Double Zero’
compensation method. A crossover frequency of 20kHz is targeted.
16
Figure 14: Bode Plot
e. Compensation Calculation
17
Figure 15: Type 3 Compensation Network
An Excel spread sheet TI SLUC263C was used to crosscheck our calculations (figure 17).
Figure 16: Loop Simulation
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f. Measured Loop
Figure 17: Measured Loop Response
The table below summarises the results from Figure 19.
Bandwidth (kHz) 19.8
Phase Margin 69.8°
Slope (20dB/decade) ‐1.01
Gain Margin (dB) 14.74dB
Slope (20dB/decade) ‐1.3
19
6. Additional Topics
a. Snubber Circuit
The purpose of the Snubber circuit is to attenuate the high frequency oscillations that can occur at the
switch node. The target of the additional circuit is to increase the oscillation period by a factor of two,
and at the same time, to decrease the amplitude of the initial overshoot by a factor of two.
Figure 18: Snubber Circuit
Figure 19: Switch Node With and Without Snubber Circuit.
• Without Snubber: • With Snubber:
– Overshoot: 4.6V – Overshoot: 1.2V
– Period: 6.4ns – Period: 11.2ns
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b. Input Filter
The input filter, consisting of a ‘PI’ layout, is included to completely cancel out the reflected ripple at the
input. This helps to reduce EMI, however, at an additional cost to the overall converter.
Figure 20: Input Filter
Figure 21: Effect of Filter on Input Signal
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c. Transient Response
The figure below displays the response of the loop to a 50% step in the load. As can be seen in the
diagram in Figure 23, the crossover frequency of the loop can be deduced from a quick investigation of
the transient.
Figure 22: Load Transients
Figure 23: Transient Response
22
7. Application Schematic
Figure 24: Application Schematic (Note: True component values can be found in the BOM)
23
8. Application BOM
24
30V, -4A, 50mΩ
Resistor, Chip,
1 R1 68.1k 68.1K-Ohms, 1/16- 0603 Std Std
W, 1%
Resistor, Chip, 1/8W,
1 R2 0.047 1206 CRCW1206-xxxx-F Vishay
1%
Resistor, Chip, 1k-
1 R3 1.0k 0603 Std Std
Ohms, 1/16-W, 1%
Resistor, Chip, 0-
1 R4 0 0603 Std Std
Ohms, 1/16-W, 1%
Resistor, Chip, 31.6k-
1 R5 31.6k 0603 Std Std
Ohms, 1/16-W, 1%
Resistor, Chip, 2k-
1 R6 1k 0603 Std Std
Ohms, 1/16-W, 1%
Resistor, Chip, 100k-
1 R7 100k 0603 Std Std
Ohms, 1/16-W, 1%
Resistor, Chip, 49.9-
1 R8 49.9 0603 Std Std
Ohms, 1/16-W, 1%
Resistor, Chip,
1 R9 16.2k 16.2K-Ohms, 1/16- 0603 Std Std
W, 1%
Resistor, Metal Film,
1 R111 TBD 1206 Std Std
1/4 watt, ± 5%
IC, Low Cost Sync
1 U1 TPS40200D SO-8 TPS40200D TI
Buck Controller
25