Dr.

Sreenivasa Rao Ijjada

Dept of Electronics and Communication Engineering

GITAM University, Visakhapatnam

Module: I Lecture Notes

Introduction to MOS Technology

Dr.Sreenivasa Rao Ijjada Dept of Electronics & Communication Engineering GITAM University
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Module: I Introduction to MOS Technology

Materials: Materials can be classified in three groups according to their electron

configuration and their valency. They are conductors, semiconductors and insulators.

Conductors: conducts electricity with little resistance because the atoms have only one
electron on the out-most layer or shell, called valence electron, which is only loosely bound
to the atom and can easily become a free electron freely movable under an applied voltage to
conduct electricity.

EX: Copper(Cu) =2+8+18+1=29), silver (Ag) =2+8+18+18+1=47 and gold (Au)

=2+8+18+32+18+1=79

Insulators: On the other hand, insulators do not conduct electricity as no free electrons exist
in the material. Ex: wood, rubber, and Bakelite

The table showing the maximum number of electrons in each shell, In general, there are 2n2
electrons in the nth shell. However, each level is not necssarily completely filled, and the
outmost layer, the valence shell, can only have no more than 8 valence electrons.

Semiconductors: The conductivity of those elements with four valence electrons in the
carbon group is not as good as the conductors but still better than the insulators, and they are
given the name semiconductors.

Ex: The two semiconductors of great importance are silicon (Si)=2+8+4=14 and germanium
(Ge)=2+8+18+4=32, both of which have four valence electrons. Their crystal structure lattice
has a tetrahedral pattern with each atom sharing one valence electron with each of its four
neighbors to form the covalent bonds.

Intrinsic semiconductor: If an electron gains enough thermal energy (1.1 eV for Si or 0.7
eV for Ge), it may break the covalent bond and becomes a free electron of negative charge,
while leaving a vacancy or a hole of positive charge. In an electric field, a free electron may
move to a new location to fill a hole there, i.e., both such electrons and holes contribute to
electrical conduction. Such crystal is called intrinsic semiconductor.

Intrinsic Semiconductors–No impurities and lattice defects in its crystal structure

–If thermal or optical energy (E > Eg)→ break covalent bond →free electron and hole
–Electrons and holes are created in pairs,so no= po ≡ ni (at thermal equilibrium)

Main point: At room temperature, relatively few electrons gain enough energy to become free
electrons, the overall conductivity of semiconductors is low, thereby their name
semiconductors. –Increasing temperature leads to better conductivity
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Elemental semiconductors – Si and Ge –compose of single species of atoms

Compound semiconductors – combinations of atoms of column III and column V and some
atoms from column II and VI. (Combination of two atoms results in binary compounds).
There are also three-element (ternary) compounds (GaAsP) and four-element (quaternary)
compounds such as InGaAsP.

Solid state structures: A crystalline solid is distinguished by the atoms making the crystal
are arranged in a periodic fashion. There is some basic arrangement of atoms that is repeated
throughout the entire solid. Thus the crystal appears exactly the same at one point as it does at
a series of other equivalent points, once the basic periodicity is discovered. However, some
have no periodic structure at all (amorphous solids), and other are composed of many small
regions of single-crystal material (polycrystalline solids).

The periodic arrangement of atoms in crystal is called the lattice; the lattice contains a
volume, called a unit cell, which is representative of the entire lattice and is regularly
repeated throughout the crystal.

1. Semiconductors & Semiconductor materials:

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 CdS Cadmium(II) Sulphide(VI)
GaAs Gallium(III) Arsenide(V)
GaN Gallium (III) Nitride(V)
GaP Gallium (III) phosphide(V)
PbS Lead(IV) Sulphide(IV)
SiC Silicon(IV) Carbide(IV)

Doped Semiconductors: The conductivity of semiconductor material can be improved by

doping, i.e., by adding an impurity element with either three or five valence electrons, called,
respectively, trivalent and pentavalent elements. A semiconductor is called either intrinsic or
extrinsic, depending on whether it contains any doped impurity.

N-type semiconductor: When a small amount of pentavalent donor atoms (e.g., phosphorus
(P) and Arsenic (As)) is added, a silicon atom in the lattice may be replaced by a donor atom
with four of its valence electrons forming the covalent bounds and one extra free electron.
This is an N-type semiconductor whose conductivity is much improved compared to the
intrinsic semiconductors, due to the extra free electrons in the lattice, which are called
predominant or majority current carriers. There also exist some tiny number of holes called
minority carriers.

P-type semiconductor: When a small amount of trivalent acceptor atoms (e.g., boron (B)
and aluminum (Al)) is added, a silicon atom in the lattice may be replaced by an acceptor
atom with only three valence electrons forming three covalent bounds and a hole in the
lattice. This is a P-type semiconductor whose conductivity is also much improved compared
to the intrinsic semiconductors, due to the holes in the lattice, which are called predominant

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or majority current carriers. There also exist some tiny number of free electrons called
minority carriers.

PN-Junction : When P-type and N-type materials are in contact with each other, a PN-
junction is formed due to these two effects:

Diffusion: Although both sides are electrically neutral, they have different concentration of
electrons (the N-type) and holes (the P-type), and a diffusion current is formed by the
diffusion of the higher concentration of the freely movable electrons in the N-type material
that move across the PN-junction from the N side to the P, due to the thermal motion. They
arrive at the P side to fill some of the holes there. Equivalently, we can also consider the
holes are diffusing from the P side to the N side.

Electric Field: If no other forces were involved, the diffusion would carry out continuously
until the free electrons and holes are uniformly distributed across both materials. However, as
the result of the diffusion process, electrical field is gradually established, negative on the
side of P-type material due to the extra electrons, positive on the side of N-type material due
to the loss of free electrons. This electrical field prevents further diffusion as the electrons on
the N-type side are expelled from the P-type side by the electrical field.

The effects of both diffusion and electric field eventually lead to an equilibrium where the
two effects balance each other so that there are no more charge carriers (free electrons or
holes) crossing the PN-junction. This region around the PN-junction, called the depletion
region as there no longer exist freely movable charge carriers, becomes a barrier between the
two ends of the material that prevent current to flow through.

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MOS technology

o nMOS
o pMOS
o CMOS
o Bicmos

Metal Oxide Semiconductor FET

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is one type of FET. In these
transistors the gate terminal is electrically insulated from the current carrying channel so that
it is also called as Insulated Gate FET (IG-FET). Due to the insulation between gate and
source terminals the input resistance of MOSFET may be very high such as in mega ohms
(MΩ).

Like JFET the MOSFET also acts as a voltage controlled resistor when no current flows into
the gate terminal. The small voltage at the gate terminal controls the current flow through the
channel between the source and drain terminals.

MOSFET has three terminals, such as Drain (D), Source (S) and Gate (G) and also one more
terminal called substrate or Body (B) is used in the circuit connections. MOSFETs are two
types, N-channel (NMOS) and P-channel (PMOS). The MOSFETs are basically classified in
to two forms they are Depletion type and Enhancement type transistors.

2. Enhancement mode MOS transistor:

The Enhancement mode MOSFET is equivalent to “Normally Open” switch and these types
of transistors require gate-source voltage to switch ON the device. The symbols of both N-
channel and P-channel transistors are shown below.

Symbols of Enhancement Mode MOSFET

The broken line is connected between the source and drain which represents the enhancement
mode type. In enhancement mode MOSFETs the conductivity increases by increasing the
oxide layer which adds the carriers to the channel. This oxide layer is called as ‘Inversion
layer’. The channel is formed between the drain and source in the opposite type to the
substrate, such as N-channel is made with a P-type substrate and P-channel is made with an
N-type substrate. The conductivity of the channel due to electrons or holes depends on N-
type or P-type channel respectively.

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The basic structure of the MOSFET is shown in the figure. In both enhancement and
depletion modes of MOSFETs an electric field is produced by gate voltage which changes the
flow charge carriers, such as electrons for N-channel and holes for P-channel. The gate
terminal is injected into the thin metal oxide insulated layer at the top and two N-type regions
are used below the drain and source terminals.

Internal Structure of MOSFET

The channel between drain and source is an N-type which is formed opposite to the P-type
substrate. It is easy to bias the MOSFET gate terminal for the polarities of either positive
(+ve) or negative (-ve). If there is no bias at the gate terminal, then the MOSFET is generally
in non-conducting state so that these MOSFETs are used to make switches and logic gates.

If the positive voltage (+VGS) is applied to the N-channel gate terminal, then the channel
conducts and the drain current flows through the channel. If this bias voltage increases to
more positive then channel width and drain current through the channel increases to some
more. But if the bias voltage is zero or negative (-VGS) then the transistor may switch OFF
and the channel is in non-conductive state. So now we can say that the gate voltage of
enhancement mode MOSFET enhances the channel.

IV Characteristics of Enhancement Mode MOSFET Circuit symbols EMOSFET

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Enhancement mode MOSFET transistors are mostly used as switches in electronic circuits
because of their low ON resistance and high OFF resistance and also because of their high
gate resistance. These transistors are used to make logic gates and in power switching
circuits, such as CMOS gates, which have both NMOS and PMOS Transistors.

The V-I characteristics of enhancement mode MOSFET are shown above which gives the
relationship between the drain current (ID) and the drain-source voltage (VDS). From the
above figure we observed the behavior of an enhancement MOSFET in different regions,
such as ohmic, saturation and cut-off regions.

MOSFET transistors are made with different semiconductor materials. These MOSFETs have
the ability to operate in both conductive and non-conductive modes depending on the bias
voltage at the input. This ability of MOSFET makes it to use in switching and amplification.

3. Depletion mode MOS transistor:

The depletion mode MOSFETs are generally known as ‘Switched ON’ devices, because
these transistors are generally closed when there is no bias voltage at the gate terminal. The
depletion type of transistors requires gate – source voltage (VGS) to switch OFF the device.
The symbols for depletion mode of MOSFETs are shown in fig. In the symbols observe the
fourth terminal substrate is connected to the ground, but in discrete MOSFETs it is connected
to source terminal. The continuous thick line connected between the drain and source
terminal represents the depletion type. The arrow symbol indicates the type of channel, such
as N-channel or P-channel.

Symbols of Depletion Mode MOSFET

In this type of MOSFETs a thin layer of silicon is deposited below the gate terminal. The
depletion mode MOSFET transistors are generally ON at zero gate-source voltage (VGS). The
conductivity of the channel in depletion MOSFETs is less compared to the enhancement type
of MOSFETs.

If the gate voltage increases in positive, then the channel width increases in depletion mode.
As a result the drain current ID through the channel increases. If the applied gate voltage more
negative, then the channel width is very less and MOSFET may enter into the cutoff region.
The depletion mode MOSFET is rarely used type of transistor in the electronic circuits.

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 Characteristic Curve of Depletion Mode MOSFET

The V-I characteristics of the depletion mode MOSFET transistor are given above. This
characteristic mainly gives the relationship between drain- source voltage (VDS) and drain
current (ID). The small voltage at the gate controls the current flow through the channel.

The channel between drain and source acts as a good conductor with zero bias voltage at gate
terminal. The channel width and drain current increases if the gate voltage is positive and
these two (channel width and drain current) decreases if the gate voltage is negative.

4. NMOS FABRICATION PROCESS

Step 1: Processing is carried on single crystal silicon of high purity on which required P
impurities are introduced as crystal is grown. Such wafers are about 75 to 150 mm in
diameter and 0.4 mm thick and they are doped with say boron to impurity concentration of 10
to power 15/cm3 to 10 to the power 16 /cm3.

Clean substrate

Step 2: A layer of silicon dioxide (SiO2) typically 1 micrometer thick is grown all over the
surface of the wafer to protect the surface, acts as a barrier to the dopant during processing,
and provide a generally insulating substrate on to which other layers may be deposited and
patterned.

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 Silicon dioxide(SiO2) grown at the surface of the wafer

Step 3: The surface is now covered with the photoresist which is deposited onto the wafer and
spun to an even distribution of the required thickness.

substrate surface covered with photoresist

Step 4: The photo resist layer is then exposed to ultraviolet light through masking which
defines those regions into which diffusion is to take place together with transistor channels.

• The opaque region at the mask allow the ultraviolet light to hit the surface of the
photoresist at the substrate and making it dissolve.

Photo-mask is in position for patterning

Dr.Sreenivasa Rao Ijjada Dept of Electronics & Communication Engineering GITAM University
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 UV light exposed to the substrate

Photoresist surface that hit by the UV light dissolve

The uncovered dissolve while the covered region remain

Step 5: The substrate now is ready to be etched to remove the remaining photoresist at the
substrate and to create an opening at the substrate. In this process, Hydrofluoric acid is used
as its etch acid.

hydrofluoric acid used as etch acid

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 the remaining photoresist removed and an opening to the substrate created.

Step 6: A layer of the thin oxide is form SiO2 (0.1 micrometer typical) is grown over the
entire chip surface at high temperature.

A layer of thin oxide grown at the surface of the substrate

Step 7: The polysilicon layer consists of heavily doped polysilicon deposited at the surface of
the substrate by chemical vapor deposition (CVD).

Polysilicon is deposited at the surface of the substrate.

Step 8: Photoresist is done for the second time at the surface of the substrate.

Substrate is coated with photoresist

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Step 9: The photolithography process also done for the second time. The process is done to
create a new pattern to make a polysilicon gate at the center of the substrate.

Photo-mask is in position for patterning

UV light exposed to the substrate

Photoresist surface that hit by the UV light dissolve

The uncovered dissolve while the covered region remain

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Step 10: The substrate is now etch with hydrofluoric acid to remove the remaining photoresist
and polysilicon. As a result , a polysilicon gate is formed at the center of the substrate.

hydrofluoric acid used as etch acid

polysilicon gate created

Step 11: In this process, Substrate is bombarded by an amount of arsenic or phosphorus

electron to create N region to form drain and source.

Arsenic or phosphorus ion bombarded at the substrate.

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 N region formed at the substrate representing source and drain

Step 12: After the ion implantation done, the annealing process is conducted to repair the
single crystal structure of the substrate and active the dopant.

The annealing process done to repair the single crystal structure

Step 13: Oxidation process is conducted once more to grow an insulating oxide at the
substrate

The growth of insulating oxide

Step 14: Photoresist is conducted once more at the surface of the substrate.

Photoresist coated the substrate

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Step 15: Another photolithography is done to create an opening to metallization process

Masking process

UV light exposed to the substrate

Photoresist surface that hit by the UV light dissolve

The uncovered dissolve while the covered region remain

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Step 16: The substrate is now etched remove the remaining photoresist. As a result creating
an opening for metallization process.

Etching process to remove photoresist and create an opening

An opening created through etching

Step 17: The substrate then has metal (aluminum) deposited over its surface to a thickness
typically of 1 micrometer. Aluminum evaporated to cover surface. This metal layer is then
masked and etched to form the required interconnection pattern.

Aluminum evaporated to cover the surface of the surface

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 Aluminum etched to form Metal contact

Step 18: Then passivation layer is created with an oxide layer to protect against
contamination and increase electrical stability at the substrate.

The substrate then coated by the passivation layer

5. CMOS Fabrication process:

o N-well,
o P-well
o Twin tub
o SOI.

A P-well has to be created on a N-substrate or N-well has to be created on a P-substrate.

N-well Process: Fabrication of CMOS is described using the P-substrate, in which the NMOS
transistor is fabricated on a P-type substrate and the PMOS transistor is fabricated in N-well.
The fabrication process involves twenty steps, which are as follows:

Step1: Substrate: First choose a substrate as a base for fabrication. For N- well, a P-type
silicon substrate is selected.

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Step2: Oxidation: The selective diffusion of n-type impurities is accomplished using SiO2
as a barrier which protects portions of the wafer against contamination of the substrate. SiO2
is laid out by oxidation process done exposing the substrate to high-quality oxygen and
hydrogen in an oxidation chamber at approximately at 1000 degree centigrade.

Step3: Photoresist: At this stage to permit the selective etching, the SiO2 layer is subjected
to the photolithography process. In this process, the wafer is coated with a uniform film of a
photosensitive emulsion.

Step4: Masking: This step is the continuation of the photolithography process. In this step, a
desired pattern of openness is made using a stencil. This stencil is used as a mask over the
photoresist. The substrate is now exposed to UV rays the photoresist present under the
exposed regions of mask gets polymerized.

Step5: removal of unexposed Photoresist: The mask is removed and the unexposed region
of photoresist is dissolved by developing wafer using a chemical such as Trichloroethylene.

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Step6: Removal of SiO2 using acid etching (Etching): The wafer is immersed in an etching
solution of hydrofluoric acid, which removes the oxide from the areas through which dopants
are to be diffused.

Step7: Removal of photoresist: During the etching process, those portions of SiO2 which
are protected by the photoresist layer are not affected. The photoresist mask is now stripped
off with a chemical solvent (hot H2SO4).

Step8: Formation of the N-well: The n-type impurities are diffused into the p-type substrate
through the exposed region thus forming an N- well.

Step9: Removal of SiO2: The layer of SiO2 is now removed by using hydrofluoric acid.

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Step10: Deposition of polysilicon: The misalignment of the gate of a CMOS transistor
would lead to the unwanted capacitance which could harm circuit. So to prevent this “Self-
aligned gate process” is preferred where gate regions are formed before the formation of
source and drain using ion implantation. Chemical Vapor Deposition (CVD) process is used
to deposit a very thin layer of gate oxide.

Polysilicon is used for formation of the gate because it can withstand the high temperature
greater than 80000c when a wafer is subjected to annealing methods for formation of source
and drain. Polysilicon is deposited by using Chemical Deposition Process over a thin layer of
gate oxide. This thin gate oxide under the Polysilicon layer prevents further doping under the
gate region.

Step11: Removing the layer barring a small area for the Gates: Except the two small
regions required for forming the Gates of NMOS and PMOS, the remaining layer is stripped
off.

Step12: Oxidation process: Next, An oxidation layer is deposited over the wafer which acts
as a shield for further diffusion and metallization processes.

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Step13: Masking and N-diffusion: By using the masking process small gaps are made for
the purpose of N-diffusion.

The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for the
formation of the terminals of NMOS.

Step14: Oxide stripping: The remaining oxidation layer is stripped off.

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Step15: P-diffusion: Similar to the above N-diffusion process, the P-diffusion regions are
diffused to form the terminals of the PMOS.

Step16: Thick field oxide: Before forming the metal terminals a thick field oxide is laid out
to form a protective layer for the regions of the wafer where no terminals are required.

Step17: Metallization: This step is used for the formation of metal terminals which can
provide interconnections. Aluminum is spread on the whole wafer.

Step18: Removal of excess metal: The excess metal is removed from the wafer layer.

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Step19: Terminals: The terminals of the PMOS and NMOS are made from respective gaps.
In the gaps formed after removal of excess metal terminals are formed for the
interconnections.

Step20: Assigning the names of the terminals of the NMOS and PMOS

Fabrication of CMOS using P-well process: Among all the fabrication processes of the
CMOS, N-well process is mostly used for the fabrication of the CMOS. P-well process is
almost similar to the N-well. But the only difference in p-well process is that it consists of a
main N-substrate and, thus, P-wells itself acts as substrate for the N-devices.

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Twin tub-CMOS Fabrication Process: In this process, separate optimization of the n-type
and p-type transistors will be provided. The independent optimization of Vt, body effect and
gain of the P-devices, N-devices can be made possible with this process.

Different steps of the fabrication of the CMOS using the twintub process are as follows:

• Lightly doped n+ or p+ substrate is taken and, to protect the latch up, epitaxial layer is
used.
• The high-purity controlled thickness of the layers of silicon are grown with exact
dopant concentrations.
• The dopant and its concentration in Silicon are used to determine electrical properties.
• Formation of the tub
• Thin oxide construction
• Implantation of the source and drain
• Cuts for making contacts
• Metallization

By using the above steps we can fabricate CMOS using twintub process method.

6. BiCMOS Technology: BiCMOS technology is a combination of Bipolar and CMOS

technology. CMOS technology offers less power dissipation, smaller noise margins, and
higher packing density. Bipolar technology, on the other hand, ensures high switching and
I/O speed and good noise performance. It follows that BiCMOS technology accomplishes
both - improved speed over CMOS and lower power dissipation than bipolar technology. The
main drawback of BiCMOS technology is the higher costs due to the added process
complexity.

CMOS Changes for Bipolar

P+ Substrate P- Substrate
Buried N+/P-Layer
P- EPI intrinsic doped EPI-Layer
N-Well / P-Well
Well drive-in reduced drive time
Poly Buffer Locos high pressure Oxidation

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 Deep Collector/N+ Resistor
Base/P Resistor

Implant
Gate Oxidation (200 )
Poly Deposition/Doping Poly Deposition
Emitter Pattern/Etch
Implant Poly Emitter
Pattern/Etch Poly
LDD Pattern/Implant
SWO Deposition/Etch
Pattern/Implant N+/P+ S/D
Anneal S/D Anneal optimized for Emitter

The integration of the bipolar process steps into the baseline CMOS process flow is given by
First, the P+ substrate is replaced by a P- substrate material to incorporate the NPN device
into the N-well of the PMOS device.

This lower doped substrate increases the susceptibility for latchup. To improve latchup
immunity retrograde N-well doping is used. The retrograde doping can be either achieved by
high energy ion implantation or by using buried layers. With the first approach no epitaxial
layer is required, but ion implantation damage has to be considered. By using buried layers a
relatively thick and expensive epitaxial layer has to be grown on top of the substrate. This
epitaxial layer hosts the collector of the NPN as well as the P-well and the N-well of the
CMOS devices. The epitaxial deposition process must be optimized to reduce material
defects and minimize auto doping.

7. Comparison between CMOS, BiCMOS and Ga As

CMOS BIPOLAR GaAs

Low power dissipation High power dissipation Medium power dissipation

Low current drive High current drive Low current drive

High input impedance Low input impedance High input impedance

High noise margin Medium noise margin Low noise margin

Medium speed of operation High speed of operation Very high speed of

operation

High voltage swing Low voltage swing Low voltage swing

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High packing density Low packing density High packing density

High delay sensitivity Low delay sensitivity High delay sensitivity

Low output drive High output drive Low output drive

Bidirectional Unidirectional Bidirectional

Reasonable switching
Ideal switching device Non ideal switching device
device

8. Integration levels:

9. Moore’s law: Moore's Law is the observation made in 1965 by Gordon Moore, co-founder
of Intel that the number of transistors per square inch on integrated circuits had doubled every
year since the integrated circuit was invented. Moore predicted that this trend would continue
for the foreseeable future. In subsequent years, the pace slowed down a bit, but data density
has doubled approximately every 18 months. Most experts, including Moore himself, expect
Moore's Law to hold true until 2020-2025.

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9.1 Advantages of IC technology:

o Miniaturization of circuit
o Higher package density
o High circuit speeds
o Low power consumption
o Reduced cost per function
o Reduced physical size
o High reliability
o Suitability for operation
o Easy replacement

9.2 Dis-advantages of IC

o Coils or indicators cannot be fabricated.

o It can be handle only limited amount of power.
o High grade P-N-P assembly is not possible.
o It is difficult to be achieved low temperature coefficient.
o The power dissipation is limited to 10 watts.
o Low noise and high voltage operation are not easily obtained.
o Inductors and transformers are needed connecting to exterior to the semiconductor
chip as it is not possible to fabricate inductor and transformers on the semiconductor
chip surface.

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 o Inductors cannot be fabricated directly.
o Low noise and high voltage operation are not easily obtained.

9.3 Semiconductor

TSMC Taiwan Semiconductor Manufacturing Taiwan

Company Limited (TSMC)
UMC United Microelectronics Corporation Taiwan
SMIC Semiconductor Manufacturing International China
Corporation
Tower jazz Tower semiconductor ltd US
Global foundries
Samsung
Apple

10. Design challenges: In producing smaller systems and reducing power dissipation, IC
manufacturers are facing major design challenges due to the following constraints

o Power density(W/cm2)
o High dynamic power dissipation
o High static power dissipation

The design challenges can be overcome by improvement in design, material and

manufacturing processes.

Major aspects of successful designs are

o Approach to system design cycle

o Workable transistors models

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