An Efficient BIST Design Using LFSR-ROM Architecture'
Lijian Li and Yinghua Min
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080
Abstract
Built-in self-test (BIST) is considered to be one of the
most promising approaches to testing modern ICs. This
paper proposes an efficient BIST design using LFSR-ROM
architecture. I t takes advantage of don 't-care bits that
remain during the process of test pattern generation. It
determines the target fault set with an ATPG tool to
achieve predefined fault coverage. It compresses the size
of ROM in two dimensions to reduce the number of test
patterns and ROM outputs as well. Experimental results
demonstrate that the proposed scheme is able to reduce
hardware overhead several-fold.
1 Introduction
With the rapid development of IC technology, transistor
density and operational frequency of modern ICs are higher
and higher. To test such kind of IC is challenging, because
it needs an effective test approach to deal with circuits with
large size and a sophisticated tester to generate and capture
test signals under high operation frequency. Built-in self-
test (BIST) is considered to be one of the most promising
approaches to solving this problem. There are many
advantages of BIST. First, it can test a chip at-speed and
thus reduces test application time. Second, it decreases
the dependency on an expensive tester. Finally, it can test a
chip in-system or in the field, that is, on-line testing, which
is considered very important to some systems that need to
guarantee high reliability.
An efficient BIST should have three properties,
including less hardware overhead, higher fault coverage,
and less test application time. A BIST design consists of a
' This work is supported by the National Natural Science Foundation of China under the grant No.69733010.
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1081-7735/00 $10.00 0 2000 IEEE
test pattern generator (TPG), circuit under test (CUT), and
output response analyzer (ORA). There are two types of
TPGs: random test pattern generator and deterministic test
pattern generator. The former usually adopts a linear-
feedback shift-register (LFSR) to generate pseudo-random
test patterns. It has a regular and simple architecture that is
easy to be integrated into an IC, but it is difficult to achieve
high fault coverage and needs long test application time
due to its long test sequences. Deterministic test pattern
generator guarantees a BIST to achieve predefined fault
coverage in a short test sequences, but needs some
additional hardware to support the TPG. Its architecture
varies widely, as well as its advantages and disadvantages.
Paper [ I ] presents a scheme of insertion of test points
in a CUT to enhance its random testability, The locations
of these test points are determined according to the
principles of controllability and observability. The
disadvantage of the scheme is that it needs to access to a
circuit and requires modification of the CUT, which may
impact on performance in some cases. A weighted random
testing scheme is presented in paper [2], where an LFSR
generates test patterns with non-uniform probability
distribution of 0 and 1, so that some random pattern
resistant faults may be detected. For the sake of detecting
more such faults, multiple weights are used. However, this
method requires a considerable amount of additional
hardware to implement the scheme. In order to achieve
high fault coverage, a reseeding scheme is proposed in
paper [3]. By reseeding deliberately selected seeds, an
LFSR can generate more deterministic test patterns in its
test pattern sequence. Some hardware is thus needed to
store seeds. In scheme of bit-fixing [4], some bits of test
patterns are fixed to 0 or 1 according to the analysis of the
test set while the other bits are fill in 0 or 1 randomly.
The generated test sequence tends to contain some
deterministic test patterns, which leads a BIST to achieve
high fault coverage [5]. Unfortunately, it can not guarantee
each CUT to acquire predefined fault coverage. A counter-
decoder scheme is proposed in paper [6], where a counter
generates a series of numbers while a decoder transforms
them to test patterns that contain some deterministic test
patterns. The main disadvantage of this approach is that it
needs high hardware overhead. Paper [7] proposed a
compromised method, which combines a ROM and an
LFSR together. The LFSR provides large number of
random test patterns to test easy-to-detect faults, while the
ROM provides a small number of test vectors for hard-to-
detect faults. Paper [8] presents an LFSR-decoder scheme,
in which the decoder is constituted by simplifying those
test patterns with don’t-care bits corresponding to their
complete test set of a circuit. It can not guarantee to
achieve predefined fault coverage, although it can acquire
high fault coverage.
This paper presents an efficient BIST design using
LFSR-ROM architecture. The target fault set is determined
by an ATPG tool to achieve a predefined fault coverage.
The design includes an LFSR to generate pseudo-random
patterns first, and then takes the advantage of don’t-care
bits that remain during the process of test pattern
generation by the ATPG tool to compress the size of its
ROM (Read Only Memory). By balancing the hardware
overhead and the number of test patterns to be stored, this
scheme stores intentionally a few more test patterns in
ROM due to its efficient storage, so that the number of
pseudo-random test patterns may be reduced dramatically,
which leads to a short test application time.
The remainder of the paper is organized as follows.
The LFSR-ROM architecture is introduced in Section 2.
The compression method of ROM can be found in Section
3. The design process is described in Section 4.
Experimental results on ISCAS85 benchmarks are given in
Section 5. Finally, the conclusions appear in Section 6.
2 Architecture of The Test Pattern Generator
The TPG of the BIST design consists of an LFSR and
a ROM as shown in Figure 1 [ 7 ] . The LFSR is used to
generate large number of pseudo-random test patterns to
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detect easy-to-detect faults. The ROM is employed to
generate small number of deterministic test patterns to
detect the rest hard-to-detect faults. At first, the TPG is set
to ROM mode. The register is initiated to 100 ... 0 and is
operated as a shift-register. The 1 in the register shifts right
once a clock to index the test patterns in the ROM to be
output to the CUT. After this process, LFSR mode is
followed. The register and the feedback logic are combined
to form an LFSR, which produces pseudo-random test
patterns.
LFSR feedback logic
I
\
v
U ( OR array )
Figure 1. The Test Pattern Generator
As we know, it is difficult for pseudo-random patterns
to cover random pattern resistant faults. In many cases
one pattern generated by an ATPG tool can only detect one
of such faults. It is then not a good idea for a BIST design
to generate this kind of test patterns by an LFSR. To store
them into a ROM, however, a large amount of hardware is
needed to construct the ROM. For example, c3540, a
benchmark of ISCAS85, has 1669 gates and 50 prime
inputs. If the TPG of c3540 contains 1000 pseudo-
random test patterns and 20 deterministic test patterns, 500
( = 5 0 ~ 2 0 / 2 )gates must be used to store deterministic test
patterns on condition that each bit is equally likely to take 0
or 1. It means that about 30%(=500/1669) hardware
overhead is required for the ROM. Therefore, the key to
achieve an efficient LFSR-ROM BIST design is how to
reduce the size of its ROM. The presented scheme in this
paper makes a good use of remaining don’t-care bits during
the process of deterministic test pattern generation by an
ATPG tool, and compresses those test patterns with don’t-
care bits. The hardware overhead of ROM thus decreases
dramatically.
3 ROM Compression corresponding to logic 1’s in the merged test set need to be
connected, and thus save the hardware overhead of the
During the process of test pattern generation of an ROM. For example, the merged test set as shown in
ATPG tool, many don’t-care bits of a test pattern may Figure 2c can be stored in a ROM as shown in Figure 3.
remain, which are generally assigned with 0 or 1 randomly.
However, it is just those don’t-care bits, which can help to
reduce the size of the ROM in the TPG. Two patterns are Test patterns
consistent if and only if the corresponding bits are not 0 6 1
5 4 3 2
and 1 respectively, and then can be merged. Notice that
not only two consistent test patterns can be merged, but 0 1 1 0 1
also two outputs of the ROM can be merged if they are 1 0 o u 2
consistent. The compression of the ROM is done as 0 1 1 1 3

-
follows: 0 1 1 0 4
U 0 1 0 5
(1)Test pattern mergence
U 1 1 0 6
If some test pattern is consistent with another test
pattern, then they can be merged to one. For example, in
Figure 2a, test pattern 1 is consistent with test pattern 2,
and test pattern 6 is consistent with test pattern 4, then they
are merged to test patterns 2 and 4 respectively as shown in
Figure 2b. Figure 3. The compressed ROM for the example
(2)ROM output mergence Other optimal compaction algorithms are not taken into
If some ROM output is consistent or inversely consideration, because they contribute less compression
consistent with another ROM output, then they can be after above mergence.
merged to one ROM output. For example, in Figure 2b,
ROM outputs 1 , 4 and 6, are consistent, and ROM outputs 4 Synthesis Process
2 and 3 are inversely consistent, then they can be merged to
ROM outputs 4 and 2 respectively in Figure 2c. The synthesis process can be described as the following
123456 123456 123456 steps.
First of all, An ATPG tool is selected to find the target

2
xOxxOx>
OXlOXX
AA
oo~oox
0 00
fault set to achieve the predefined fault coverage. In this
step, the generated test set may not be important. Rather,
3 l x x x l l l x x x l l x 11 we try to find the target faults to satisfy our fault coverage
4 XXXlOX XOXlOX 0 10 requirement.
5 OlXOXO OlXOXO 1 ox In the second step, pseudo-random test patterns
fi’
6 x O x l x x generated by an LFSR are simulated to determine the
detected target faults, until 10% more consecutive test
a. Original test set b. Test pattern c. output patterns of the total do not detect any new faults. Those
compression compression
random test patterns will be generated by the LFSR in the
BIST design. The seed of the LFSR both in the TPG and
Figure 2. An example of ROM compression in the synthesis procedure must keep the same, and
(3)Utilization of don’t-care bits in ROM carefully selected.
In the ROM that are constituted by OR gates, Next, the ATPG tool generates tests for the rest faults
connected points, i.e. gates, of row lines and column lines undetected by the LFSR in the target fault set. These test
stand for logic 1 while un-connected points denote logic 0. patterns are with don’t-care bits, and then compressed as
If we set don’t-care bits to logic 0, then only those points mentioned in the last section, and stored in the ROM.

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 From the synthesis process, we can see that the
predefined fault coverage is guaranteed, and sometimes an
even higher fault coverage may be obtained. The size of
the ROM depends on how many don't-care bits available
for the compression.
5 Experimental Results
In the Experiment, we use FAN algorithm as the ATPG
tool. After a proper modification, test patterns with don't-
care bits can be generated for given faults.
The first experiment is to explore how large space
available for the possibility for test pattern compression by
using don't-care bits. The meaning of the columns in
Table 1 is as follows.
Circuits --- circuit name of ISCAS'85 Benchmark
circuits.
PIS --- number of primary inputs.
#tests --- number of tests generated by FAN algorithm.
Fault Coverage --- fault coverage of the test set without
any don't-care bits.
X bits --- percentage of don't-care bits in test patterns
before 0 or 1s are randomly assigned.
Test pattern mergence: #tests --- number of tests after
test pattern compression.
Test pattern mergence: X bits --- percentage of don't-
care bits in the test patterns after Test pattern mergence.
ROM output mergence: #outputs --- number of outputs
after ROM output compression.
ROM output mergence: X bits --- percentage of don't-
Table 1 . Results of mergences and ratio of X bits
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care bits in the test patterns after ROM output mergence.
From the table we can learn that there is a high
percentage of don't-care bits in those test patterns, and then
a large space available for test pattern mergence and ROM
output mergence. In the examples, on an average 31.27%
of test patterns, and 54.33% of ROM outputs are merged,
and 29.4% of the total bits of the ROM are don't-care bits
that are still available to assign 0 to them to reduce the
hardware overhead of the ROM.
The second experiment is to show the efficiency of the
proposed BIST design in reducing the hardware overhead.
The meaning of the columns in Table 2 is as follows.
# P.R. tests --- number of pseudo-random test patterns
generated by LFSR.
# faults to detect --- number of faults keeping
undetected by those random patterns.
# D. tests --- number of deterministic tests to detect
those undetected faults.
Overhead no comp. --- number of gates needed to
implement those deterministic tests without compression.
#Tests with X bits --- number of tests with don't-care
bits to detect those undetected faults.
ROM size --- ROM size after compression.
%X bits in ROM --- percentage of don't-care bits in the
ROM.
#gates in ROM --- number of gates needed in the ROM.
Hw reduc(times) --- (number of gates needed without
compression)/(number of gates needed in ROM of the
BIST design)
Table 2 shows a comparison of hardware overhead
 Table 2. The compari on of hardware overhead
Circuit PIS # P.R. #faults #D. Overhead #gates in Hw reduc
--

C5315
C6288
178
32
2300
54
9
16
6
7
534
112
between the ROMs that store test patterns with and without
don’t-care bits. We choose logic gate counts as the measure
+q-++-+E
16
34
9
16
I
I
3x4
9x13
23x13
5x7
9x17
I
I 5%
0%
5%
25%
0%
*- 73 I 1.5
10.1

29.6

hardware several-fold. In addition, a user-predefined fault

of hardware overhead. We assume that one OR gate
corresponds to a 1 in a ROM, and that bits of deterministic
test patterns without don’t-care bits have the same
probability to be 0 or 1. Inverters that are involved in the
process of merging test patterns are not taken into account
in the comparison, because only one or two inverters are
used in the ROMs. For example, after compression the size
of the ROM of c432 is 4x5, which means that there are 4
test patterns and 5 ROM outputs. In the ROM, 5% of the
total bits are still don’t-care bits that can be used to reduce
hardware overhead of the ROM if we take the logic 0.
Compared to the hardware overhead of the ROM that
stores deterministic test patterns, the proposed ROM design
uses only 10% of that hardware overhead on an average.
It is really a big saving.
6 Conclusions
This paper proposes an efficient BIST design using
LFSR-ROM architecture. The design takes advantage of
don’t-care bits that remain during the process of test pattern
generation by an ATPG tool. In addition to the LFSR to
generate pseudo-random test patterns, a ROM is used to
store deterministic test patterns. The sufficient utilization
of don’t-care bits is significant for compressing the size of
the ROM. Don’t-care bits are used not only for test
pattern mergence, but also ROM output mergence, which
result in a big saving of hardware overhead. An ATPG
tool is used for the BIST design to guarantee the fault
coverage not lower than a user-predefined one.
Experiments show that comparing to storing deterministic
test patterns without don’t-care bits, this scheme can save
coverage can be achieved with short test application time.
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