Contents

Assignment-1 ................................................................................................................................................ 5
Yield:.......................................................................................................................................................... 5
Observability: ............................................................................................................................................ 5
Controllability:........................................................................................................................................... 5
DPPM: ....................................................................................................................................................... 5
Coverage: .................................................................................................................................................. 5
JTAG: ......................................................................................................................................................... 6
Boundary scan:.......................................................................................................................................... 7
DFT Interview Questions ............................................................................................................................... 8
2. AU faults:............................................................................................................................................... 8
3. Improve coverage: ................................................................................................................................ 8
5. Boundary Scan test mandatory instructions:........................................................................................ 8
7. Collar logic: ............................................................................................................................................ 8
10. If memory is failing what would be possible causes of failure. What you will check first? ................ 8
11. SETUP and HOLD timing violations: .................................................................................................... 9
DFT Interview Questions ......................................................................................................................... 10
How you decide no of scan chains? ........................................................................................................ 10
How you are going to handle multi clock domain? ................................................................................ 10
Why do you need Lock up latch? ............................................................................................................ 10
What type of care taken to ICG (clock gating) during scan? ................................................................... 10
Difference between Scan Enable and Test Enable? ................................................................................ 11
Why negedge flop follow posedge flop? ................................................................................................ 11
How we are going to fix Setup & hold violations? .................................................................................. 11
What are different categories of faults?................................................................................................. 11
Differences between test coverage and fault coverage? ....................................................................... 12
What are the benefits of compressor? ................................................................................................... 12
What is compression ratio? How you are going to decide compression ratio? ..................................... 12
What is disadvantage of LOC over LOS? ................................................................................................. 13
In atpg why shift clock is slow and functional clock fast?....................................................................... 13
 16. How to handle:.................................................................................................................................. 13
Internally generated clock?................................................................................................................. 13
Synchronous set and reset? ................................................................................................................ 14
Bidirectional I/Os?............................................................................................................................... 14
Tri state buffers? ................................................................................................................................. 14
Clock gating logic? ............................................................................................................................... 14
Combinational feedback loops?.......................................................................................................... 15
Scan insertion and ATPG ............................................................................................................................. 16
Importance of Testing: ............................................................................................................................ 16
What is testability? ................................................................................................................................. 16
What is DFT? ........................................................................................................................................... 16
Fault Modeling: ....................................................................................................................................... 17
Stuck-at-fault: ......................................................................................................................................... 17
............................................................................................................................................................ 17
Transition fault: ................................................................................................................................... 17
Methods to test transition fault: .......................................................................................................... 18
Comparison between LOC and LOS: ................................................................................................... 19
Path delay fault: .................................................................................................................................. 19
Features: ............................................................................................................................................. 19
Bridging fault: ..................................................................................................................................... 19
IDDQ: ................................................................................................................................................... 20
Automatic Test Pattern Generation (ATPG): .......................................................................................... 21
Path Sensitization:................................................................................................................................... 21
Scan cell: ................................................................................................................................................. 22
Scan terminology: ............................................................................................................................... 22
Scan Cell Operation/ Scan Test: .............................................................................................................. 23
Scan Chain: .............................................................................................................................................. 23
Testing of Combinational versus Sequential Circuits:............................................................................. 25
ATPG and Testing of Combinational and Sequential circuits:................................................................. 25
A simple sequential circuit with a stuck-at-0 fault: ............................................................................ 26
Controllability and Observability of Flip-Flops:....................................................................................... 29
Scan Chain based Testing and ATPG for sequential circuits: .............................................................. 33
 Conclusion: .............................................................................................................................................. 38
BOUNDARY SCAN ........................................................................................................................................ 39
JOINT TEST ACTION GROUP (JTAG): ........................................................................................................ 39
BOUNDARY SCAN: ................................................................................................................................... 39
Boundary Scan Methods: ........................................................................................................................ 39
IEEE standards of JTAG:........................................................................................................................... 39
Boundary Scan Architecture: .................................................................................................................. 40
TAP Controller Signals: ............................................................................................................................ 41
Boundary Scan Instructions: ................................................................................................................... 41
Boundary Scan Cell: ................................................................................................................................ 42
Operation Modes: ................................................................................................................................... 43
EXTEST: .................................................................................................................................................... 44
TAP Controller: ........................................................................................................................................ 45
TAP Controller State Diagram: ................................................................................................................ 45
Bypass and Identification Registers: ....................................................................................................... 47
Instruction Register:................................................................................................................................ 48
Instruction Set: ........................................................................................................................................ 49
Benefits of Boundary Scan: ..................................................................................................................... 51
Disadvantages of Boundary Scan: ........................................................................................................... 51
MEMORY BUILT IN SELF TEST ..................................................................................................................... 52
Built In Self Test(BIST): ............................................................................................................................ 52
Basic architecture of BIST: .................................................................................................................. 52
BIST Components: ............................................................................................................................... 52
LINEAR FEEDBACK SHIFT REGISTER (LFSR): ......................................................................................... 54
Types of BIST: ...................................................................................................................................... 56
Advantages of BIST: ............................................................................................................................ 56
Disadvantages of BIST: ........................................................................................................................ 56
MEMORY BUILT IN SELF TEST (MBIST): ....................................................................................................... 57
MBIST Architecture: ................................................................................................................................ 57
Memory fault models: ............................................................................................................................ 58
MBIST Structure: ..................................................................................................................................... 62
Test Algorithms: ...................................................................................................................................... 62
 March Tests:............................................................................................................................................ 64
Other March Algorithms: ........................................................................................................................ 65
Advantages of MBIST .............................................................................................................................. 65
Disadvantages of MBIST.......................................................................................................................... 65
DUAL PORT MEMORY ................................................................................................................................. 66
BIST Controller: ....................................................................................................................................... 67
Address Generator: ................................................................................................................................. 68
Data Generator: ...................................................................................................................................... 69
Dual-port Controller:............................................................................................................................... 69
Data Comparator: ................................................................................................................................... 69
OPCG ........................................................................................................................................................... 70
Scan chain loading and unloading............................................................................................................... 72
Scan Testing: ........................................................................................................................................... 73
Load-Unload procedure: ......................................................................................................................... 73
Capture procedure: ................................................................................................................................. 74
ASSIGNMENT-2 ........................................................................................................................................... 75
Difference between serial simulation and parallel simulation? ............................................................. 75
Logic present in de-compressor and compactor? .................................................................................. 77
Dead cycle: .............................................................................................................................................. 79
Test points:.............................................................................................................................................. 79
Clock gating: ............................................................................................................................................ 79
Assignment-1

Yield:

It is the ratio of good chips over all chips fabricated in a single substrate or area.
(or)
Fraction of good chips produced in a manufacturing process.

Observability:
Ease of observing a node by watching external output pins of the chip.

Controllability:
Ease of forcing a node to 0 or 1 by driving input pins of the chip.

DPPM:

Effectiveness of manufacturing tests can be described with a metric known as defective

level (DL).
DL is a measure of product quality. It denotes the fraction of faulty chips escaping to the
customer among the chips that pass all manufacturing tests, and is often measured as
DPPM (Defective Parts Per Million).
The lower the DPPM, the higher the quality of products shipped to the customers.

Coverage:

It refers to the percentage of some type of fault that can be detected during the test of any
system. Coverage is of two types. They are
 Fault coverage
 Test coverage
 Fault coverage: It is defined as the ratio of number of detectable faults to the total
number of faults.

Fault Coverage = (DT+(NP+AP)*PT_credit)/total faults.

DT-Detected

PT- Possibility detected

AP-ATPG untestable possibly detected.

NP-not analyzed, possibly detected.

Test coverage: It is defined as the ratio of number of detected faults to the total number
of detectable faults.

Test Coverage = DT+(NP+AP)*PT_credit)/(total faults-UD-(AN*AU_credit).

DT-Detected

PT-Possibility detected

AP-ATPG untestable possibly detected.

NP-not analyzed, possibly detected.

UD-Undetectable

AU-ATPG untestable

AN-ATPG untestable not detected.

JTAG:

JTAG is an industry standard for verifying designs and testing PCB after manufacture.
The term JTAG refers to the interface or test access port used for communication. It
includes TCK, TDI, TDO, TMS, TRST connections. For some applications this interface
may be used to interrogate or communicate with internal instruments within the core of
the chip.
Boundary scan:

It is an integrated method for testing interconnections (wire lines) on PCB or sub blocks
inside an integrated circuit that are implemented at IC level.
It is also widely used as a debugging method to watch integrated circuit pin states,
measure voltage or analyze sub blocks inside an integrated circuit.
DFT Interview Questions

2. AU faults:

Some faults are testable, meaning that a defect at these fault sites would result in a functional
failure. Unfortunately ATPG tools cannot produce patterns to detect all of the testable faults.
These testable but undetected faults are called AU faults.

Pin constraints, Black box models, RAM, Cell constraints, ATPG constraints, Faults/Multicycle
paths, False paths.

3. Improve coverage:

Use as many boundary scan devices as possible.

Use buffers, data transceivers and other glue logic with boundary scan capability (TIABT,BCT
families).
Improving the test coverage with at speed tests.
Test point insertion for test coverage improvement.

5. Boundary Scan test mandatory instructions:

Extest opcode-10000
Preload/Sample opcode- 10010,
Bypass opcode-11111

7. Collar logic:

In memory collar it usually consists of a wrapper around memory and is used to select between
functional inputs and test inputs based upon MBIST functional mode selection bit. Collar logic
consists of a multiplexer within it.It interfaces the memory with onchip logic and MBIST
controller.

10. If memory is failing what would be possible causes of failure. What you will
check first?

Improper address of selection will cause the memory failure. Fail Map extraction is required to
output all the relevant data necessary to determine why a failure occured with in the memory.
In order to diagnose failures in the memory implementation the BIST logic must take the timing
latency.
For MBIST the traditional approach is to use a failed bitmap, but this is limited to topological
signature analysis.
Yield problem associated to MBIST failures at high operating temperature.

11. SETUP and HOLD timing violations:

Setup time : It is defined as the minimum amount of time before the clocks active edge by which
the data must be stable for it to be latched correctly. Any violations in this required time causes
incorrect data to be captured and is known as set up violation.

Hold time : It is defined as the minimum amount of time after the clocks active edge by which
the data must be stable. Any violation in this required time cause incorrect data to be latched and
is known as hold violation.
 DFT Interview Questions

How you decide no of scan chains?

 Number of package pins available for scan I/O.

 Size of the design
 EDA tools available for use (w/ or w/o compression)
 The targeted ATE (available pin count and vector memory)

How you are going to handle multi clock domain?

In that case do we create scan chain for each clock domain. Also, is the scan clock
different from normal clock used during normal functionality are there issues in scan
testing when the clock is generated internally (say using PLL) we need to create seperate
scan chains for each clock domain same clocks can be used as scan clocks as this will
reduce extra pins. After going through some theory on DFT, I found the following
answers:
1) the functional clock is bypassed for scan testing. So clocks in multiple domains can be
clubbed into a single chain with a single clock if DC testing is the only target

2) About the pll also, the answer is same since the internal clock is bypassed and scan
clock is used, the pll remains inactive during scan testing.

Why do you need Lock up latch?

Lock up latches are necessary to avoid skew problems during shift phase of scan based
testing.
Lock up latch is an important element in scan based designs, especially for hold timing
closure of shift modes.

What type of care taken to ICG (clock gating) during scan?

ICG- Integrated Clock Gating which is used for removing the glitches. Negative clock
must be given to the flop then only the glitches are eliminated.
Difference between Scan Enable and Test Enable?
Scan Enable:
Scan enable is mostly used in scan flip flops to shift the data from input to
output based on functional mode and test mode.

Test Enable:
Test enable is mostly used in BIST circuitry. It performs the operation on both
functional mode and test mode to capture the data and send the data.

Why negedge flop follow posedge flop?

At the intersection of positive and negative flop the data will not be captured. Since at
single pulse data launch and capture is not possible. We will require lock up latch. The rule is
that there should not be 2 shifts during one clock period. So if you put +ve edge flop followed by
-ve edge flop, there is a chance of 2 shift (if the clock skew between 2 clocks is small) in one
clock period. But if you put -ve edge flop then +ve edge flop, then there is no chance of that
because the +ve edge come in the next period. Or if ur design needs that +ve edge then -ve edge
then you a lock up latch (if skew is small) this depends on the nature of clock involved in your
scan design.

How we are going to fix Setup & hold violations?

To fix setup violations:
1. Upsizing
2. Swapping from HVT to LVT
3. Push capture path
4. Pulling launch clock.

To fix Hold Violations:

1. Adding delay / buffer [as buffer offers lesser delay, we go for special Delay cells
whose functionality Y=A, but with more delay]
2. Add lockup-latches [in cases where the hold time requirement is very huge, basically
to avoid data slip].

What are different categories of faults?

DT- Detected
DS- Detected by simulation
DI- Detected by implication
 DR- Robustly detected delay fault
UD- Undetectable
UU- Undetectable Unusuable
UT- Undetectable tied
UR- Undetectable redundant
UB- Undetectable blocked
PT- Possibly Detected
AP- ATPG Untestable, Possibly Detected
NP- Not Analyzed, Possibly Detected
AU- ATPG Untestable
AN- ATPG Untestable, Not Detected
ND- Not Detected
NC- Not Controlled
NO- Not Observed

Differences between test coverage and fault coverage?

Test coverage:
It is defined as that the percentage of detected faults for all detectable faults

T.C = DT+(NP+AP)*PT_Credit/Total faults-UD-(AN*AU_Credit)

Fault Coverage:
It is defined as that the total number of detected faults (during testing) divided by the
total number of faults in the design.

F.C = DT+(NP+AP)*PT_Credit/Total faults

What are the benefits of compressor?

1. Reduces test costs
2. Reduces test time
3. Improves the coverage

What is compression ratio? How you are going to decide compression

ratio?
Compression ratio in DFT is basically used for TAT(TEST APPLICATION TIME)
and TDV(TEST DATA VOLUME).
 It is the reduction in these two numbers when compared to a design which has just
the scan chains and no compression techniques.
TAT and TDV is achieved by lesser number of cycles needed to load the internal
chains.

External chain = Internal chains*compression ratio*beta

What is disadvantage of LOC over LOS?

LOC LOS
1.Medium fault coverage Requires fast scan enable signals
2.More test patterns
3.sequential ATPG

In atpg why shift clock is slow and functional clock fast?

In functional mode different paths are varying combinational logic between any two
registers.
In shift mode, there is absolutely no logic at all. Hence all flops tends to switch at the
same time. Therefore the peak power is very high because it is directly proportional to
switching frequency.

16. How to handle:

Internally generated clock?

For the shift mode, the internally generated clocks need to drive the scan cells. Since this flow
uses an inserted OCC controller, the internally generated scan clock drives the OCC controller
input pin. Then, one clock pulse after capture is consumed inside the OCC controller, the output
of the OCC controller drives the scan cells.
Synchronous set and reset?
Synchronous set and reset are able to handle scan or capture violations. By using
mux the set and reset will give high coverage.

Bidirectional I/Os?
First fix bidirectional ports of the design to ensure that direction of bidirectional
ports are fixed to either input or output by controlling the enable signal of
bidirectional ports. If the enable signal is generated internally proper DFT logic
has to be employed or else if the controlling signal is a primary port provide
proper logic value on the bidirectional controlling port during the test to make
the bidirectional ports unidirectional.

Tri state buffers?

Tri state buffers can be handled by adding a bus keeper.
This bus keeper provides better than 90% coverage on tri state bus networks, but
sequential ATPG is required, which can slow down test program generation.
A sequential logic primitive called a bus keeper or holder.

Clock gating logic?

Clock gating may be essential for low power design, but it impacts on design
testability. A flip-flop whose clock pin is held constant during scan is
noncompliant. A scan-compliant flip-flop is one that functions correctly during
 scan-shift without risk. Checking compliance is important, since ATPG
algorithms assume working scan chains. Noncompliant flip-flops are excluded
from all scan chains, and may impact coverage.

Combinational feedback loops?

Combinational feedback loops may introduce internal logic states to a design that
scan storage elements cannot control. If you cannot avoid the feedback loops
then you should break the feedback loop by inserting an additional flip flop that
may present in the feedback path only during scan test mode.
If flip flop is not inserted then insert a mux in the feedback path drives a constant
value during scan test mode.
 Scan insertion and ATPG

Importance of Testing:
 According to Moore’s law feature size is decreasing.

 Defects are unavoidable.

 Testing is required to guarantee fault-free chips.

 Product quality depends on the following parameters,

 Test cost

 Test quality

 Test time

What is testability?
 The ability to put a design into a known initial state, and then control and observe internal
signal values.

 Circuit with DFFs: Low testability.

 Two basic properties determine the testability of a node:

 Controllability:

The ability to set node to a specific value.

 Observability:

The ability to observe a node’s value.

What is DFT?
 DFT is adding logic to enhance the testability of a design, DFT increases ability to
measure the quality.

 It is a method of testing each and every node in the design for structural and other faults.

 Higher the no. of nodes which can be tested through the targeted no. of patterns greater is
the test coverage of the design.
Fault Modeling:
Due to defect during manufacturing of integrated circuit, There is need to model the possible
faults that might occur during fabrication process, This is called Fault Modeling.

Generally there are two types of faults

1. Stuck-at-fault

2. Transition fault

3. Bridging fault

4. Path delay fault

5. IDDQ

Stuck-at-fault:
In this model, faults are fixed (0 or 1) value to a net which is an input or an output of a
logic gate or a flip-flop in the circuit. If the net is stuck to 0, it is called stuck-at-0 (s-a-0)
fault and if the net is stuck to 1, it is called stuck-at-1 (s-a-1) fault. If it is assumed that only
one net of the circuit can have a fault at a time, it is called single stuck-at fault model.
Without this assumption, it is called multiple stuck-at fault model.

This has been observed though fabrication and testing history, that if a chip is verified
to be free of single stuck-at faults, then it can be stated with more than 99.9% accuracy that
there is no defect in the silicon or the chip is functionally (logical) normal. Further, single-
stuck at fault is extremely simple to handle in terms of DFT required, test time etc.; this will
be detailed in consequent lectures. So single stuck-at fault model is the most widely accepted
model.

Transition fault:
The faults caused by the rise and fall times are called transition delay faults. Due to this
finite time it takes for an input of a gate to show up on the output, faults may arise if the
signals are not given the time to settle. There are two types of transition faults
  slow-to-rise (stuck-at-0)

 slow-to-fall (stuck-at-1)

Methods to test transition fault:

Delay tests require a vector pair to detect a fault. Since the patterns must be applied at the
rated speed, at-speed testing is needed. Several different methods are used to apply the vectors
at-speed. Transition faults are detected through scan chain. There are two methods to detect
transition faults.

 Skew Load or Launch-On-Capture (LOC).

 Skew Load or Launch-On-Shift (LOS).

In the case of LOS the transition is launched at the last shift, and is captured at-speed in the
capture mode. If you are using muxed scan, scan enable signal, which determines the
shift/capture mode, should have the transition with in the short period of functional frequency.

When it comes to LOC, the transition at the fault sites will be launched in the capture period and
the launch vector is derived from combinational logic or PIs (unlike in LOS where they are
loaded on last shift). Hence here the controllability on fault sites is less when compared to that of
LOS, and hence the ATPG run time increases and there might be slight reduction in coverage.
Also there will be minimum of two pulses with extra dead cycles in the capture mode, hence the
tester time also increases substantially.
Comparison between LOC and LOS:
LOC LOS

Advantage Advantage

 High fault coverage, few test patterns  No requirement for fast scan enable
signals

Disadvantage
Disadvantage
 Medium fault coverage, more test
 Requires fast scan enable signals patterns, sequential ATPG

Path delay fault:

A path is a sequence of connected gates from a circuit primary input to a primary output. A
path delay fault is said to have occurred if the delay of a path is more than the specified clock
period of the circuit.

Features:
 Much more complex than transition delay model

 Low fault coverage

Bridging fault:
A bridging fault represents a short between a group of nets. In the most widely accepted
bridging fault models, short is assumed between two nets in the circuit. The logic value of the
shorted net may be modeled as 1-dominant (OR bridge), 0-dominant (AND) bridge. It has been
observed that if a circuit is verified to be free of s-a-faults, then with high probability it can be
stated that there is no bridging fault also.
  A bridging fault occurs when two leads in a logic network are connected accidentally and
“wired logic” is performed at the connection.

 Bridging faults inside an integrated circuit chip may arise if:

 The insulation between adjacent layers of metallization inside the chip breaks down

 Two conductors in the same layer are shorted due to improper masking or etching

 Types of bridging faults Bridging faults may be classified into two types:

1. Input bridging

2. Feedback bridging

IDDQ:
IDDQ testing is based on the principle that CMOS does not draw any current from the power
supply when its inputs are static(i.e. not switching)In reality there exists a small leakage current
which typically which is smaller than the switching current. Faults detected by IDDQ tests:

 Resistive shorts

 Line and gate break faults

 Latch up

 Source or drain break faults

Automatic Test Pattern Generation (ATPG):
ATPG enables testers to distinguish between the correct circuit behavior and fault circuit
behavior based on input patterns. The generated patterns are used to test semiconductor devices
for defects after manufacturing. The effectiveness of ATPG gives an estimate of test quality.

There are two steps that ATPG should take to detect a fault

 Fault Activation: Establishes a signal value at the fault model site i.e. opposite of the
value produced by the fault model.

 Fault propagation: Moves the resulting signal value, or fault effect, forward by
sensitizing a path from the fault site to a primary output.

Path Sensitization:
ATPG by path sensitization method is generally applied for “difficult to test faults” and
comprises three phases.

 Fault sensitization

 Fault propagation

 Line justification
Scan cell:
To check the connectivity between different flops in the design we need Scan Input(SI) in
addition to functional input. Both scan and normal inputs depends on the value of Scan Enable
(SE), flip state will change. So flops like above will be grouped to form chain which is called as
scan chain.

The flops in the design have to be modified in order to be put in the scan chains. To do so, the
normal input (D) of the flip-flop has to be multiplexed with the scan input. A signal called scan-
enable is used to control which input will propagate to the output.

If scan-enable = 0, data at D pin of the flop will propagate to Q at the next active edge
If scan-enable= 1, data present at scan-in input will propagate to Q at the next active edge

Scan terminology:

It will be useful to know some signals used in scan chains which are as follows:
 Scan-in: Input to the flop/scan-chain that is used to provide scan data into it
 Scan-out: Output from flop/scan-chain that provides the scanned data to the next
flop/output
 Scan-enable: Input to the flop that controls whether scan_in data or functional data will
propagate to output
Scan Cell Operation/ Scan Test:
The scan cell provides observability and controllability of the signal path by conducting the
four transfer functions of a scan element.

 Functional operation

 Scan sample

 Scan load/shift

 Scan data apply

Scan Chain:
These scan chains are made externally accessible by connecting the scan input of the first
scan cell in a scan chain to a primary input and the output of the last scan cell in a Scan chain to
a primary output. Scan design is currently the most popular structured DFT approach. It is
implemented by connecting selected storage elements present in the design into multiple shift
registers, called Scan chains.

Scan chains are the elements in scan-based designs that are used to shift-in and shift-out
test data. A scan chain is formed by a number of flops connected back to back in a chain with the
output of one flop connected to another. The input of first flop is connected to the input pin of
the chip (called scan-in) from where scan data is fed. The output of the last flop is connected to
the output pin of the chip (called scan-out) which is used to take the shifted data out. The figure
below shows a scan chain.
Purpose of scan chains:

Scan chains are inserted into designs to shift the test data into the chip and out of the chip.
This is done in order to make every point in the chip controllable and observable as discussed
below.

Purpose of testing using scan:

Scan testing is carried out for various reasons, two most prominent of them are:
 To test stuck-at faults in manufactured devices
 To test the paths in the manufactured devices for delay; i.e. to test whether each path is
working at functional frequency or not

How a scan chain functions:

The fundamental goal of scan chains is to make each node in the circuit controllable and
observable through limited number of patterns by providing a bypass path to each flip-flop.
Basically, it follows these steps:
 Assert scan enable (make it high) so as to enable (SI -> Q) path for each flop
 Keep shifting in the scan data until the intended values at intended nodes are reached
 De-assert scan enable (for one pulse of clock in case of stuck-at testing and two or more cycles
in case of transition testing) to enable D->Q path so that the combinational cloud output can be
captured at the next clock edge.
 Again assert scan enable and shift out the data through scan out
How Chain length is decided:

By chain length, we mean the number of flip-flops in a single scan chain. Larger the chain
length, more the number of cycles required to shift the data in and out. However, considering the
number of flops remains same, smaller chain length means more number of input/output ports is
needed as scan in and scan out ports. As

Number of ports required = 2 X Number of scan chains

Since for each scan chain, scan in and scan out port is needed. Also,

Number of cycles required to run a pattern = Length of largest scan chain in

design

Suppose, there are 10000 flops in the design and there are 6 ports available as input/output.
This means we can make (6/2=) 3 chains. If we make scan chains of 9000, 100 and 900 flops, it
will be inefficient as 9000 cycles will be required to shift the data in and out. We need to
distribute flops in scan chains almost equally. If we make chain lengths as 3300, 3400 and 3300,
the number of cycles required is 3400.

Keeping almost equal number of flops in each scan chain is referred to as chain balancing.

Testing of Combinational versus Sequential Circuits:

Due to different state inside flip-flops, it is difficult to employ the same methods as with
combinational logic. Alternative approach: Design for test

Scan Path technique: FF inputs pass through multiplexer stages to allow them to be used in
normal mode as well as a special test shift register mode.

ATPG and Testing of Combinational and Sequential circuits:

Basic architecture of a sequential circuit:

Once indirect controllability and observability are achieved, ATPG for these combinational
blocks can be done using D-algorithm or any other combinational APTG algorithm. In the figure
it may be noted that there are three blocks, namely NSF, OFB and state flip-flop. The first two
blocks are combinational circuits and the state flip-flop has sequential elements. So ATPG
procedure for the NSF and OFB blocks should be similar to the ones already introduced in the
previous lectures. However, it may be noted that compared to a standard combinational circuit,
in case of NSF some inputs (state feedback) are not controllable and its outputs are not
observable.

Similarly, in case of the OFB, some of its inputs are non-controllable. When a circuit powers
up, the flip-flops can have any value (0 or 1). So for ATPG of the combinational blocks in
sequential circuits, we need to control (indirectly) the values in the nets which are outputs of flip-
flops and observe (indirectly) the nets which are inputs to the flip-flops. Once indirect
controllability and observability are achieved, ATPG for these combinational blocks (in
sequential circuits) can be done using D-algorithm (or any other combinational APTG
algorithm).

A simple sequential circuit with a stuck-at-0 fault:

S-a-0 fault at net a:

Gate-1 corresponds to the OFB

Gate-2 is for the NSF

D-flip flop is the memory element.

 Flip-flop can have any signal value (marked as X). So testing the s-a-0 fault is not as simple
as in case of combinational circuits. To test the s-a-0 fault, simply, a=1 and f =0, which results in
D being propagated to the primary output. It may be noted that net f (secondary input) is driven
by the output of the state flip-flop. As net f is not directly controllable, we cannot make it 0 and
test the fault. As discussed, after power up, the flip-flop can have any signal value (marked as
X). So testing the s-a-0 fault is not as simple as in case of combinational circuits.

Indirect controlling of f to 0

For ATPG of the fault, we need to indirectly control the net f to 0. Following that, we can apply
the test pattern as a =1 and b =X, which propagates D to the primary output. From the circuit it
may be noted that to make f to 0, we first need to make net d=0, which is the input to the flip-
flop; following that a clock edge can transfer the value of d to f (in the next state). The process of
making f =0 in a indirect manner (by state change)
 Test pattern for the s-a-0 fault

After net f is made 0, then a =1 and b =X would propagate the fault effect (D) to the primary
output

ATPG for s-a-1 fault in the NSF block

It may be noted that ATPG for combinational blocks in sequential circuits require more than
one pattern. In this example, the first pattern is a =X, b =0 and clock edge followed by a =1
and b =X. In such cases, final pattern is according to combinational ATPG (that sensitize the
fault and propagates the effect to a primary output) and all other initial patterns are to bring the
secondary inputs to their required value.

ATPG for a fault in the NSF block is more complex than the ones in the OFB. In case of a
fault in the NSF we need to indirectly control the secondary inputs and in addition, propagate the
fault effect to the primary output via OFB. This is illustrated using a s-a-1 fault at net c in the
circuit. First, primary input b =0 ( a =X) and a clock edge is applied; this makes e =0 (and
also c =0) after the edge. It may be noted that even in presence of the s-a-1 fault, b =0 and a
clock edge makes c =0; this sensitizes the fault ( D at c ). In the next step, b =1 ( a =X) and a
clock edge would propagate the fault effect ( D ) to the output of the flip-flop (i.e, secondary
input of the OFB). Finally, a =0 ( b =X) would propagate fault effect to the primary output.

Controllability and Observability of Flip-Flops:

Set and reset lines:

One of the simplest ways to directly control flip-flops is through set-reset lines. Set-reset
lines can directly make the output of a flip-flop to be 1/0 without any input and clock pulse. One
of the simplest way to directly control flip-flops is through set-reset lines. Set-reset lines can
directly make the output of a flip-flop to be 1/0 without any input and clock pulse. A D flip-flop
with set-reset lines is shown in Figure

Fig: D-Flip-flop with set and reset

 Testing using set/reset flip-flops for a cyclic circuit

The circuit with a s-a-1 fault in the primary input line is shown in Figure 2 (a). Also, the
flip-flop has set/reset lines. By D-algorithm, a test pattern would be: primary input =0, secondary
input (other input of XOR gate) =0 and fault effect at primary output = D. So in Step-1, set =1
and reset =0 (and and primary input =X); this makes output of flip-flop (i.e., secondary input) to
be 1. In Step-2, set =0, reset =0 and primary input =0; this sensitizes fault location as D and its
effect propagates to the input of the flip-flop as D. Also a positive clock pulse is applied which
transfers D to output of the flip-flop (primary output). These two steps complete ATPG (and
testing) of the fault.

Input output block diagram of the circuit

It may be noted that it has 9 I/O pins (3 primary inputs + 1 primary output +2 x nffs set-reset
lines, where nffs is the number of flip-flops and a clock). The largest number of I/O pins
supported in most complicated packages is about 1024. So, for a circuit with thousands of flip-
flops, this approach requires a package of thousands of I/O pins (for the 2 x nffs factor) with
makes it impractical.
 Set and reset by shift register

we saw that flip-flops with set/reset capability can ease the testing and ATPG problem for
sequential circuits. However, the main problem is the huge number of I/O lines that gets added to
the chip. To avoid this issue of high I/Os, another technique called “set and reset by shift
register” is used which uses a shift register and loads itself with the pattern required for setting
the flip-flops. Now the set and reset lines of the flip-flops of the circuit (under test) are connected
with the outputs of the flip-flops of the shift resister. The shift register has an input line and a
separate clock (for shifting data) and an output line. So in this case only three extra I/O lines are
required. ATPG and testing for the circuit shown in figure, using shift register.

As there are two flip-flops in the circuit under test, there are four flip-flops in the shift
register. Now, set and reset lines of F1 (flip-flop) of the circuit under test are connected to output
of SR1 and SR2 (flip-flops of register), respectively. Similarly, set and reset lines of F2 are
connected to output of SR3 and SR4, respectively. As already discussed, testing the fault (s-a-0
at j) requires the two flip-flops of the circuit to be set to 1. So the pattern
is set (F1)=1, reset (F1)=0, set (F2)=1 and reset (F2)=0, which when mapped to the flip-flops of
the shit register is SR1=1,SR2=0,SR3=1 and SR4=0. The pattern 1010 can be inserted in the
shift register using four clock edges of S clock . Once the shift register is loaded, the flip-flops F1
and F2 are set; this is shown in Figure. Now, another pattern 0000 is inserted in the shift register
using four clock edges of S clock; this makes the circuit under test ready to be operational.
Following that input pattern a =1, b =1, c =X is applied to sensitize and propagate effect of the
fault to primary output; this is shown in Figure. The block diagram of the circuit (under test) with
shift register is shown in Figure 6. So in addition to original I/Os, three new I/Os get added
namely: (i) S clock , (ii) test in and (iii) test out .

Scan Chain based Testing and ATPG for sequential circuits:

In the last section we saw that shift register based testing of sequential circuits solved the
problem of a large number of I/Os. However, the major drawback of the scheme is due to the
huge area overhead; twice the number of flip-flops in the circuit under test is required in the shift
register. The concept of Scan chin is motivated from the idea of shift register based testing,
however, alleviates the problem of area overhead. The basic idea in scan chain is to convert the
flip-flops in the circuit under test itself to a shift register, rather than using a separate one. To
elaborate, the circuit under test has two modes: (i) test (or scan chain) and (ii) working (or
normal). In test mode the flip-flops are decoupled from the circuit and they are connected in
form of a shift register (called scan chain). The input of the first flip-flop in the scan chain is
taken out as a special input test pin called “Scan in” and the output of the last flip-flop in the scan
chain is taken out as a special output test pin called “Scan out”. Now all the flip-flops are set as
required by shifting bit values in the scan chain. Once the flip-flops are set they are removed
from the scan chain and connected back to the circuit. So another advantage of scan chain based
testing over shift register based testing is due to non requirement of set/reset lines. The basic
concept of scan chain is shown in Figure. It shows the state flip-flops with scan chain in a
sequential circuit; other blocks are not shown for clarity. As discussed, flip-flops with scan-chain
take inputs from two parts of the circuit (i) next state function block (when operating normally)
and (ii) from the previous flip-flop in the chain (when in test mode); the first flip-flop in the scan
chain takes input from a primary input “Scan in”. So in state flip-flop block with scan chain, all
the flip-flops must have a 2X1 multiplexer. One input is from the next state function block and
the other is from the previous flip-flop in the chain. The control input called mode basically
decides the mode of operation; 1 for scan-chain and 0 for normal operation. Figure shows this
concept for a circuit with three flip-flops. It shows a flip-flop used in scan chain called scan flip-
flop and shows the block diagram representation of scan flip-flop. It shows the flip-flops in scan
chain mode and shows the flip-flops in normal mode. Figure shows the basic block diagram of a
sequential circuit with scan chain in both normal and test mode.

Flip Flops in scan chain mode

Flip Flops in normal mode
Sequential circuit with scan chain: normal and test mode
 ATPG and testing of a sequential circuit with scan chain

The circuit with the flip-flops having scan chain compatibility is shown in figure. As
discussed about the circuit to test the s-a-0 fault at net j, the signal values at nets d and i are to be
1. So both the flip-flops are to be set to 1; this was achieved by making the set input as 1 and
reset input as 0 in case of testing using set/reset flip-flops. In case of scan chain, to set the flip-
flops, in the first step mode (M) is made 1. Making M=1, removes the next state function block
from the circuit and the flip-flops are connected in a chain; this is shown by dotted lines in
Figure. Two 1s are applied in the Scan in input at two clock pulses which makes d =1 and i =1.
Now, the circuit is brought in normal mode by making M=0. In this stage testing is performed by
making a =1, b =1, c =X which propagates the fault effect to the output.

In the last example we saw how scan chain can be used to set the flip-flops to desired value for
testing. However, D-algorithm is required on the entire circuit (after removing flip-flops) to find
the test pattern. Now we will see another advantage of scan chain, which eliminates the need for
performing ATPG on the whole circuit. One needs to consider input of the nearest flip-flop from
the fault site as an output line and perform ATPG on the sub-circuit lying in the cone of
influence of the output line (i.e., input of the nearest flip-flop).

Conclusion:
Scan chain has overcome all the problems regarding the previous methods. But the only
disadvantage is that if there is n no. of flip flops then we require n clock pulses to shift the data
for set or reset the flip flops.
 BOUNDARY SCAN

JOINT TEST ACTION GROUP (JTAG):

JTAG is an industry standard for verifying designs and testing PCB after manufacture. The
term JTAG refers to the interface or test access port used for communication. It includes TCK,
TDI, TDO, TMS, TRST connections. For some applications this interface may be used to
interrogate or communicate with internal instruments within the core of the chip.

BOUNDARY SCAN:
It is an integrated method for testing interconnections (wire lines) on PCB or sub blocks
inside an integrated circuit that are implemented at IC level.

It is also widely used as a debugging method to watch integrated circuit pin states, measure
voltage or analyze sub blocks inside an integrated circuit.

Boundary Scan Methods:

For testing interconnects –PCBs used as a debugging method to watch integrated circuit
pin states, measure voltage, or analyze sub-blocks inside an integrated circuit. Boundary scan is a
family of test methodologies aiming at resolving many test problems.

 From chip level to system level,

 Logic cores to interconnects between cores
 Digital circuits to analog or mixed-mode circuits.

IEEE standards of JTAG:

Boundary Scan Architecture:
The boundary-scan test architecture provides a means to test interconnects between integrated
circuits on a board without using physical test probes. It adds a boundary-scan cell that includes
a multiplexer and latches, to each pin on the device. Figure illustrates the main elements of a
universal boundary-scan device. The Figure shows the following elements:

• Test Access Port (TAP) with a set of four dedicated test pins: Test Data In (TDI), Test
Mode Select (TMS), Test Clock (TCK), Test Data Out (TDO) and one optional test pin Test
Reset (TRST*).

• A boundary-scan cell on each device primary input and primary output pin, connected
internally to form a serial boundary-scan register (Boundary Scan).

• A TAP controller with inputs TCK, TMS, and TRST*.

• An n-bit (n >= 2) instruction register holding the current instruction.

• A 1-bit Bypass registers (Bypass).

• An optional 32-bit Identification register capable of being loaded with a permanent device
identification code.

The test access ports (TAP), which define the bus protocol of boundary scan, are the
additional I/O pins needed for each chip employing Std.1149.1a. The TAP controller is a 16-state
 final state machine that controls each step of the operations of boundary scan. Each instruction to
be carried out by the boundary scan architecture is stored in the Instruction Register. The various
control signals associated with the instruction are then provided by a decoder. Several Test Data
Registers are used to stored test data or some system related information such as the chip ID,
company name, etc.

TAP Controller Signals:

Test Clock Input (TCK) -- Clock for test logic

Can run at different rate from system clock

Test Mode Select (TMS) -- Switches system from functional to test mode

Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one
of many test instructions

Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or
device ID or other internal registers)

Test Reset (TRST) -- Optional asynchronous TAP controller reset

Boundary Scan Instructions:

The IEEE 1149.1 standard defines a set of instructions that must be available for a device to
be considered compliant. These instructions are:

 BYPASS – this instruction causes the TDI and TDO lines to be connected via a single-bit
pass-through register (the BYPASS register). This instruction allows the testing of other
devices in the JTAG chain without any unnecessary overhead.
 EXTEST – this instruction causes the TDI and TDO to be connected to the Boundary Scan
Register (BSR). The device’s pin states are sampled with the ‘capture dr’ JTAG state and new
values are shifted into the BSR with the ‘shift dr’ state; these values are then ap plied to the
pins of the device using the ‘update dr’ state.
 SAMPLE/PRELOAD – this instruction causes the TDI and TDO to be connected to the
BSR. However, the device is left in its normal functional mode. During this instruction, the
BSR can be accessed by a data scan operation to take a sample of the functional data entering
and leaving the device. The instruction is also used to preload test data into the BSR prior to
loading an EXTEST instruction.
Other commonly available instructions include:

 IDCODE – this instruction causes the TDI and TDO to be connected to the IDCODE register.
 INTEST – this instruction causes the TDI and TDO lines to be connected to the Boundary
Scan Register (BSR). While the EXTEST instruction allows the user to set and read pin sta tes,
the INTEST instruction relates to the core-logic signals of a device.

Boundary Scan Cell:

The IEEE Std. 1149.1a specifies the design of four test data registers as shown in Figure.
Two mandatory test data registers, the bypass and the boundary-scan resisters, must be included
in any boundary scan architecture. The boundary scan register, though may be a little confusing
by its name, refers to the collection of the boundary scan cells. The other registers, such as the
device identification register and the design-specific test data registers, can be added optionally.

The cell has four modes of operation: normal, update, capture, and serial shift. The memory
elements are two D type flip-flops with front-end and back-end multiplexing of data. It is
important to note that the circuit shown in Figure is only an example of how the requirement
defined in the Standard could be realized. The IEEE 1149.1 Standard does not mandate the
design of the circuit, only its functional specification. The four modes of operation are as
follows:

1) During normal mode also called serial mode, Data In is passed straight through to Data Out.

2) During update mode, the content of the Update Hold cell is passed through to Data Out.
Signal values already present in the output scan cells to be passed out through the device output
pins. Signal values already present in the input scan cells will be passed into the internal logic.

3) During capture mode, the Data In signal is routed to the input Capture Scan cell and the
value is captured by the next Clock DR. Clock DR is a derivative of TCK. Signal values on
device input pins to be loaded into input cells, and signal values passing from the internal logic
to device output pins to be loaded into output cells

4) During shift mode, the Scan Out of one Capture Scan cell is passed to the Scan In of the next
Capture Scan cell via a hard-wired path. The Test Clock, TCK, is fed in via yet another dedicated
device input pin and the various modes of operation are controlled by a dedicated Test Mode
Select (TMS) serial control signal.

Note that both capture and shift operations do not interfere with the normal passing of data
from the parallel-in terminal to the parallel-out terminal. This allows on the fly capture of
operational values and the shifting out of these values for inspection without interference. This
application of the boundary-scan register has tremendous potential for real-time monitoring of
the operational status of a system — a sort of electronic camera taking snapshots — and is one
reason why TCK is kept separate from any system clocks.
Operation Modes:
S.No Mode Description

1 Normal Mode=0
IN=OUT

2 Scan Shift DR=1 clock DR,

TDI …….SINSOUT….TDO

3 capture Shift DR=0, clock DR,

INQA output driven by IN or QB

4 Update Mode=1,update DR
QAout.
EXTEST:
It tests the interconnection between the chips.

Test the internal logic of the chip

TAP Controller:

The operation of the test interface is controlled by the Test Access Port (TAP) controller. This is
a 16-state finite state-machine whose state transitions are controller by the TMS signal.

TAP Controller State Diagram:

A transition between the states only occurs on the rising edge of TCK, and each state has a
different name.

The two vertical columns with seven states each represent the Instruction Path and the Data Path.

The data registers operate in the states whose names end with "DR" and the instruction register
operates in the states whose names end in "IR". The states are otherwise identical.

The operation of each state is described below.

Test-Logic-Reset

All test logic is disabled in this controller state enabling the normal operation of the IC. The TAP
controller state machine is designed so that, no matter what the initial state of the controller is,
the Test-Logic-Reset state can be entered by holding TMS at high and pulsing TCK five times.
This is why the Test Reset (TRST) pin is optional.

Run-Test-Idle

In this controller state, the test logic in the IC is active only if certain instructions are present. For
example, if an instruction activates the self test, then it is executed when the controller enters this
state. The test logic in the IC is idle otherwise.

Select-DR-Scan

This controller state controls whether to enter the Data Path or the Select-IR-Scan state.

Select-IR-Scan

This controller state controls whether or not to enter the Instruction Path. The Controller can
return to the Test-Logic-Reset state otherwise.
Capture-IR

In this controller state, the shift register bank in the Instruction Register parallel loads a pattern
of fixed values on the rising edge of TCK. The last two significant bits must always be "01".

Shift-IR

In this controller state, the instruction register gets connected between TDI and TDO, and the
captured pattern gets shifted on each rising edge of TCK. The instruction available on the TDI
pin is also shifted in to the instruction register.

Exit1-IR

This controller state controls whether to enter the Pause-IR state or Update-IR state.

Pause-IR

This state allows the shifting of the instruction register to be temporarily halted.

Exit2-DR

This controller state controls whether to enter either the Shift-IR state or Update-IR state.

Update-IR

In this controller state, the instruction in the instruction register is latched to the latch bank of the
Instruction Register on every falling edge of TCK. This instruction becomes the current
instruction once it is latched.

Capture-DR

In this controller state, the data is parallel-loaded into the data registers selected by the current
instruction on the rising edge of TCK.

Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR and Update-DR

These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR
states in the Instruction path.

Bypass and Identification Registers:

It is a 1-bit register, selected by the Bypass instruction and provides a basic serial-shift
function. It is a 1-bit register, selected by the Bypass instruction and provides a basic serial-shift
function. There is no parallel output (which means that the Update DR control has no effect on
the register), but there is a defined effect with the Capture DR control — the register captures a
hard-wired value of logic 0.
Instruction Register:

Each instruction to be carried out by the boundary scan architecture is stored in the Instruction
Register. An Instruction register has a shift scan section that can be connected between TDI and
TDO, and a hold section that holds the current instruction. There may be some decoding logic
beyond the hold section depending on the width of the register and the number of different
instructions. The control signals to the Instruction register originate from the TAP controller and
either causes a shift-in/shift-out through the Instruction register shift section, or cause the
contents of the shift section to be passed across to the hold section (parallel Update operation). It
is also possible to load (Capture) internal hard-wired values into the shift section of the
Instruction register. The Instruction register must be at least two-bits long to allow coding of the
four mandatory instructions — Extest, Bypass, Sample, Preload — but the maximum length of
the Instruction register is not defined. In capture mode, the two least significant bits must capture
a 01 pattern.

(Note: by convention, the least-significant bit of any register connected between the device
TDI and TDO pins, is always the bit closest to TDO.) The values captured into higher-order bits
of the Instruction register are not defined in the Standard. One possible use of these higher-order
bits is to capture an informal identification code if the optional 32-bit Identification register is
not implemented. In practice, the only mandated bits for the Instruction register capture are the
01 pattern in the two least-significant bits.
Instruction Set:
The IEEE 1149.1 Standard describes four mandatory instructions: Extest, Bypass, Sample, and
Preload, and six optional instructions: Intest, Idcode, Usercode, Runbist, Clamp and HighZ.
Whenever a register is selected to become active between TDI and TDO, it is always possible to
perform three operations on the register: parallel Capture followed by serial Shift followed by
parallel Update. The order of these operations is fixed by the state-sequencing design of the TAP
controller. For some target Data registers, some of these operations will be effectively null
operations, no ops.

EXTEST:

This instruction is used to test interconnect between two chips. The code for Extest used to
be defined to be the all-0s code. The EXTEST instruction places an IEEE 1149.1 compliant
device into an external boundary test mode and selects the boundary scan register to be
connected between TDI and TDO. During this instruction, the boundary scan cells associated
with outputs are preloaded with test patterns to test downstream devices. The input boundary
cells are set up to capture the input data for later analysis.

BYPASS:

A device's boundary scan chain can be skipped using the BYPASS instruction, allowing the
data to pass through the bypass register. The Bypass instruction must be assigned an all-1s code
and when executed, causes the Bypass register to be placed between the TDI and TDO pins. This
allows efficient testing of a selected device without incurring the overhead of traversing through
other devices. The BYPASS instruction allows an IEEE 1149.1 compliant device to remain in a
functional mode and selects the bypass register to be connected between the TDI and TDO pins.
The BYPASS instruction allows serial data to be transferred through a device from the TDI pin
to the TDO pin without affecting the operation of the device.

SAMPLE/PRELOAD:

The Sample and Preload instructions, and their predecessor the Sample/Preload instruction,
selects the Boundary-Scan register when executed. The instruction sets up the boundary-scan
cells either to sample (capture) values or to preload known values into the boundary-scan cells
prior to some follow-on operation. During this instruction, the boundary scan register can be
accessed via a data scan operation, to take a sample of the functional data entering and leaving
the device. This instruction is also used to preload test data into the boundary-scan register prior
to loading an EXTEST instruction.

INTEST:

With this command the boundary scan register (BSR) is connected between the TDI and the
TDO signals. The chip's internal core-logic signals are sampled and captured by the BSR cells at
the entry to the "Capture DR" state as shown in TAP state transition diagram. The contents of the
BSR register are shifted out via the TDO line at exits from the "Shift DR" state. As the contents
of the BSR (the captured data) are shifted out, new data are sifted in at the entries to the "Shift
DR" state. The new contents of the BSR are applied to the chip's core-logic signals during the
"Update DR" state.

IDCODE:

This is used to select the Identification register between TDI and TDO, preparatory to loading
the internally-held 32-bit identification code and reading it out through TDO. The 32 bits are
used to identify the manufacturer of the device, its part number and its version number.
USERCODE: This instruction selects the same 32-bit register as IDCODE, but allows an
alternative 32 bits of identity data to be loaded and serially shifted out. This instruction is used
for dual-personality devices, such as Complex Programmable Logic Devices and Field
Programmable Gate Arrays.

RUNBIST:

An important optional instruction is RunBist. Because of the growing importance of internal

self-test structures, the behavior of RunBist is defined in the Standard. The self-test routine must
be self-initializing (i.e., no external seed values are allowed), and the execution of RunBist
essentially targets a self-test result register between TDI and TDO. At the end of the self-test
cycle, the targeted data register holds the Pass/Fail result. With this instruction one can control
the execution of the memory BIST by the TAP controller, and hence reducing the hardware
overhead for the BIST controller.
CLAMP:

Clamp is an instruction that uses boundary-scan cells to drive preset values established
initially with the Preload instruction onto the outputs of devices, and then selects the Bypass
register between TDI and TDO (unlike the Preload instruction which leaves the device with the
boundary-scan register still selected until a new instruction is executed or the device is returned
to the Test Logic Reset state). Clamp would be used to set up safe guarding values on the outputs
of certain devices in order to avoid bus contention problems.

HIGH-Z:

It is similar to Clamp instruction, but it leaves the device output pins in a high impedance
state rather than drive fixed logic-1 or logic-0 values. HighZ also selects the Bypass register
between TDI and TDO.

Benefits of Boundary Scan:

 Lower test generation cost.
 Reduced test time
 Reduced time to market
 Simpler and less costly testers
 Compatibility with tester interfaces
 High-density packaging devices accommodation

Disadvantages of Boundary Scan:

 Internal scan design cannot have multiple chains
 Cannot test at system clock speed.
 MEMORY BUILT IN SELF TEST

Built In Self Test(BIST):

Built-in Self Test, or BIST, is the technique of designing additional hardware and software
features into integrated circuits to allow them to perform self-testing, i.e., testing of their own
operation (functionally, parametrically, or both) using their own circuits, thereby reducing
dependence on an external automated test equipment (ATE).

BIST is also the solution to the testing of critical circuits that have no direct connections to
external pins, such as embedded memories used internally by the devices. In the near future,
even the most advanced tester may no longer be adequate for the fastest chip, a situation wherein
self-testing may be the best solution for.

Basic architecture of BIST:

BIST is basically same as off-line testing using ATE where the test pattern generator and the test
response analyzer are on-chip circuitry (instead of equipments). As equipments are replaced by
circuitry, so it is obvious that compressed implementations of test pattern generator and response
analyzer are to be designed.

BIST Components:
 Hardware Pattern Generator
 Circuit Under Test(CUT)
 Test Controller
 Output Response Compactor
 ROM
  Comparator

Hardware Test Pattern Generator: This module generates the test patterns required to
sensitize the faults and propagate the effect to the outputs (of the CUT). As the test pattern
generator is a circuit (not equipment) its area is limited. So storing and then generating test
patterns obtained by ATPG algorithms on the CUT (discussed in Module XI) using the hardware
test pattern generator is not feasible. In other words, the test pattern generator cannot be a
memory where all test patters obtained by running ATPG algorithms (or random pattern
generation algorithms) on the CUT are stored and applied during execution of the BIST. Instead,
the test pattern generator is basically a type of register which generates random patterns which
act as test patterns. The main emphasis of the register design is to have low area yet generate as
many different patterns (from 0 to 2n ,if there are n flip-flops in the register) as possible.

Input Mux: This multiplexer is to allow normal inputs to the circuit when it is operational and
test inputs from the pattern generator when BIST is executed. The control input of the
multiplexer is fed by a central test controller.

Output response compactor: Output response compacter performs lossy compression of the
outputs of the CUT. As in the case of off-line testing, in BIST the output of the CUT is to be
compared with the expected response (called golden signature); if CUT output does not match
the expected response, fault is detected. Similar to the situation for test pattern generator,
expected output responses cannot be stored explicitly in a memory and compared with the
responses of the CUT. So CUT response needs to be compacted such that comparisons with
expected responses (golden signatures) become simpler in terms of area of the memory that
stores the golden signatures.

ROM: Stores golden signature that needs to be compared with the compacted CUT response.

Comparator: Hardware to compare compacted CUT response and golden signature (from ROM).

Test Controller: Circuit to control the BIST. Whenever an IC is powered up (signal start BIST is
made active) the test controller starts the BIST procedure. Once the test is over, the status line is
made high if fault is found. Following that, the controller connects normal inputs to the CUT via the
multiplexer, thus making it ready for operation.

Among the modules discussed above, the most important ones are the hardware test pattern
generator and the response compactor. The other ones are standard digital blocks [1]. In the next
two sections we will discuss these two blocks in details.

Hardware pattern generator:

As discussed in the last sub-section, there are two main targets for the hardware pattern
generator—(i) low area and (ii) pseudo-exhaustive pattern generation (i.e., generate as many
different patterns from 0 to 2n as possible, if there are n flip-flops in the register). Linear feedback
shift register (LFSR) pattern generator is most commonly used for test pattern generation in BIST
because it satisfies the above two conditions. There are basically two types of LFSRs, (i) standard
LFSR and (ii) modular LFSR. In this section we will discuss both these LFSRs in detail.

LINEAR FEEDBACK SHIFT REGISTER (LFSR):

The following matrix systems of equations describe the standard LFSR:

LFSR, as the name suggests, it is basically a shift register having D flip-flops where the output of
the last flip-flop provides feedback to the input of the first flip-flop. If there are n flip-flops
(numbered as ), then the LFSR is called n -stage LFSR. The feedback is basically a
linear XOR function of the outputs of the flip-flops. Output of any flip-flop may or may not
participate in the XOR function; if output of any flip-flop Xi say, provides input to the XOR
function then corresponding tap point hi is 1. Similarly, if output of flip-flop Xi does not provide
input to the XOR function then corresponding tap point hi is 0. In the circuit representation
if hi =0, then there is no XOR gate in the feedback network corresponding to the output of the
flip-flop Xi; otherwise, the XOR gate is included.

This LFSR in terms of the matrix can be written as . It may be noted the matrix
Ts. Ts defines the configuration of the LFSR. Leaving behind the first column and the last
row Ts is an identity matrix; this indicates that X0 gets input from X1, X1 gets input from X2 and
so on. Finally, the first element in the last row is 1 to indicate that Xn-1 gets input from X0. Other
elements of the last row are the tap points . The value of ,
indicates that output of flip-flop Xi provides feedback to the linear XOR function. Similarly, the
value of , indicates that output of flip-flop Xi does not provide feedback to
the linear XOR function.

This LFSR can also be described by the characteristic polynomial:

It may be noted that output of flip-flop X2 provides feedback to the XOR network, while flip-
flop X1does not; so h1 =0 and h2=1. The characteristic polynomial of the LFSR
is .

If the initial values of the flip-flops are then the sequence of patters is as
follows:

So the LFSR generates 7 patterns (excluding all 0s) after which a pattern is repeated. It may be
noted that this LFSR generates all patters (except all 0s) which are generated by a 3 bit counter,
however, the area of the LFSR is much lower compared to a counter. In a real life scenario, the
number of inputs of a CUT is of the order of hundreds. So LFSR has minimal area compared to
counters (of order of hundreds).

Hardware response compactor:

This module, expected output (i.e., golden response) of the CUT cannot be sorted explicitly in a
memory and compared with response obtained from the CUT. In other words, in BIST, it is
necessary to compress the large number of CUT responses to a manageable size that can be
stored in a memory and compared. In response compaction, sometimes it may happen that the
compacted response of the CUT under normal and failure conditions are same. This is called
aliasing during compaction.

There are some simple techniques to compress CUT responses namely:

(i) Number of 1s in the output and

(ii) Transition count at the output. For other complex techniques like LFSR based
compaction, multiple input signature register based compaction, built-in logic observer
based compaction etc.

LFSR Properties:
The maximal length cycle of an LFSR with a primitive characteristic polynomial 2^N -1.In a
maximal length cycle “1” appears N+1 times while “0” appears N times.

Types of BIST:
 Logical BIST(LBIST)
 Memory BIST(MBIST)
 Programmable Memory BIST(PMBIST)

Advantages of BIST:
 Lower cost of test, since the need for external electrical testing using an ATE will be
reduced.
 Better fault coverage, since special test structures can be incorporated onto the chips.
 Shorter test times if the BIST can be designed to test more structures in parallel.
 Easier customer support

Disadvantages of BIST:
 Additional silicon area and fabrication processing are required for the BIST circuits.
 Reduced access times.
 Additional pin (and possibly bigger package size) requirements
 MEMORY BUILT IN SELF TEST (MBIST):

MBIST, as its name implies, is used specifically for testing memories. It typically
consists of test circuits that apply, read, and compare test patterns designed to expose defects in
the memory device. There now exists a variety of industry-standard MBIST algorithms, such as
the "March" algorithm, the checkerboard algorithm, and the varied pattern background
algorithm.

One may also encounter the acronym "ABIST", which stands for two totally different BIST
techniques: the Array BIST, which is a form of MBIST used for embedded memories, and
the Analog BIST, which is a BIST approach for analog circuits.

MBIST Architecture:

A typical embedded memory BIST (MBIST) approach comprises an MBIST wrapper, an

MBIST controller and the interconnect between them, as shown in Figure. The MBIST wrapper
further includes an address generator to provide complete memory address sequences (i.e., for n
address lines all the 2n locations are visited in a complete sequence); a background pattern
generator to produce data patterns when testing word-oriented memories (as described in the
preceding chapter); a comparator to check the memory output against the expected correct data
pattern; and a finite state machine (FSM) to generate proper test control signals based on the
commands received from the MBIST controller. The MBIST controller pre-processes the
commands received from upper-level controller (either on-chip microprocessor or off-chip ATE)
and then sends them to the MBIST wrapper. The interconnect between the wrapper and the
controller could be either serial (i.e., a single command line is shared by all the wrappers) or
parallel (i.e., dedicated multiple command lines are linking different wrappers to the controller).
Note, the previously described partition of the MBIST architecture and the terms MBIST
wrapper’ and ’MBIST controller’ are not universal, and only applicable in this thesis.

Memory fault models:

As in the case of gate level digital circuits, testing the physical defects of memory is not
possible. The other possible testing mechanism is to see if each cell can be written with the
desired value (0/1) and be read back, which necessitates modeling of physical defects as logical
faults. In case of memory, if logical fault model is to be applied then first a logic functional
model is to be developed. Modeling faults as logical faults in a logical functional model makes
the testing approach independent of the technology and the manufacturing process. Figure 1
shows logic functional model of a memory.

When data is to be read from the memory, first the row and column decoders determine the
location (i.e., the cell) from the address (sent in the address bus) that needs to be accessed. Based
on the address in the row and column decoders the cell of the appropriate row and column gets
connected to the sense amplifier, which sends the data out. Similar situation (for accessing the
required cells) holds when data is to be written in the memory, however, in case of writing,
special driver circuitry writes the values in the cells from the data bus. Also there is a read/write
select line in the memory. For testing of memory this top level idea of its working suffices. It
may be noted that from the testing perspective we would only check if

• The required value (0/1) can be written to a cell

• The stored value can be read from a cell

• The proper cell is accessed, i.e., the row and column decoder do not have faults.

It may be noted that the row and column decoders are digital circuits implemented using logic
gates (which are different from memory cell implementation). The sense amplifier and driver are
analog circuits. In testing of memory, we do not consider the decoders as gate level digital
circuits nor the sense amplifier and driver as analog circuits. For the decoders, we test the
functionality whether they can access the desired cells based on the address in the address bus.
For the amplifier and driver we check if they can pass the values to and from the cells correctly.
There can be a large number of logical faults b However, the following faults called “reduced
functional faults” are sufficient for functional memory testing

 Stuck-at fault
 Transition fault
 Coupling fault
 Neighborhood pattern sensitive fault

Stuck-at-fault:

• The logic value of (a line or) a cell is always 0 (SA0) or 1 (SA1)

• To detect memory cell's SAFs:

– SA0: Write 1 Read 1 (w1 r1)

– SA1: Write 0 Read 0 (w0 r0)

Transition fault:

• A cell fails to undergo a 0  1 transition (TFrise) or a 1  0 transition (TFfall) when it is

written

• To detect transition fault:

– TFrise : w0 w1 r1

– TFfall : w1 w0 r0
Coupling Faults:

Coupling fault, as the name suggests, implies deviation from normal behavior of a cell
because of coupling with others. As there can be exponential number of combinations of
coupling of a cell with others cells, we assume that in coupling faults a faulty cell can get
coupled with another faulty cell. In other words, in the widely used coupling fault model it is
assumed that any “two” cells can couple and normal behavior changes in these two cells; it is
called 2-coupling fault model. So if there are n cells in a memory then there can be nC2 number
of 2-coupling faults. To reduce the number of 2-coupling faults further from nC2 we assume that
only neighboring cells (decided on threshold distance) can be involved in the fault. We consider
two types of coupling faults namely:

(i) Inversion coupling faults and

(ii) Idempotent coupling faults.

Bridging fault

A bridging fault is a short circuit between two or more cells. As in the case of coupling
faults, to keep the number of faults within a practical number, it is assumed that only two cells
can be involved in a bridging fault. There are two types of bridging faults

•AND bridging fault ANDibi,j (involving cells i and j) which results in values in
cells i and j to be logic AND of the values in these cells under normal condition. AND bridging
fault is represented by where the first two places represent the values
in cells i and j under normal condition and the two values following “|”represent the values in
cells i and j under AND bridging fault. are the four types
of AND bridging faults possible.

• OR bridging fault ORbfi,,j (involving cells i and j ) which results in values in cells i and j to
be logic OR of the values in these cells under normal
condition. are the four types of OR bridging faults
possible.

Neighborhood pattern sensitive coupling faults

One of the most important and different kind of fault in memory compared logic gate circuits is
neighborhood pattern sensitive faults (NPSFs). As memory cells are very close to each other, the
cells behave normally except for certain patterns in the neighborhood cells. For example, if a
cell i has 0 and all the neighboring cells have 1, then the value of cell i may be pulled up to 1. It
is obvious that given a cell there can be infinite number of neighborhood combinations. However
for all practical cases there are two types of neighborhoods used in fault modeling for the cell
under test.

Address decoder faults:

Row and column decoder blocks comprise the address decoder. As discussed before these
blocks are composed of logic gates. However, their testing and fault models are different from
that used to test circuits made of logic gates. From the context of memory testing four types of
faults are considered in address decoder (for both reading and writing).

• No cell is accessed for a certain address

• No address can access a certain cell

• With a particular address, multiple cells are simultaneously accessed

• A particular cell can be accessed with multiple addresses.

MBIST Structure:

A broad architecture for memory BIST using LFSR is shown in Figure 17. The various blocks
are explained as follows

LFSR:

The LFSR block comprises both forward and reverse LFSRs. This block is used to generate
address of the memory cells where read/write is to be done

Data:

The data block to writes 0 and 1 in the cells as per steps of March test.

Equality comparator:

The comparator eliminates the need to generate the good machine response, response
compaction etc.

Controller:

It basically coordinates the BIST procedure. It selects forward LFSR and backward LFSR
alternatively to generate address for memory cells

Test Algorithms:
Notations used:

–  : indicates address ascending order

–  : indicates address descending order

– w0 : write 0 at current location

 – w1 : write 1 at current location

– r0 : read current location, expecting a 0

– r1 : read current location, expecting a 1

– (….): algorithm element

– {(…),(…),…,(…)}: full algorithm

Test Algorithm: Zero-One:

• This minimal test consists of writing 0s and 1s in the memory

– Step1: write 0 in all cells

– Step2: read all cells (0 expected)

– Step3: write 1 in all cells

– Step4: read all cells (1 expected)

• O(n) test

• Fault coverage:

– Not all AFs detected

– SAFs detected if the adress decoder is fault free

– Not all TFs and CFs detected

Test Algorithm : Checkerboard :

• Cell are divided in two groups

– Step1: write 1 in all green cells and in pink cells

– Step2: read all cells

– Step3: write 0 in all green cells and 1 in pink cells

– Step4: read all cells

• This test is able to detect bridging faults

 In the checkerboard the pattern present in the memory should be alternate location of zeros and
ones. These are good for stuck at faults and data retention faults.

Data retention faults means when we write some value in any one of the cell and it is expected
that the value will be retained and after some time we again do a read operation and found that
the value has been changed.

March Tests:
• The test is "marching" through the memory

• The test is composed of March elements represented between ()

• March tests: example of MATS++

• {(w0); (r0,w1); (r1,w0,r0)}

March Test Summary:

Name Ref. algorithm

MATS [NAI79] { (w0); (r0,w1);(r1)}
MATS+ [ABA83] {(w0);(r0,w1); (r1,w0)}
MATS++ [VAN91] {(w0);(r0,w1);(r1,w0,r0)}
March X [VAN91] {(w0);(r0,w1);(r1,w0);(r0)}
March C- [MAR82] {(w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0)}
March A [SUK81] {(w0);(r0,w1,w0,w1);(r1,w0,w1);(r1,w0,w1,w0);(r0,w1,w0)}
March Y [VAN91] {(w0);(r0,w1,r1);(r1,w0,r0);(r0)}
March B [SUK81] {(w0);(r0,w1,r1,w0,r0,w1);(r1,w0,w1);(r1,w0,w1,w0);
(r0,w1,w0)}
March GS [VAN93] {(w0);(r0,w1,r1,w0,w1);(r1,w0,r0,w1);(r1,w0,w1,w0);
(r0,w1,r1,w0);Del;(r0,w1,r1);Del;(r1,w0,r0)}
March M [MIK96] {(w0);(r0,w1,r1,w0);(r0);(r0,w1);(r1);(r1,w0,r0,w1,);(r1);(r1,w0)}
March LR [VAN96] {(w0);(r0,w1);(r1,w0,r0,w1);(r1,w0);(r0,w1,r1,w0,);(r0)}
March U [VAN97] {(w0);(r0,w1,w0,w1,r1);(r1,w0,w1,w0,r0);(r0,w1,w0,w1,r1);
(r1,w0,w1,w0,r0;  (r0)}
March LA [VAN99] {(w0);(r0,w1,r1,w0);(r0,w1);  (r1,w0,r0,w1);  (r1,w0)}
March SR [VAN00] { (w0);(r0,w1,r1,w0);(r0,r0); );(w1), (r1,w0,r0,w1);  (r1,r1)}
 Other March Algorithms:
SAF AF TF CF

MATS ALL Some

MATS++ ALL ALL

March X ALL ALL ALL Some

March C- ALL ALL ALL ALL

March A ALL ALL ALL Some

March B ALL ALL ALL Some

March Y ALL ALL ALL Some

Advantages of MBIST: There are several advantages of MBIST

 It allows for robust testing of memories

 Reduced test time
 All the memories of the design can be tested in parallel
 Lesser test cost

Disadvantages of MBIST: Inspite of many advantage of MBIST, there is only one

remarkable limitation. Insertion of MBIST causes increase in area. However, this increase in area
is very small in comparison to the benefits it provides.
 DUAL PORT MEMORY
A dual port memory accesses two different cells or the same cell simultaneously through two
ports. The fault detection related to dual port memories is not possible with general BIST
structure. Therefore, in this paper, it proposes an efficient BIST structure that can test dual port
memories. It uses March A2PF algorithm that detects all the faults that occur in dual port
memories.

The structure of dual port memories is shown in fig. The structure with all the input and output
signals defined. Among input/output signals of each port, the Chip Enable is the enable signal -
158 - that controls the operation of the port. The Read/Write Enable is an enable signal that
enables the read/write of data in memory. Also, the Address/Data is the address/data input
signals, and the Output is the data output signal. The CLK is the clock cycle signal for operating
port. The proposed structure of the BIST for testing the dual port memories is consisted of the
following. There is the BIST controller that generates the control signal. Also, there is the dual-
port controller that matches the data and the address sequence of dual port memories algorithm.
There is the address generator for generating the address, and the data generator for generating
data pattern. Also, it is consisted of the data comparator that compares the test results. The BIST
controller controls the memory BIST, and generates the control signals that are needed during
the memory tests. The address generator and the data generator generate the memory address and
data patterns during memory tests. Data comparator compares the read data and the expected
data to determine the existence of faults. The Figure shows this dual-port memories BIST
(DPMBIST) architecture.
BIST Controller:
BIST controller controls the operation of each memory BIST module during the test process.
This module determines the starting and the ending of the test process. Also it ensures the
running of test cycles by approving the signals to each module. BIST controller approves the
DGentEn control signal to the data generator that generates the data pattern, which corresponds
to each March element that forms the algorithm. Also, the BIST controller approves the
AGenEN control signal to the address generator that ensures the data pattern performs the
read/write operations at the correct address of the memory. Furthermore, the DComEn control
signal is approved for the data comparator, through which faults are verified. It also generates the
control signals of the memory BIST that are needed during the memory tests.
Address Generator:
When the address generator receives the AGenEN control signal from BIST controller, it
generates the target memory address. Address generator is consisted of 4 counters. The first is
the general counter that increase/ decrease from the first address of memory to the last address. It
enables read/write of test data on the correct address. Two of these counters are used. Also, it is
consisted of the counter for increment/decrement the address of row+1, and the counter for
increment/ decrement the address of column+1. There are march elements of the dual port
memories test algorithm that have the aggressor cell and the victim cell with difference in
increment/decrement address. Unlike the aggressor cell, the victim cell is accessed at the address
row+1, or the column+1. In order to generate addresses for these cases, the two special counters
are added. When the memory address switches from increment to decrement or from decrement
to increment, complementing the address through sign en signal generates the address.
Data Generator:
Data generator module generates the data pattern by the DGenEn control signal of the BIST
controller. It generates the background data or the test data for the memory test.

Dual-port Controller:
Dual-port controller is the module that generate, through analysis of the March A2PF, the
data and the address that match correctly with the sequence of the data and the address, in
accordance with the algorithm steps. Also, the dual-port controller approves the control signals
that generate the background data on the data generator.

Data Comparator:
Data comparator compares the output values read from the memory with the expected values
generated from data generator. The DComEn control signal is received from the BIST controller,
through which output values are read from the memory. These read values are compared with the
generated expected values from the data generator to detect for faults. Then it sends the final test
results through BIST controller.
 OPCG

A logic design for on-chip high-speed clock generation, implemented to avoid expensive
test equipment. Techniques for on-chip clock generation, meant to reduce test vector count and
to increase test quality.
Delay test is a two-vector (cycle) test. The first vector initializes the test. The second vector
launches the desired transition at the source of a path under test and propagates the launched
transition to an observation point. Test responses are captured with the next active clock edge at
the observation point. Thus, test frequency requirements between initial and launch vector are
relaxed, while the clock between launch and capture has to be operated at the functional speed of
the device under test (DUT). Two techniques are known to apply two-vector tests using a
standard scan architecture, “Scan shifting” or shifts the initial vector into the scan chains and
generates the launch vector by using the last shifting cycle. In justification”, “broadside or
capture” the initial vector is shifted into the scan chains. The launch vector is the functional
response of the DUT to the initial vector. “Scan shifting” requires the ability to switch the scan-
enable signal at-speed. In addition, the risk of testing non functional paths is higher for “scan
shifting” since both vectors are completely independent of the DUT function. Due to the
disadvantages of “scan shifting”, it was decided to implement delay testing based on “functional
justification”.
SOC devices implement multiple functional clock domains. An at-speed test has to test all
clock domains at their own functional speeds. Testing one clock domain after another is a
potential solution for multi-clock domain delay test. However, the logic between the clock
domains remains untested and the number of patterns is comparably high. Testing all clock
domains simultaneously requires separate clock pins for each domain and a complex clocking
procedure if an ATE is used to apply the test clock.
The usage of an ATE for clocking also requires a high speed clock generator to apply at-
speed clock pulses for launch and capture. A high-speed clock generator is usually not available
in low-cost ATE. Even if a high-speed clock generator is available, it is doubtful that a high-
speed clock can be transmitted into the DUT. Today’s especially controller devices,
communicate to their environment at a comparably low speed. Therefore, the device pads are
slow compared to the internal frequency. The application of an external high-speed clock would
require the additional implementation of a high-speed pad that is capable of transmitting the
clock signal. To overcome these issues the functional on-chip PLL can be used to generate at
speed clock pulses for test purposes.
 Scan chain loading and unloading
Scan chain design is a popular design-for-test technique for testing of sequential circuits.
Significant amount of power is consumed during loading and unloading of scan chains due to
weighted transitions. As the power consumption in the test mode is quite high compared to
normal circuit operation, the test power has become the prime concern .Scan chain reordering is
widely used method to reduce test power.

During test mode, the flip-flops are loaded with scan-in vector. This vector is shifted to
scan chain via scan-in primary input pin in serial fashion. So each flip-flop undergoes with lots
of transitions. This causes a large amount of power consumption during test mode. Therefore, it
is very common that with the scan design, the circuit-under-test (CUT) will consume much more
power in its test mode than that in its functional mode. This excessive power consumption during
the scan-based testing may result in physical damage or reliability degradation to the CUT, and
in turn decreases the yield and product lifetime. The increased functionality per chip has
demanded the increase in number of flip-flops per chip.

Scan chain insertion is a widely used, effective Design-For Test (DFT) technique. The flip
flops are arranged in a scan chain using a 2×1 multiplexer before each flip flop. Here the flip
flops in the circuit are connected into a scan chain so that the flip flops can be initialized as and
when required through the ATE or BIST. This enhances the controllability and observability of
the flip flops. The multiplexers are controlled by a TC (scan enable) signal. After scan chain
insertion, the circuit functions in two modes: Normal mode (TC = 0) and Test mode (TC = 1).

When the test pattern generation is done using any known Automatic Test Pattern
Generator (ATPG), the test pattern generation algorithm sitting inside the ATPG generates the
following test patterns:

1. Patterns to be loaded serially into the scan chain through scan-in (SI) input. (Load patterns).
The bits in this pattern are loaded to scan chain flip-flops serially via SI.

2. Patterns to be applied at the primary input pins. The bits in this pattern are applied to
corresponding Primary Input pins (PIs) simultaneously.

3. Patterns to be checked at the output pins. The bits in this pattern are checked at corresponding
Primary Output pins (POs) simultaneously.

4. Patterns to be observed serially from the scan chain through scan-out (SO) output. (Unload
patterns). The bits in this pattern are unloaded from scan chain flip-flops serially via SO.

Loading and unloading test patterns during scan testing causes many scan flip-flops to
trigger simultaneously. This instantaneous switching activity during shift in turn may cause
excessive IR-drop that can disrupt the states of some scan flip-flops and corrupt test stimuli or
responses. A common design technique to even out these instantaneous power surges is to design
multiple scan chains and shift only a group of the scan chains at a same time. For a given test
data set containing n vectors with m bits each, let’s denote scan-in vector by t and scan-out
vector by p.

The WTM for the loading operation is given for jth pattern and ith bit in the pattern by equation:
𝑛
WTM load = ∑ (t(j, i)XOR t(j, i + 1)) ∗ (n − i)
𝑖=1

Where j = 1,2,………….m
𝑛
p(j, i)XOR p(j, i + 1) ∗ i
WTM unload = ∑
𝑗=1

Here load pattern means that the flip flop will have the corresponding value after loading the
scan chain. Unload pattern means that the flip flop will have the corresponding value before
unloading the scan chain.

Scan Testing:
In a full or partial scan design, the sequential elements are converted to scan flops and are
stitched back to back along the Q → SD path to form a chain of scan flops referred to as the scan
chain, which can be shifted in at one end through the scan in port and shifted out through the
other end which is the scan out port. Scan testing for stuck-at faults like opens and shorts consists
of two steps, viz. load-unload procedure and capture procedure.

Load-Unload procedure:
In the load-unload step, the state of internal sequential elements required to excite a fault is
loaded into elements by shifting the test vector into scan chain. As the test vector is loaded into
the scan chain, the current state of the design gets scanned out. Thus in this step, a new state of
the design is directly loaded into the sequential elements and the existing state is read directly as
part of the unload operation.

During load-unload procedure the scan-enable pin is asserted high and the value in the SD is
captured into the flop at the arrival of a clock edge in a edge triggered MUX scan flop.
 Fig: Normal D Flop, Mux Scan Flop, Scan Chain

Capture procedure:
The load-unload procedure initializes the design into a state which can excite a fault. The
fault is excited and the response is captured into another flop in the capture procedure. During
the capture procedure cycle, the scan-enable pin is asserted low and the value in the D is
captured into the flop at the arrival of a clock edge in edge triggered MUX scan flop.
 ASSIGNMENT-2

Difference between serial simulation and parallel simulation?

In parallel pattern simulation, the values that should have actually reached the D i/p of FFs
in scan chain by shifting through the Scan Inputs are directly forced at the D i/p by the simulator.
This way, we save the time for shifting the pattern data.

In serial simulation, the pattern is shifted through the scan-in ports and loaded in the scan
chain. The disadvantage is that it takes longtime for the pattern to load into the scan chains,
capture the output and then shift out through the scan-out ports, especially as in the practical
designs the scan chains are as long as 5000 flops. For debugging, we can use serial patterns as
we can see all the events associated with scan as-such. Also in ATE, the serial patterns are used
for testing.

Serial fault simulation:

1. The circuit is first simulated (using event driven simulator) without any fault for a random
pattern and primary output values are saved in a file.

2. Next, faults are introduced one by one in the circuit and are simulated for the same input
pattern. This is done by modifying the circuit description for a target fault and then using event
driven simulator.

3. The output values (at different primary outputs) of the faulty circuit are compared with the
saved true responses. The simulation of a faulty circuit halts when output value at any primary
output differs for the corresponding normal circuit response. All faults detected are dropped and
the procedure repeats for a new random pattern.
Parallel fault simulation:

Parallel fault simulation can processes more than one fault in one pass of the circuit simulation.
It uses bit-parallelism of a computer.
Logic present in de-compressor and compactor?
Test Compression is driven by two structures:

A De-compressor and

A Compressor (or Compactor)

The De-compressor drives the test stimuli onto the IC from the small number of scan-in pins
on the ATE to the large number of internal scan channels which are applied to the IC. The De-
compressor is designed to allow a continuous flow of stimuli so that it is possible to load the scan
chain data for a given test onto the IC and to unload from the IC the previous test response data
to the Compressor, all in a single clock cycle. Compression and De-compression logic generally
are built using discrete logic gates such as:

XORs, multiplexers and flip-flops and placed inside a logic module called CoDec which is
normally placed in one corner of the IC.
Dead cycle:

The ATPG tools will target a transition fault and then automatically find a path where the
transition from the launch point will propagate through the targeted fault location. Clock
application is usually applied by doing the following: loading the scan chains at a slow
frequency, switching to functional mode, and pulsing a launch and capture clock with the desired
timing. This sequence is referred to as a broadside or launch-from-capture pattern. The timing of
the scan-chain load is completely independent of the at-speed launch and capture cycles. An
extra "dead cycle" can be used if additional time is desired to allow the scan-enable signal to
settle prior to applying the launch-clock pulse.

Another method to apply the at-speed scan pattern also is possible. Called "launch-off-shift"
(LOS), it is usually avoided by most companies. In a "launch-off-shift" pattern, the transition
occurs because the last shift in the load-scan chains is the launch cycle. The scan-enable must
turn off very quickly. One clock is pulsed in functional mode to capture the response at the end
of a path.

Dead cycles are also needed when mode transitions, such as the read to write operation and
the selection of different DRAM chip occurs.

Test points:
Test points are points in the design where the DFTMAX tool inserts logic to improve the
testability of the design. The tool can automatically determine where to insert test points to
improve test coverage and reduce pattern count. You can also manually define where test
points are to be inserted.

Test points consists of MUX, XOR components.

Clock gating:
Clock gating will be operated in functional mode only.