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Lab 7: Digital Gates

  • 1 Introduction

We are now preparing to leave the analog world and move into digital terri- tory. This is a place where, thanks to transistors and op-amps and the like, we will no longer worry about input and output impedances, and will start dealing only with ones and zeroes. In this lab we will look at how to make the gates work properly and what makes them tick, before going fully digital.

  • 2 New Tools

For this lab, and the ones that remain, you will using some new parts of the breadboard and probes to help you observe the workings of the digital gates. The Slide Switch will be used to provide either 0 V or +5 V. Simply connect one side of the switch to the +5 V line of the breadboard and the other to ground. The selector switch will choose to which side the output is connected. To make sure the switch is working properly you can test it by using the digital logic probe and verifying that you observe the expected output. Alternatively, you can use the LEDs of the breadboard. The Digital Logic Probe can be used to test different parts of the circuit. It is in the shape of a pen, and if properly powered (it needs a reference +5 V and ground), lights up “high” or “low”. Remember, if neither light is on, this means your output is not in a well-defined digital state. You will not need voltages that exceed 5 V in this lab, and for the survival of your chip, you shouldn’t want to.

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  • 3 Input and Output Characteristics of Inte- grated Gates

3.1 V out

You will begin by testing two different types of NAND gates: CMOS and TTL. The TTL part is 74SL00 and the CMOS part is 74CH00. They both have the same pinout which is shown in Figure 1. For the CMOS part tie all six unused input lines to a common line, and temporarily ground that line.

14 13 12 11 10 9 8 V CC (+5V) GND 1 2 3 4 5
14
13
12 11
10
9
8
V CC
(+5V)
GND
1
2
3
4
5 6
7
Figure 1: TTL and CMOS chip pinout.
Question 1 Complete the following truth table and voltage list for the TTL
and CMOS NAND gates:
INPUT OUTPUT VOLTAGES
TTL CMOS
0
0
0
1
1
0
1
1
Table 1: Fill out the OUTPUT column with logic values 1 or 0, and the
voltages with voltmeter measured values.
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  • 3.2 Floating Input

While doing a lab on JFETs you observed what happens when you let the gate of a MOSFET float. We will now do the same to the inputs of the TTL and CMOS NAND gates. Disconnect both inputs to the NAND, and note the output logic level.

Question 2 For the TTL circuit, what logic level did you observe at the out- put in this case? Refer to Figure 2 and explain why this is the expected result.

A Q B Figure 2: The TTL NAND gate.
A
Q
B
Figure 2: The TTL NAND gate.

We now try the same experiment for the CMOS NAND gates, however this time, wire up the circuit shown in Figure 3. Use the mA scale on your voltmeter and measure the current as you go from one well-defined logic level to another, with (of course) a not-so-well-defined level in between.

Question 3 When you connected the set of CMOS NAND circuits as in Figure 3, you probably saw non-negligible currents on the milliammeter yet CMOS circuits are supposed to be useful because of their low operating current. Why does the CMOS NAND draw such high current in this case? (refer to Figure 4 to see how the CMOS NAND is built) The NAND gate is the most useful gate in that any logic operation can made by a combination of NANDs. One such operation is the XOR (exclusive OR) gate. The truth table of the XOR gate is shown in Table 2. As you may suspect there isn’t a unique way to setup the NAND gates

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+5

10k

14 +5 7
14
+5
7

Figure 3: A circuit to explore the consequences of floating CMOS inputs

+5 V

Q A B
Q
A
B

Figure 4: The CMOS NAND gate circuit diagram.

in order to produce an XOR.

Question 4 Design an XOR gate using 5 NANDs and then 4 NANDs. Hint:

For the 4-NAND version the output of one of the NANDs can be reused.

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A B Out

  • 00 0

  • 01 1

  • 10 1

  • 11 0

Table 2: The XOR truth table.

4 Inverters

In the following experiments you will use two CD4007 packages. This part is an array of complementary MOS transistors. The pinout is shown in Figure 5.

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14 2 11 13 1 3 10 8 5 7 4 9
14
2
11
13
1
3
10
8
5
7
4
9

12

Figure 5: CMOS pinout.

Wire up the circuit in Figure 6. Be sure to tie the two body connections appropriately: pin 14 to +5 V, pin 7 to ground. Confirm that this circuit does indeed invert by driving it with a TTL level from the breadboard oscillator pulled up to +5 V through a 1 kΩ resistor. Watch the output on the scope, as the logic probe will not do. Start with a frequency in the 1 kHz range and work your way up to the 100 kHz range. Now wire up the active pullup inverter circuit shown in Figure 7. Again, drive it with the same TTL waveform from your breadboard with the same frequencies.

5

+5 V

6

8 7
8
7

Figure 6: The simplest inverter: passive pullup.

+5 V

14 13 6 8 7
14
13
6
8
7

Figure 7: An active pullup inverter.

Question 5 Make a quick sketch of V out vs f for both frequency ranges and for both inverters. Which transition is faster: 0 V to 5 V, or 5 V to 0 V? Why? Was the speed improved for the active pull-up circuit of Figure 7?

  • 5 CMOS Three-State

Thus far you’ve seen two well-defined digital states, high and low. We can however introduce a third state: off. This state becomes very useful in com- puters: it allows multiple drivers to share a single driven wire, or bus line. Here you will build a buffer (a gate that does nothing except give a fresh start to a signal), and you will be able to switch its output to the OFF state. A block diagram of the three-state buffer is shown in Figure 8. Q up and Q down refer to the pull-up and pull-down transistors. The trick is to add some logic in order to turn off both the pull-up and pull-down transistors such that the

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output is disconnected from both +5 V and ground, which leaves the output floating.

V+ Q up in Logic out Q down enable
V+
Q up
in
Logic
out
Q down
enable

Figure 8: A block diagram of the three-state buffer.

A design for the three-state circuit is shown in Figure 9. Wire the circuit

+5 V

in out enable
in
out
enable

Figure 9: A 3-state circuit design.

up and test it by driving the input with the breadboard oscillator, while the output is tied to a 100 kΩ resistor driven from a slide switch. The slide switch can be set to ground or +5 V. Use another slide switch to control the “enable”. Observe the output on the scope.

Question 6 How is the third state (disconnected) in Figure 9 achieved, i.e. what happens to the MOSFETs? Does the 3-state disappear electrically, when you disable the gate?

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  • 6 A small design problem

Question 7 Draw a diagram of some logic circuit that will light an LED if either or both the left and right door of a car are open and if the driver is seated. Assume that the doors and seat are equipped with switches, and that only NAND gates are available. (Your circuit should also be as simple as possible).

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