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Data Sheet

26186.120

6259

ADVANCE INFORMATION

(Subject to change without notice) January 24, 2000 POWER POWER 1 20 GROUND GROUND LOGIC
(Subject to change without notice)
January 24, 2000
POWER
POWER
1
20
GROUND
GROUND
LOGIC
2
V
19
CLEAR
DD
SUPPLY
S
0 (LSB)
3
18
DATA
OUT 0
4
17
OUT 7
OUT 1
5
16
OUT 6
OUT 2
6
15
OUT 5
OUT 3
7
14
OUT 4
8
EN
13
ENABLE
S 1
LOGIC
9
12
S
2 (MSB)
GROUND
POWER
10
11
POWER
GROUND
GROUND
LATCHES
DECODER LOGIC
LATCHES

Dwg. PP-050-2

Note that the A6259KA (DIP) and the A6259KLW (SOIC) are electrically identical and share a common terminal number assignment.

ABSOLUTE MAXIMUM RATINGS at T A = 25°C

Output Voltage, V O Output Drain Current, Continuous, I O Peak, I OM Peak, I OM Single-Pulse Avalanche Energy,

50 V

250 mA*

750 mA*†

2.0 A†

E AS

75 mJ

7.0 V

Logic Supply Voltage, V DD Input Voltage Range, V I Package Power Dissipation,

P D Operating Temperature Range,

-0.3 V to +7.0 V

See Graph

T A

-40°C to +125°C

Storage Temperature Range,

T S

-55°C to +150°C

*Each output, all outputs on. † Pulse duration 100 µs, duty cycle 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges.

8-BIT ADDRESSABLE DMOS POWER DRIVER

The A6259KA and A6259KLW combine a 3-to-8 line CMOS

decoder and accompanying data latches, control circuitry, and DMOS

outputs in a multi-functional power driver capable of storing single-line

data in the addressable latches or use as a decoder or demuliplexer.

Driver applications include relays, solenoids, and other medium-current

or high-voltage peripheral power loads.

The CMOS inputs and latches allow direct interfacing with micro-

processor-based systems. Use with TTL may require appropriate pull- up resistors to ensure an input logic high. Four modes of operation are

selectable with the CLEAR and ENABLE inputs.

The addressed DMOS output inverts the DATA input with all

unaddressed outputs remaining in their previous states. All of the output

drivers are disabled (the DMOS sink drivers turned off) with the CLEAR input low and the ENABLE input high. The A6259KA/KLW DMOS open-drain outputs are capable of sinking up to 750 mA. Similar devices with reduced r DS(on) are available as the A6A259.

The A6259KA is furnished in a 20-pin dual in-line plastic package. The A6259KLW is furnished in a 20-lead wide-body, small-outline plastic package (SOIC) with gull-wing leads for surface-mount applica- tions. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85°C.

FEATURES

50 V Minimum Output Clamp Voltage

250 mA Output Current (all outputs simultaneously)

1.3 Typical r DS(on)

Low Power Consumption

Replacements for TPIC6259N and TPIC6259DW

Always order by complete part number:

Part Number

Package

R θJA

R θJC

A6259KA

20-pin DIP

55°C/W

25°C/W

A6259KLW

20-lead SOIC

70°C/W

17°C/W

6259

8-BIT ADDRESSABLE

DMOS POWER DRIVER

2.5 2.0 1.5 1.0 SUFFIX 'A', R θJA = 55°C/W SUFFIX 'LW', R θJA =
2.5
2.0
1.5
1.0
SUFFIX 'A', R
θJA
= 55°C/W
SUFFIX 'LW', R
θJA
= 70°C/W
0.5
0
25
50
75
100
125
150
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

AMBIENT TEMPERATURE IN °C

IN

V DD Dwg. EP-010-15
V
DD
Dwg. EP-010-15

LOGIC INPUTS

Dwg. GS-004A

LOGIC SYMBOL

3 0 8 8M 0/7 12 2 13 G8 18 Z9 19 Z10 9,0D 4
3
0
8
8M 0/7
12
2
13
G8
18
Z9
19
Z10
9,0D
4
10,0R
9,1D
5
10,1R
9,2D
6
10,2R
9,3D
7
10,3R
9,4D
14
10,4R
9,5D
15
10,5R
9,6D
16
10,6R
9,7D
17
10,7R
Dwg. FP-046
OUT Dwg. EP-063
OUT
Dwg. EP-063

DMOS POWER DRIVER OUTPUT

FUNCTION TABLE Inputs Addressed Other CLEAR ENABLE DATA OUTPUT OUTPUTs Function H LH L R
FUNCTION TABLE
Inputs
Addressed
Other
CLEAR ENABLE
DATA
OUTPUT
OUTPUTs
Function
H
LH
L
R
Addressable
H
LL
H
R
Latch
H
H
X
R
R
Memory
L
LH
L
H
8-Line
L
LL
H
H
Demultiplexer
L
H
X
H
H
Clear
L = Low Logic Level
H = High Logic Level
X = Irrelevant
R = Previous State

LATCH SELECTION TABLE

Select Inputs

Addressed

S 2 (MSB)

S 1

S 0 (LSB)

OUTPUT

LLL

0

LLH

1

LHL

2

LHH

3

HLL

4

HLH

5

HHL

6

HHH

7

6259

8-BIT ADDRESSABLE DMOS POWER DRIVER

FUNCTIONAL BLOCK DIAGRAM

D S 0 (LSB) C1 CLR D C1 CLR S 1 D C1 CLR D
D
S
0
(LSB)
C1
CLR
D
C1
CLR
S
1
D
C1
CLR
D
C1
CLR
S
2
(MSB)
D
C1
CLR
D
LOGIC
V DD
SUPPLY
C1
CLR
LOGIC
GROUND
D
C1
CLR
DATA
D
ENABLE
C1
(ACTIVE LOW)
CLR
CLEAR
(ACTIVE LOW)

OUT 0 OUT 0

OUT 1 OUT 1

OUT 2 OUT 2

OUT 3 OUT 3

OUT 4 OUT 4

OUT 5 OUT 5

OUT 6 OUT 6

OUT 7 OUT 7

POWER

GROUND

Dwg. FP-047-1

Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.

6259

8-BIT ADDRESSABLE DMOS POWER DRIVER

RECOMMENDED OPERATING CONDITIONS

over operating temperature range

Logic Supply Voltage Range, V DD High-Level Input Voltage, V IH Low-level input voltage, V IL

4.5 V to 5.5 V 0.85V DD 0.15V DD

ELECTRICAL CHARACTERISTICS at T A = +25°C, V DD = 5 V, t ir = t if 10 ns (unless otherwise specified).

       

Limits

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Units

Logic Supply Voltage

 

V

DD

Operating

4.5

5.0

5.5

V

Output Breakdown Voltage

V

(BR)DSX

I O = 1 mA

50

V

Off-State Output

 

I

DSX

V O = 40 V

0.05

1.0

µA

Current

 

V O = 40 V, T A = 125°C

0.15

5.0

µA

Static Drain-Source On-State Resistance

r

DS(on)

I O = 250 mA, V DD = 4.5 V

1.3

2.0

 

I O = 250 mA, V DD = 4.5 V, T A = 125°C

2.0

3.2

 

I O = 500 mA, V DD = 4.5 V (see note)

1.3

2.0

Nominal Output

I

O(nom)

V DS(on) = 0.5 V, T A = 85°C

250

mA

Current

 

Logic Input Current

 

I IH

V I = V DD = 5.5 V

1.0

µA

 

I IL

V I = 0, V DD = 5.5 V

-1.0

µA

Prop. Delay Time

 

t

PLH

I O = 250 mA, C L = 30 pF

625

ns

 

t

PHL

I O = 250 mA, C L = 30 pF

140

ns

Output Rise Time

 

t

r

I O = 250 mA, C L = 30 pF

650

ns

Output Fall Time

 

t

f

I O = 250 mA, C L = 30 pF

400

ns

Supply Current

I DD(off)

V DD = 5.5 V, Outputs OFF

15

100

µA

I DD(on)

V DD = 5.5 V, Outputs ON

150

300

µA

Typical Data is at V DD = 5 V and is for design information only.

NOTE — Pulse test, duration 100 µs, duty cycle 2%.

6259

8-BIT ADDRESSABLE DMOS POWER DRIVER

FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS

ENABLE 50% DATA t PLH t PHL 90% ADDRESSED OUTPUT 10% t t r f
ENABLE
50%
DATA
t PLH
t PHL
90%
ADDRESSED
OUTPUT
10%
t
t
r
f
Dwg. WP-036
OUTPUT SWITCHING TIME ENABLE 50% t su(D) t h(D) DATA 50% t w(D)
OUTPUT SWITCHING TIME
ENABLE
50%
t su(D)
t h(D)
DATA
50%
t w(D)

Dwg. WP-037

DATA INPUT REQUIREMENTS

Data Active Time Before Enable (Data Set-Up Time), t su(D)

20 ns

Data Active Time After Enable (Data Hold Time), t h(D) Data Pulse Width, t w(D) Input Logic High, V IH Input Logic Low, V IL

20 ns 40 ns 0.85V DD 0.15V DD

Four modes of operation are selectable by controlling the CLEAR and ENABLE inputs as shown above.

In the addressable-latch mode, data at the DATA input

is written into the addressed transparent latch. The addressed output inverts the data input with all other outputs remaining in their previous states.

In the memory mode, all outputs remain in their previous states and are unaffected by the DATA or address (S n ) inputs. To prevent entering erroneus data in the latches, ENABLE should be held HIGH while the address lines are changing.

In the demultiplexing/decoding mode, the addressed

output inverts the data input and all other outputs are OFF.

In the clear mode, all outputs are OFF and are unaf- fected by the DATA or address (S N ) inputs.

Given the appropriate inputs, when DATA is LOW for a given address, the output is OFF; when DATA is HIGH, the output is ON and can sink current.

6259

8-BIT ADDRESSABLE DMOS POWER DRIVER

INPUT tav IAS = 1.0 A IO V(BR)DSX VO VO(ON)
INPUT
tav
IAS = 1.0 A
IO
V(BR)DSX
VO
VO(ON)

TEST CIRCUITS

+15 V DUT OUT Dwg. EP-066-1 mH 0.11 Ω100
+15 V
DUT
OUT
Dwg. EP-066-1
mH 0.11 Ω100

E AS = I AS x V (BR)DSX x t AV /2

Single-Pulse Avalanche Energy Test Circuit and Waveforms

6259

8-BIT ADDRESSABLE DMOS POWER DRIVER

TERMINAL DESCRIPTIONS

Terminal No.

Terminal Name

Function

1

POWER GROUND

Reference terminal for output voltage measurements (OUT 0-3 ).

2

LOGIC SUPPLY

(V DD ) The logic supply voltage (typically 5 V).

3

S

0

Binary-coded output-select input, least-significant bit.

4

OUT 0

Current-sinking, open-drain DMOS output, address 000.

5

OUT 1

Current-sinking, open-drain DMOS output, address 001.

6

OUT 2

Current-sinking, open-drain DMOS output, address 010.

7

OUT 3

Current-sinking, open-drain DMOS output, address 011.

8

S

1

Binary-coded output-select input.

9

LOGIC GROUND

Reference terminal for input voltage measurements.

10

POWER GROUND

Reference terminal for output voltage measurements (OUT 0-3 ).

11

POWER GROUND

Reference terminal for output voltage measurements (OUT 4-7 ).

12

S

2

Binary-coded output-select input, most-significant bit.

13

ENABLE

Mode control input; see Function Table.

14

OUT 4

Current-sinking, open-drain DMOS output, address 100.

15

OUT 5

Current-sinking, open-drain DMOS output, address 101.

16

OUT 6

Current-sinking, open-drain DMOS output, address 110.

17

OUT 7

Current-sinking, open-drain DMOS output, address 111.

18

DATA

CMOS data input to the addressed output latch. When enabled, the addressed output inverts the data input (DATA = HIGH, OUTPUT = LOW).

19

CLEAR

Mode control input; see Function Table.

20

POWER GROUND

Reference terminal for output voltage measurements (OUT 4-7 ).

NOTE — Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.

6259

8-BIT ADDRESSABLE DMOS POWER DRIVER

6259 8-BIT ADDRESSABLE DMOS POWER DRIVER A6259KA Dimensions in Inches (controlling dimensions) 20 11 0.280 0.240

A6259KA

Dimensions in Inches (controlling dimensions)

20 11 0.280 0.240 1 10 0.070 0.100 0.005 0.045 BSC MIN 1.060 0.980 0.210
20
11
0.280
0.240
1
10
0.070
0.100
0.005
0.045
BSC
MIN
1.060
0.980
0.210
MAX
0.015
0.150
MIN
0.115
0.022
0.014

Dimensions in Millimeters (for reference only)

20 11 7.11 6.10 1 10 1.77 2.54 0.13 1.15 BSC MIN 26.92 24.89 5.33
20
11
7.11
6.10
1
10
1.77
2.54
0.13
1.15
BSC
MIN
26.92
24.89
5.33
MAX
0.39
3.81
MIN
2.93
0.558
0.356

0.014

0.008 0.300 BSC
0.008
0.300
BSC
0.39 3.81 MIN 2.93 0.558 0.356 0.014 0.008 0.300 BSC 0.430 MAX Dwg. MA-001-20 in 0.355

0.430

MAX

MIN 2.93 0.558 0.356 0.014 0.008 0.300 BSC 0.430 MAX Dwg. MA-001-20 in 0.355 0.204 7.62

Dwg. MA-001-20 in

0.355

0.204 7.62 BSC
0.204
7.62
BSC
BSC 0.430 MAX Dwg. MA-001-20 in 0.355 0.204 7.62 BSC 10.92 MAX Dwg. MA-001-20 mm NOTES:1.

10.92

MAX

0.430 MAX Dwg. MA-001-20 in 0.355 0.204 7.62 BSC 10.92 MAX Dwg. MA-001-20 mm NOTES:1. Exact

Dwg. MA-001-20 mm

NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Lead thickness is measured at seating plane or below.

6259

8-BIT ADDRESSABLE DMOS POWER DRIVER

A6259KLW

Dimensions in Inches (for reference only)

20 11 0.0125 0.0091 0.2992 0.419 0.2914 0.394 0.050 0.016 0.020 1 2 3 0.050
20
11
0.0125
0.0091
0.2992
0.419
0.2914
0.394
0.050
0.016
0.020
1
2
3
0.050
0.013
0.5118
BSC
0° TO 8°
0.4961
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-20 in

Dimensions in Millimeters (controlling dimensions)

20 11 7.60 7.40 0.51 1 2 3 0.33 13.00 12.60 2.65 2.35 0.10 MIN.
20
11
7.60
7.40
0.51
1 2
3
0.33
13.00
12.60
2.65
2.35
0.10 MIN.

1.27

BSC

0.32 0.23 10.65 10.00 1.27 0.40 0° TO 8°
0.32
0.23
10.65
10.00
1.27
0.40
0° TO 8°

Dwg. MA-008-20 mm

NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative.

6259

8-BIT ADDRESSABLE

DMOS POWER DRIVER

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

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