Performance Optimization of 60 nm Channel Length Vertical MOSFETs Using

Channel Engineering
G. Shrivastav, S. Mahapatra, V. Ramgopal Rao and J. Vasi
Department of Electrical Engineering, Indian Institute of Technology, Bombay-400076, India.
K. G. Anil, C. Fink, W. Hansch and I. Eisele
Fakultaet fuer Elektrotechnik, Universitaet der Bundeswehr, Muenchen, D-85577, Neubiberg, Germany

Abstract
A comprehensive study has been performed to
optimize the electrical characteristics of delta doped
channel MOSFETs (D’FETs) having channel length of
60 nm. Extensive 2D device simulations have been
employed to show that D2FETs exhibit higher drain
current drive and reduced short channel and hot carrier
effects compared to MOSFETs having uniform channel
doping. The improvement has been found significant
when the delta peak is shifted near the source end of the
channel. Device simulations show acceptable short
channel effects for 60 nm D2FETs when the gate oxide
thickness is reduced to the 2.5-3 nm regime.
Introduction
Vertical MOSFETs grown by Molecular Beam
Epitaxy (MBE) have been shown to be an attractive
option to overcome lithographic constraints in the sub
100 nm regime [l]. It has been shown that delta doped
channel MOSFETs (D’FETs), which are easily
realizable in the vertical framework exhibit superior
electrical characteristics and improved hot carrier
robustness compared to MOSFETs having uniform
channel doping [2,3]. However, the reported MBE
grown vertical MOSFETs to date have a thick gate
oxide (about 14 nm), which makes them unsuitable for
most VLSI applications. In this paper, we have
performed simulation studies to examine the extent of
improvement in the device performance as the gate
oxide thickness is scaled down. We also examine the
effect of shifting the delta peak position along the
channel on MOSFET characteristics. The electrical
performance of such D2FETs are compared with respect
to uniformly doped MOSFETs to evaluate threshold
voltage (V, ) roll-off, Drain Induced Barrier Lowering
(DIBL), drain current drive and hot carrier degradation
(HCD) for different channel lengths and oxide
thicknesses.
Device Fabrication
The complete layer sequence of source, channel
and drain of the delta doped MOSFETs was realized in
a vertical framework using MBE [1,2]. An n+ source
layer was grown first on an n+ substrate. It was followed
by the growth of the p-channel region of desired
thickness and then the n+ drain layer was grown. Mesa
islands were etched and a 14 nm high pressure gate
oxide (HIPOX) [4] was grown at 650 “C to avoid smear
out of sharp doping profiles. This oxide thickness is
currently dictated by breakdown of mesa corners where
a thinning of gate oxide was observed. The gate oxide
was covered with n+ poly-Si for metallization. After
patterning the gate, isolation layers were grown and
holes were opened for contact metallization. The
resulting device structure is shown in Fig.1 along with a
schematic of the doping profile. The channel doping for
the D’FEiTs is confined to a 20 nm delta layer
sandwiched between two intrinsic layers as shown. For
comparison, uniformly doped MOSFETs of identical
channel lengths were also fabricated. The uniformly
doped device does not have the i/p+/i sandwich, but
rather a homogenous p-channel doping. The fabricated
devices have a channel length of 60nm.
Malion kill
Figure 1: A typical D2FET along with doping profile.
Device Simulation
Device simulations were carried out using
MEDIC1 [5] by employing energy balance models. The
various parameters for the mobility models were
adjusted to match the experimental and simulated
characteristics. A typical match of experimental and
simulated output characteristics of a 60nm uniformly
doped vertical MOSFET for various gate biases is
shown in Fig. 2. It is evident that there exists a good
match between simulated and experimental data. All the
device simulations used in this paper have been carried
out using the same set of mobility parameters used for

475
$10.000 2000 IEEE
0-7695-0831-6/00
matching the experimental and simulated maximum for peak delta position nea.r the drain. Since
characteristics. for D2FETs the injection occurs over the energy barrier
As seen from Fig.2, the output characteristics do of the delta-doped region, the barrier reduction by the
not show any saturation effects, which is partly due to drain voltage is less when the delta is shifted near the
the very short channel length (60nm) of these devices. source end, which results in reduced DIBL.
Moreover the insufficient oxide thickness scaling, also 2.5
leads to a decrease in gate control and an increase in . -+- Delta at center
2 .o --O-
--o- Delta near sourm
. Delta near drain
h
1.5 - - v - U r i f o m
L
12x10 5 1.0
-E, 1.ox10
0.5
-2= 8.Ox10
6.0~10 0.0
I
II.
I.I
.II
I.I
II
4.0~10 0 2 4 6 8 101214
2.0x10 Oxide thidxness (rim)
ao Figure 3: Threshold voltage variation as a function of
ao a5 1.0 1.5 20 25
oxide thickness for 60 nm vertical MCbSFETs.
VD (VI
Figure2: Comparison of the experimental and simulated It is also evident that the DIBL reduces to an
output characteristics of a 60 nm uniformly doped acceptable value (~10%VD) as the oxide thickness is
device. reduced below 5 nm. This is true for D‘FETs with peak
delta positions at the centre and near Ithe source, and for
DIBL, resulting in the observed non- saturating output the uniformly doped devices. However, the device with
characteristics. Therefore, device simulations have been peak delta near the drain shows high ‘DIBL even at such
performed to optimize the performance of D’FETs. The low oxide thicknesses due to the proximity of the delta
simulations have been carried out for three different doped layer to the drain region.
peak delta positions along the channel for D’FETs and
for the uniformly doped MOSFETs, for various channel
lengths (L) and oxide thicknesses (Tax). The effect of L
and To,on device performance is presented in the Delta near sourc~o
following sections.
s- IOoo
+Uniform d’
Threshold Voltage and DIBL
Three D’FETs with peak of the delta at the centre,
-
$ 800
-I 600
m
at a distance of 10 nm from the source end, at a distance 0 400
of 10 nm away from the drain end, as well as a 200
uniformly doped device were simulated. The peak
0
dopings of the delta-doped devices were adjusted to get
0 2 4 6 0 101214
same threshold voltage similar to the experimental
uniformly doped device. The simulated VT values for Oxjde thickness (nm)
various oxide thicknesses for all the four devices are Figure 4: DIBL as a function of oxide thickness for 60
shown in Fig.3. It is evident that all the four devices nm vertical MOSFETs.
show identical Vr variation with oxide thickness
scaling. Further, it can be seen that the expected VT Drive currents
value of 0.2-0.3V for 60 nm channel length MOSFET is Simulations were carried out on the four above
achieved at To,= 2-3 nm. mentioned devices with To, varying from 14 nm to 1.5
The simulated DIBL for all the four devices as a nm to get the output characteristics. The D’FET with
function of oxide thickness is shown in Fig.4. DIBL is the peak of the delta near the drain has been found to
obtained by noting the VT values from simulated experience punch through at relatively small drain
transfer characteristics at drain biases of 50mV and biases. Further, as shown in the previous section, this
1.5V. It is evident that DIBL is minimum for the device device has unacceptable DIBL even at an oxide
with peak delta position near the source, while it is

476
thickness of 2.5nm, and therefore is least useful when it
comes to practical applications.
Fig. 5 shows simulated output characteristics at
two different VG - VT values for the other three devices
having an oxide thickness of 2.5 nm. It is evident that
the drain currents are the lowest for the uniformly
doped devices. For D2FET with peak of the delta near
source, the currents are marginally higher than those for
the device w$h peak of the delta at the centre.
16 x 10
.=k
Delta at the center
delta doping makes the lateral electric field more evenly
distributed in the channel. This coupled with the
reduced scattering, leads to a more sustained and higher
velocity overshoot [2], which leads to higher drain
currents in delta-doped MOSFETs. As the delta-doped
region is shifted more near the source, the field becomes
more uniformly distributed leading to still higher
velocity overshoots resulting in higher currents. Our
assertions are supported by experimentally extracted
values of average carrier velocities on devices having
L=60 nm and T,,=14 nm, as shown in the table below.
Note that the average carrier velocity for the delta-doped
device is higher by about 50%, which can explain the
higher drain currents observed in D2FETs.

Device Electron

6.5 x 10

0.0 0.5 1.0 1.5 2.0 2.5 Delta at 228 9.9 x loh
center
VD (VI
FigureS: Output characteristics at Tox=2.5nm for the
Table: Experimentally extracted values of peak carrier
three different devices having 60 nm channel length.
velocities.
Fig.6 shows the saturation drain current (Idsa,)as a
We thus see that the delta-doped devices offer a
function of oxide thickness for the above three
significant improvement in terms of the drive currents
devices. The simulations were performed at VI, = VG-
compared to the uniformly doped devices. A reduction
VT = 1.5V. The VT's were obtained at VD = 1.5V to
in the gate oxide thickness to around 2-3 nm reduces the
ensure that the VG - VT remains the same for all the
three devices. It is again evident that the currents are short channel effects, giving nearly ideal output
lowest for the uniformly doped devices. characteristics.

4 VT roll off
6.0~10
Delta at the center Fig. 7 shows the simulated VT roll off as a
4
5. Ck 10 -Delta near source function of channel length for D2FETs with the peak
-E, Uniform delta region at the centre and near the source, and for a
.
5
4.0%104

3.0~10~
uniformly doped MOSFET. The gate oxide thickness
was fixed at 1.5 nm, and the dopings were adjusted to
have identical VTS at L=250 nm.
-n 4
2.0%10 0.m I
4
1.oX10

0.0
0 2 4 6 8 1 0 1 2 1 4
Oxide thckness (nm)

Figure 6: Saturation drain current as a function of oxide

thickness for the three different devices having 60 nm
channel length. q 4.12 Delta at the centre
4.14 -0- Delta near the sourc
As seen from Fig.6, there is an improvement of at >
4.16
least 1520% in the drive currents for the delta doped
0.05 0.10 0.15 0.20 0.25
devices compared to the uniformly doped one. This can
be attributed to a reduction in scattering for most part of Channel length Cm)
the channel region where the doping is less. Further, the Figure 7: VT roll-off characteristics as a function of
channel length.

477
 The uniformly doped device shows the normal
roll-off characteristics. The roll off is suppressed for the
D’FETs, the device with peak delta near the source
showing the least roll off. For uniformly doped
MOSFETs, the reduction of net charge under the gate
and increased charge sharing by the source and drain is
responsible for the reduction in V, as the channel length
is reduced. However for the D’FETs, the charge under
the gate remains almost the same as the channel length
is reduced. This competes with the charge sharing
effects at lower channel lengths, resulting in reduced V T
roll off. Moreover for D’FET with the peak delta near
the source, the higher peak doping (to match VT at
k 2 5 0 nm) further reduces the 2D effects. This explains
the still-lesserroll off observed in such devices.
Hot Carrier Degradation
It is well known that with the reduction in
channel length below 100 nm, HCD can become a
significant factor affecting device performance. It has
been recently shown [3] that HCD is less in D’FETs
having 14 nm gate oxide with peak delta at the center of
the channel. The reason for this improvement was
attributed to reduced lateral field near the drain junction
[2,3]. In this section, we carried out simulations on
D’FET and uniformly doped MOSFET having oxide
thickness of 2.5 nm to see whether the said field
reduction persists with the reduction in oxide thickness.
The effect of shifting the position of the peak delta
towards the source is also studied.
6.0~10~
;
_ _ - - - _Delta at h e centre
4.0~10~ -Uniform
.... .... Delta near the source
2.0~10~
E
y 0.0
E
2 -2.0~10~
,.g -4.0~10~
1 a gate oxide thickness of about 2.5-3 nm will show
; optimum performance in terms of highest drive
!? -6.0~10~;
-I
-8.0~10~ I
-1 .0xlO6;
-1LJx10e: . I . , , I
Fig.8 shows the lateral electric fields for
uniformly doped MOSFETs and for D’FETs with peak
delta position at the center and near the source junction.
It is evident that peak lateral electric field near the drain
junction is less for D’FET even for reduced oxide
thickness. Moreover, the shifting of the delta-doped
region near the source causes the lateral fields to spread
out more uniformly in the channel, which further
reduces the field near the drain. Since HCD depends
478
exponentially on lateral electric field, II’FETs will show
improved hot-carrier hardness compared to the
uniformly doped device. Furthermore, this improvement
will be enhanced by shifting the delta-doping peak
towards the source end of the channel.
Conclusion
Extensive 2D device simulations have been
performed over different channel length and oxide
thicknesses to optimize the short channel and hot
carrier performance of delta-doped MC)SFETs (D’FETs)
with respect to MOSFETs having uniform channel
doping. The effect of shifting the position of the peak
delta on D’FET performance has also been studied. We
have found that oxide thickness values of about 2.5-3
nm brings down the DIBL and the threshold voltage to
acceptable limits suitable for D’FETs having 60 nm
channel length. The drain current characteristics of
such devices show near ideal behaviour. The DIBL has
been found better for D’FETs with de1l.a near the source,
compared to uniformly doped device. Higher drain
currents were observed for D’FETs for all the oxide
thicknesses used in the study, which has been attributed
to sustained velocity overshoot over a large part of the
channel. Further improvement in drain current was
found in D’FETs with delta shifted towards the source.
The D’FETs show better VT roll off compared to the
uniformly doped devices, and the device with peak delta
near the source shows hardly any roll off effect. Finally,
the lateral electric field near the drain has been found
significantly lower for D’FETs compared to uniformly
doped MOSFETs, for oxide thickness down to 2.5 nm,
especially when the delta is shifted towards the source.
This suggests better hot-carrier hardness of D’FETs
compared to uniformly doped MOSFETs. Therefore,
D’FETs with the peak delta near the s,ource and having
currents, least DIBL, most suppressed VT roll off and
least hot carrier degradation.
Acknowledgemmt
Siemens AG, Germany is acknowlediged for financial
support.
References.
[ l ] H. Gossner et. al., Electronic Lett, ~01.31,p. 1394,
1995.
[2]V. Ramgopal Rao et. al., IEDM Tech. Dig., p.8 1 1,
1997.
[3] S. Mahapatra et. al, submitted, IEEE Electron Dev.
Lett (1999).
[4] V. Ramgopal Rao et. al, Thin Solid Films, vo1.296,
p.37, 1997.
[5] MEDICI, Technology Modelling Associates Inc.,
Sunnyvale, CA, USA.