3610 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO.

7, JULY 2015

A High-Efficiency MOSFET Transformerless

Inverter for Nonisolated Microinverter Applications
Baifeng Chen, Student Member, IEEE, Bin Gu, Member, IEEE, Lanhua Zhang, Student Member, IEEE,
Zaka Ullah Zahid, Student Member, IEEE, Jih-Sheng (Jason) Lai, Fellow, IEEE, Zhiling Liao,
and Ruixiang Hao, Member, IEEE

Abstract—State-of-the-art low-power-level metal–oxide–

semiconductor field-effect transistor (MOSFET)-based trans-
formerless photovoltaic (PV) inverters can achieve high efficiency
by using latest super junction MOSFETs. However, these
MOSFET-based inverter topologies suffer from one or more of
these drawbacks: MOSFET failure risk from body diode reverse
recovery, increased conduction losses due to more devices, or low
magnetics utilization. By splitting the conventional MOSFET-
based phase leg with an optimized inductor, this paper proposes a
novel MOSFET-based phase leg configuration to minimize these Fig. 1. Two-stage nonisolated PV microinverter.
drawbacks. Based on the proposed phase leg configuration, a
high efficiency single-phase MOSFET transformerless inverter is
presented for the PV microinverter applications. The pulsewidth
modulation (PWM) modulation and circuit operation principle order to achieve high system efficiency and minimize the sys-
are then described. The common-mode and differential-mode tem common-mode (CM) voltage, the secondary stage of the
voltage model is then presented and analyzed for circuit design.
Experimental results of a 250 W hardware prototype are shown to nonisolated PV microinverter requires a high efficiency trans-
demonstrate the merits of the proposed transformerless inverter formerless inverter, which is the concentration of this paper.
on nonisolated two-stage PV microinverter application.
Index Terms—Microinverter, MOSFET inverters, photovoltaic A. State-of-the-Art Transformerless PV Inverters
(PV) inverter, transformerless inverter. In recent years, there have been quite a few new transformer-
less PV inverters topologies [1]–[5], which eliminate traditional
I. INTRODUCTION line frequency transformers to achieve lower cost and higher
efficiency, and maintain lower leakage current as well. For high-
ITH worldwide growing demand for electric energy,
W there has been a great interest in exploring photovoltaic
(PV) sources. The PV microinverter has become a popular trend
power-level transformerless inverters, most of them adopt neu-
tral point clamp (NPC) or T-type three-level inverter topologies,
which require high dc-bus voltage and are not suitable for low-
for its great flexibility in system installation and expansion,
power PV inverter application [7]–[10]. For the lower power
safety of low-input voltage, and high system-level energy har-
level transformerless inverters, most of the innovative topolo-
nessing under shading [1]–[4]. Because it is not mandatory for
gies use super junction metal–oxide–semiconductor field-effect
PV microinverters to have galvanic insulation, the nonisolated
transistor (MOSFET) to boost efficiency [1]–[5]. With super
architecture, as shown in Fig. 1, is an ideal choice for high-
junction MOSFETs, the conduction and switching losses are
efficiency design [2]–[5]. Gu et al. [6] reported a nonisolated
lowered. However, with the poor reverse recovery from MOS-
high boost ratio dc–dc converter, which boosts PV panel volt-
FET’s slow body diode, MOSFET-based phase legs will have a
age to around 380 V dc-link voltage for 240 V grid voltage
risk of device failure, which is related to high dv/dt, di/dt and
and achieves high efficiency over wide input voltage range. In
phase-leg shoot through from gating voltage false trigging on. In
the following, state-of-the-art MOSFET-based transformerless
Manuscript received April 13, 2014; revised May 30, 2014; accepted July inverter topologies will be reviewed and discussed according to
4, 2014. Date of publication July 16, 2014; date of current version February
13, 2015. This work was supported by the U.S. Department of Energy un- their circuit topology, efficiency, MOSFET failure possibility
der Award DE-EE0004681. Recommended for publication by Associate Editor from body diode reverse recovery, and magnetics utilization.
Y.-M. Chen. The first and most influential one is the Highly Efficient and
B. Chen, B. Gu, L. Zhang, Z. U. Zahid, and J.-S. Lai are with the Fu-
ture Energy Electronics Center, Virginia Tech, Blacksburg, VA 24061 USA Reliable Concept (HERIC) inverter topology [11]. As shown
(e-mail: bfchen@vt.edu; gubin@vt.edu; lhzhang@vt.edu; zuzahid@vt.edu; in Fig. 2, this circuit uses ac switches S5 /D5 (or S6 /D6 ) to
laijs@vt.edu). decouple the PV panel from the grid during the current free-
Z. Liao is with the School of Electrical and Information Engineering, Jiangsu
University, Zhenjiang 212013, China (e-mail: liaozhiling@ujs.edu.cn). wheeling period to reduce the CM voltage. Topology 2 in Fig. 3
R. Hao is with the School of Electrical Engineering, Beijing Jiaotong Uni- uses one active switch and four diodes to replace the two active
versity, Beijing 100044, China (e-mail: haorx@bjtu.edu.cn). switches at the cost of higher conduction loss on freewheeling
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. diodes [12]. Both of these two topologies have simple structure
Digital Object Identifier 10.1109/TPEL.2014.2339320 with low conduction and switching losses, but device failure risk

0885-8993 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
CHEN et al.: HIGH-EFFICIENCY MOSFET TRANSFORMERLESS INVERTER FOR NONISOLATED MICROINVERTER APPLICATIONS
Fig. 2. Topology 1: HERIC inverter.
Fig. 3. Topology 2: Topology proposed in [12].
Fig. 4. Topology 3: H5 topology of SMA.
exists in phase leg when MOSFETs are adopted. Using MOS-
FETs in H bridge (S1 toS4 ) for these topologies are prevented
for commercial products. Commercial products obtains 97.8%
peak efficiency for 5 kW inverter by using insulated gate bipo-
lar transistor (IGBT) in HERIC topology [13]. Reference [14]
uses the SiC-JFET to achieved 99% peak efficiency; however,
it suffers from the high cost of devices.
As shown in Fig. 4, H5 topology of SMA [15], which only
needs three MOSFETs and two IGBTs, decouples the PV panel
from grid with two middle IGBTs during the current free-
wheeling period. The MOSFET failure risk from body diode
reverse recovery is eliminated by splitting MOSFET phase leg
with two IGBTs. However, the conduction loss will be a little
higher than HERIC topology due to the three devices that are
in the conduction loop and fixed voltage drop of IGBTs. This
topology achieves 98.6% peak efficiency and 98% California
Energy Commission (CEC) efficiency in commercial product
SunnyBoy-8000-US-TL [16].
As shown in Fig. 5, H6 Topology uses MOSFETs to decrease
the conduction loss of IGBTs in H5 topology by splitting S5 of
H5 topology into two MOSFETs [5]. This patent-free topology
achieves 98.1% CEC efficiency under 300 W condition, but
3611
Fig. 5. Topology 4: H6 topology of [5].
Fig. 6. Topology 5: Topology proposed in [18]
Fig. 7. Topology 6: STECA topology.
needs one more active switch compared with H5 topology and
also has 3 devices in the conduction loop.
As shown in Fig. 6, reference [17] splits S5 of H5 topology
into S5 and S6 in series and operates them in high-frequency
switching, S1 −S4 in line grid line frequency switching. Draw-
backs of this inverter are higher conduction loss from four
devices in conduction loop. By switching S1 −S4 in high fre-
quency, Yang et al. [18] introduced a double-frequency modu-
lation method, which can reduce the output filter at the cost of
increasing switching loss. Drawbacks of this inverter are more
switching loss and more conduction loss (four devices in a con-
duction loop).
As shown in Fig. 7, topology 6, which has similar modulation
method with topology 5, operates S5 and S6 in high frequency
and S1 to S4 in lower frequency. With proper operation of S5 and
S6 in response to different input voltage level, system switching
loss could be optimized. This method is adopted in the commer-
cial product of StecaGrid series PV inverter and obtains 98%
peak efficiency and 97.5% CEC efficiency [19]. The drawbacks
3612
Fig. 8. Topology 7: Reversed dual boost inverter of SMA.
Fig. 9. Topology 8: Dual buck inverter of Xantrex technology.
of this topology are still too many switches and high conduction
loss (four devices in conduction loop).
Another reversed dual boost inverter [20], which is patented
by SMA, uses hybrid unipolar modulation (S1 and S2 in high-
frequency and S3 and S4 in low-frequency switching), and
achieves 99% peak efficiency [21]. As shown in Fig. 8, the
two filter inductors (Li1 and Li2 ) only conduct positive or neg-
ative current for the half of line cycle, and the switches S3 and
S4 need to be connected to the grid directly for low CM volt-
age. This inverter pays for its extra high efficiency with 50%
magnetic utilization and shoot through risk of the grid voltage
by S3 and S4 .
B. High-Reliability MOSFET Inverter Topology
The dual buck inverter [22], which is patented by Xantrex
Technology Inc, provides another way for high-reliability and
high-efficiency MOSFET inverter design. As shown in Fig. 9,
the dual buck inverter uses four output filter inductors to split the
MOSFET phase legs and also needs to use bipolar modulation
to minimize the CM voltage for a transformerless inverter appli-
cation [23], [24]. Thus, this inverter pays for its high reliability
with lower efficiency and 50% magnetic utilization.
Gu et al. [25] present a 99% CEC efficiency and high-
reliability transformerless PV inverter, which is shown in
Fig. 10. Similar to the dual buck inverter, this topology also
splits the MOSFET phase legs with filter inductors, but with
a pair of ac switches, this inverter can work with the unipolar
pulsewidth modulation (PWM) to improve system efficiency.
Due to each filter inductor only conducting half-line cycle cur-
rent, the high efficiency and high reliability come at the cost of
only 50% magnetic utilization.
In summary, state-of-the-art MOSFET transformerless invert-
ers have tradeoffs in one or more of the following: MOSFET
body diode reverse recovery risk, increased conduction losses
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 7, JULY 2015
Fig. 10. Topology 9: Topology proposed in [25].
Fig. 11. MOSFET phase leg configurations: (a) traditional phase leg, (b) H5
inverter method, (c) dual buck method, and (d) proposed method.
due to more devices, and low magnetic utilization. In Section
II of this paper, based on a novel MOSFET phase leg, a high
efficiency and high magnetics utilization transformerless in-
verter without MOSFET body diode reverse recovery risk will
be proposed. PWM modulation and operating modes of the pro-
posed transformerless inverter will be presented in Section III.
Differential-mode (DM) and CM voltage model will be pre-
sented and analyzed in Section IV to minimize the CM voltage.
Component selection and loss calculation will be presented in
Section V. Experimental result and tested efficiency will be
shown in Section VI.
II. PROPOSED TRANSFORMERLESS INVERTER
A. Proposed MOSFET-Based Phase Leg
Traditional MOSFET-based phase leg has a risk of MOSFET
failure, which is related to high dv/dt, high di/dt, overvoltage
of gating voltage, and phase leg shoot through by false trigging
on during the body diode reverse recovery and is normally not
suggested for high-voltage hard-switching applications [26]–
[29]. Fig. 11(a) shows the traditional MOSFET phase leg. By
splitting the MOSFET phase legs with IGBTs, as shown in
Fig. 11(b), H5 inverter and other similar topologies minimize
CHEN et al.: HIGH-EFFICIENCY MOSFET TRANSFORMERLESS INVERTER FOR NONISOLATED MICROINVERTER APPLICATIONS 3613

Fig. 12. Double pulse test of the body diode reverse recovery.

the MOSFET body diode reverse recovery issues. However,

this method introduces another voltage drop in the conduction
loop. As shown in Fig. 11(c), by splitting the MOSFET phase
leg into independent buck converters and boost converters with
filter inductors, dual buck inverter disables the MOSFET body
diodes. However, the magnetics are only 50% utilized.
Considering the MOSFET body diode reverse recovery risk
in Fig. 11(a), additional IGBTs conduction loss in Fig. 11(b),
and 50% magnetics utilization in Fig. 11(c), an improved circuit
is proposed in Fig. 11(d). The basic idea of the proposed method
is splitting the traditional MOSFET phase leg with a small
phase-leg splitting inductor, which serves two functions: the
first function is disabling the MOSFET body diode by splitting
the phase leg into an independent buck converter and boost con-
verter under normal working conditions, and the second func-
tion is protecting MOSFETs by minimizing the di/dt and dv/dt
even when an unexpected MOSFET body diode reverse recov-
ery happens under abnormal conditions [30]. The design of this
phase-leg splitting inductor will be based on when MOSFET
body diodes have reverse recovery under abnormal conditions,
which can be output current is not well controlled in phase with Fig. 13. Diode reverse recovery of IPB60R099C6 in (a) traditional phase leg
grid voltage or sudden disturbance from grid side or dc input and (b) proposed phase leg.
side.
In order to verify the proposed MOSFET-based phase leg
circuit under MOSFET body diode reverse recovery, two sim- turn on and turn off, respectively. In this case, MOSFET failure
ulations are done in the SIMetrix by using the PSpice model will happen.
of IPB60R099C6 [31]. The simulation adopts the double pulse The second simulation uses the proposed phase leg with added
method for device testing [32], which is shown in Fig. 12. The phase-leg splitting inductor shown in Fig. 11(d). With a 38 μH
dc voltage is 380 V, the inductor value is 4.5 mH, and the gating inductor, the di/dt of the reverse current is only 10 A/μs, and
resistor is 4 Ω. In order to study the di/dt effect on gating voltage, the peak reverse recovery current is less than 2.8 A under the
a 5 nH common source inductance LCSI , which comes from the same 0.7 A load current condition, as shown in Fig. 13(b). The
device lead and the printed circuit board trace, is introduced in false turn on and shoot through failure are avoided in this case.
the circuit [33], [34]. By turning on the bottom MOSFET, the The selection criteria of phase-leg splitting inductor will be
inductor current will be charged to about 0.7 A. Then by turning discussed in Section V-A.
off the bottom MOSFET, the inductor current will be forced
to conduct through the top MOSFET’s body diode. When the
bottom MOSFET is turned on again, the top MOSFET’s body B. Proposed Transformerless Inverter with Proposed
Phase Leg
diode will have a forced reverse recovery.
The first simulation uses the phase leg shown in Fig. 11(a) Based on the proposed MOSFET phase leg method in
to study the MOSFET body diode reverse recovery effect. The Fig. 11(d), this paper proposes a novel high efficiency MOSFET
waveforms during the forced reverse recovery are shown in transformerless inverter. The diagram of proposed transformer-
Fig. 13(a). The peak reverse recovery current is about 27.5 A less inverter with separated magnetics and integrated magnetics
under 0.7 A load current condition, and the di/dt of the recovery are shown in Fig. 14(a) and (b), respectively.
current is more than 1000 A/μs. Both gate voltages see more S1 , S2 , D1 , D2 , and Lo1 make up one proposed phase leg and
than 40 V, and both top and bottom MOSFETs experience false S3 , S4 , D3 , D4 , and Lo4 make up another proposed phase leg;
3614 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 7, JULY 2015

Fig. 15. PWM implemented circuit for the proposed inverter.

Fig. 14. Proposed transformerless inverter topology with (a) separated mag-
netics and (b) integrated magnetics.

S5 and D5 provide a freewheeling loop for positive current; S6

and D6 provide a freewheeling loop for negative current. Phase-
leg splitting inductors Lo1 and Lo4 can be coupled together and
filter inductors Lo2 and Lo3 can be coupled together.
The phase-leg splitting inductors Lo1 and Lo4 have 50% uti-
lization, but the filter inductors Lo2 and Lo3 have full utilization
(will be shown in Section III). As discussed in Section II-A,
the phase-leg splitting inductors Lo1 and Lo4 are only designed
for di/dt suppression with a value much smaller than the fil-
ter inductance. In this paper, the total inductance of phase-leg
splitting inductor is 86 μH, and the filter inductors Lo2 and Lo3 Fig. 16. PWM signals in time domain for the proposed inverter.
are 4.7 mH (will be shown in Section V-A). So even though
the phase-leg splitting inductors only have 50% utilization, the
overall inductance utilization is over 98%. Compared with in-
and the output signals are used to drive devices S2 and S3 , which
verter topologies in Figs. 8–10 whose magnetics only have 50%
are switched simultaneously in high frequency; S6 is turned on
utilization, the proposed inverter almost achieves almost full uti-
and operates as a polarity selection in grid line frequency. As
lization of magnetics. Thus, the cost and volume of magnetics
one MOSFET is switching in high frequency, the other com-
can almost be reduced by half. In addition, the proposed in-
plimentary MOSFET in phase leg is in off state, so all PWM
verter still does not need PWM dead-time, only has two devices
signals do not need dead time. This means duty cycle utilization
in the conduction loss, and has no risk from reverse recovery of
is 100%.
MOSFET body diodes.
Fig. 17 shows the four operating modes in one grid cycle
for the proposed inverter. In the positive half-line grid cycle,
III. PWM METHOD AND OPERATING MODES S1 and S4 are switched synchronously in high-frequency PWM
Fig. 15 shows the PWM implementation circuit scheme for modulation; S5 is turned on. As shown in Fig. 17(a), when S1
the proposed transformerless inverter. Fig. 16 shows the PWM and S4 are turned on, D5 is reverse-biased, the output current
signals in time domain. In the positive half grid cycle, voltage goes through S1 and S4 . As shown in Fig. 17(b), when S1 and
reference signal Vref is compared with the carrier signal Vcarrier , S4 are turned off, D5 is forward-biased and the freewheeling
and the output signal is used to drive the devices S1 and S4 , current goes through S5 and D5 . In the positive half-line cycle,
which are switched simultaneously in high frequency; voltage both filter and phase-leg splitting inductors conduct current.
reference signal Vref is compared with 0 and outputs a high- Similarly, in the negative half-line cycle, S2 and S3 are
level signal to turn on S5 in the entire positive grid cycle, which switched synchronously in the high-frequency PWM modula-
operates as a polarity selection in grid line frequency. tion; S6 is turned on. As shown in Fig. 17(c), when S2 and S3
In the negative half grid cycle, the inverse signal of voltage are turned on, D6 is reverse-biased, the output current goes
reference Vref inv is compared with the carrier signal Vcarrier , through S2 and S3 . As shown in Fig. 17(d), when S2 and
CHEN et al.: HIGH-EFFICIENCY MOSFET TRANSFORMERLESS INVERTER FOR NONISOLATED MICROINVERTER APPLICATIONS
Fig. 17. Operating modes of the proposed transformerless inverter: (a) positive
half-line cycle, S 1 and S 4 are on, (b) positive half-line cycle, S 1 and S 4 are off,
free-wheeling current goes through S 5 and D 5 , (c) negative half-line cycle, S 3
and S 2 are on, and (d) negative half-line cycle, S 3 and S 2 are off, free-wheeling
current goes through S 6 and D 6 .
S3 are turned off, D6 is forward-biased and the freewheeling
current goes through S6 and D6 . In the negative half-line cycle,
phase-leg splitting inductors do not need to conduct. Therefore,
the phase-leg splitting inductors have 50% utilization, but filter
inductors are fully utilized.
IV. COMMON MODE AND DM VOLTAGE ANALYSIS
In the transformerless PV inverter system, a galvanic connec-
tion between the ground of the grid and the PV array exists. The
PV mental frame is normally grounded. If the high-frequency
CM voltage and DM voltage are not well controlled, a high-
frequency leakage current will go to the ground through the
parasitic capacitance of PV array (CG −PV ), which is formed
between the PV array terminals and the frame [35]–[40]. The
3615
Fig. 18. Proposed inverter system with EMI filters and parasitic components.
Fig. 19. Simplified circuit with CM and DM model during the positive half-
line grid cycle.
requirements for limiting ground loop leakage current and fault
current can be referred to VDE0126-1-1 [41], [42].
The system diagram of the proposed transformerless PV in-
verter with electromagnetic interference (EMI) filters and par-
asitic components is shown in Fig. 18. This paper will analyze
DM and CM voltage between the ground of grid (point E in
Fig. 18) and the PV cells (point G in Fig. 18), which will be re-
ferred as VE G . Zg represent other parasitic CM impedance; Cf
is the differential capacitor; LCM is the CM inductor; CY 1 and
CY 2 are the CM capacitors. The voltage VE G not only depends
on the CM and DM voltage in the circuit but also depends on
the inverter operating modes and the component parameters.
During the positive half cycle, the output terminals of the
switch phase legs are V1 and V4 , respectively. The diagram of
the simplified circuit with CM and DM model during the positive
half-line grid cycle is shown in Fig. 19.
When S1 and S4 are turned on, V1 equals to Vdc , V4 equals to
zero if G is set as zero reference. According to the definition of
CM voltage and DM voltage, the CM and DM voltages in the
positive half cycle are
V1 + V4 Vdc
VCM −P on = = (1)
2 2
VDM −P on = V1 − V4 = Vdc . (2)
As shown in Fig. 19, the voltage VE G has three components.
The first one is from the DM voltage of the switch phase legs,
the second one is from the DM voltage of the grid voltage Vac ,
and the third one is from the CM voltage of the switch phase
legs. The voltage VE G in the positive line cycle with switches
3616 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 7, JULY 2015

(VDM −N on + Vac ) · Lo3

−
Lo2 + Lo3
(Vdc + Vac ) · Lo3
= Vdc − . (9)
Lo2 + Lo3
As shown in Fig. 17(d), in the negative half-line grid cycle,
when S2 and S3 are turned off, the free-wheeling current goes
through S6 and D6 . The CM and DM voltages in the circuit are
V3 +V2 Vdc
VCM −N off = = (10)
2 2
Fig. 20. Simplified CM and DM model during negative half-line grid cycle. VDM −N off = V3 − V2 = 0. (11)
The voltage VE G in the negative line cycle with switches S2
and S3 off is given as shown
on is given as shown
VEG−N off = VCM −N off + 0.5 VDM −N off
VEG−P = VV 4−G + VE −V 4
on
(VDM −N off − Vac ) · Lo3
+
= VCM −P on − 0.5 VDM −P on Lo2 +Lo3
(VDM −P on − Vac ) · (Lo3 + Lo4 ) −Vac · Lo3
+ = 0.5 Vdc + . (12)
Lo1 + Lo2 + Lo3 + Lo4 Lo2 +Lo3
(Vdc − Vac ) · (Lo3 + Lo4 ) In the proposed inverter, if the inductance Lo2 and Lo3 have
= . (3) the same value and Lo1 and Lo4 have the same value, VE G
Lo1 + Lo2 + Lo3 + Lo4
comes out to be the same in four different operating modes
As shown in Fig. 17(b), in the positive half-line grid cycle, according to (3), (6), (9), and (12), that is
when S1 and S4 are turned off, the free-wheeling current goes
through S5 and D5 . The CM and DM voltages in the circuit are VEG−P on = VEG−P off = VEG−N on

V1 +V4 Vdc Vdc − Vac

VCM −P = = (4) = VEG−N off = . (13)
off
2 2 2
VDM −P = V1 − V4 = 0. (5) If the phase-leg splitting inductors (Lo1 and Lo4 ) or filter
off
inductors (Lo2 and Lo3 ) are not symmetrically designed, the
The voltage VE G in the positive line cycle with switches S1 DM and CM voltages will bring high-frequency voltage to VE G .
and S4 off is given as shown In order to minimize the high-frequency leakage current, Lo2
and Lo3 are designed with one coupled inductor, Lo1 and Lo4
VEG−P off = VCM −P off − 0.5 VDM −P off
are designed with another coupled inductor, which allows a
(VDM −P off − Vac ) · (Lo3 + Lo4 ) better matching between Lo2 and Lo3 and between Lo1 and
+
Lo1 +Lo2 +Lo3 +Lo4 Lo4 . As a result, the voltage VE G will be a line frequency
−Vac · (Lo3 +Lo4 ) sinusoidal voltage with a dc offset, which is shown in (13).
= 0.5 Vdc + . (6) The experimental VE G waveform will be shown in Section VI,
Lo1 +Lo2 +Lo3 +Lo4
which should verify the validity of the analysis in this section.
During the negative half cycle, the output terminals of switch
phase legs are V2 and V3 , respectively. The diagram of the V. COMPONENT SELECTION AND LOSS ANALYSIS
simplified circuit with CM and DM model during the negative
A. Output LC Filter Design
half-line grid cycle is shown in Fig. 20. When S2 and S3 are
turned on, V3 equals to Vdc , V2 equals to zero if G is set as zero 1) Filter Inductor: The output filter of this inverter design
reference. is based on the maximum ripple current. As shown in (14), the
When the S2 and S3 are turned on, the CM and DM voltage maximum ripple current is usually designed to be around 10%
are to 30% of rated current, which is about 1.04 A (1.47 A peak
V3 +V2 Vdc value) for 240 V output voltage and 250 W rated output power.
VCM −N on = = (7) The ripple current is a function of dc voltage, ac grid voltage,
2 2
filter inductor value, and PWM turn on time, which is presented
VDM −N on = V3 − V2 = Vdc . (8) in (15)
The voltage VE G in the negative line cycle with switches S2 Δiripple−m ax ≤ (10% ∼ 30%) · Irated (14)
and S3 on is given as shown
Vdc − Vac Vdc − D · Vdc D
VEG−N = VV 3−G + VE −V 3 2Δiripple = · Ton = · .
on Lfilter Lfilter fsw
= VCM −N on + 0.5 VDM −N on (15)
CHEN et al.: HIGH-EFFICIENCY MOSFET TRANSFORMERLESS INVERTER FOR NONISOLATED MICROINVERTER APPLICATIONS
The proposed inverter is designed to work at 30 kHz switching
frequency, and the inverter output filter inductor is designed
to have 25% maximum current ripple, which is 0.37 A. The
maximum current ripple happens at duty cycles equals to 0.5.
Through (15), the output filter inductance is calculated to be
4.3 mH.
RM 14 low profile magnetic cores with N95 ferrite material
from EPCOS are selected for the output filter [43]. Proper gap
lgap is used to prevent the maximum flux density Bm ax from sat-
urating under the maximum current condition. The relationship
of maximum flux density with turns N, maximum current Im ax ,
and gap is shown in (16). The relationship between inductance
value Lfilter and gap distance is shown in (17). Finally, 4.7 mH
inductance is achieved through 91 turns, which can achieve 23%
maximum current ripple
N · Im ax
Bm ax ∼
= (16)
lgap /u0
N2 N2
Lfilter = ∼
= . (17)
(lgap /u0 Ae ) + (le /ui Ae ) lgap /u0 Ae
2) Filter Capacitor: The filter capacitor design is based on
the cutoff frequency of the output filter, which is usually around
10% to 20% of the switching frequency, the selection of filter
capacitor can follow (18). The 0.47 μF capacitor is selected as
the output filter capacitor for the 30 kHz switching frequency
in proposed inverter, which achieves 3.4 kHz cutoff frequency
with the filter inductor
1 vds = i · Rds
√ ≤ (10% − 20%) × fsw . (18)
2π Lfilter · Cfilter
3) Phase-Leg Splitting Inductor: As mentioned in the Sec-
tion II, the design of phase-leg splitting inductor L01 and L04
should be based on the worst condition. The worst condition is
when the top MOSFET S1 and bottom MOSFET S2 have a hard
commutation through L01 .
The design criterion of phase-leg splitting inductor is mainly
to set the limit of the di/dt for the MOSFET body diode re-
verse recovery current under abnormal conditions to avoid false
turn on and partial shoot through. For the selected MOSFET
IPB60R099C6 [31], as shown in Fig. 13(b), the gate plateau
voltage is around 5.4 V, therefore, the phase-leg splitting in-
ductor should be large enough to ensure the gating spike or
noise voltage well below the plateau voltage. In this paper, a
peak gating voltage of 2.7 V is selected as the design target for
100% margin. To achieve this target, one can perform the circuit
simulation with actual device model or through try-and-error ex-
periments. This paper uses PSpice model of IPB60R099C6 in
SIMetrix circuit simulator with the double pulse simulation to
determine the di/dt that limits the peak gating spike or noise
voltage to below 2.7 V. Simulation results in Fig. 13(b) indicate
that di/dt should be less than 10 A/μs to achieve the design
target. Thus, the minimum value of phase-leg splitting inductor
Lm in can be formulated as follows:
ΔV Vdc
L= = (19)
Δi/Δt Δi/Δt
3617
Vdc
Lm in ≥ . (20)
di/dt|m ax
With 10 A/μs as the maximum di/dt limit, the minimum
inductor comes out to be 38 μH for 380 Vdc through (20).
The final implementation adopts two molypermalloy powder
cores (#55035) in stack, which yields 43 μH inductance with 16
turns for each phase-lag splitting inductor.
B. MOSFETs and Diodes Selection
During the normal condition, four diodes D1 to D4 only
serve as the clamping diodes and they do not conduct current.
MURA160T3G (600 V, 2 A; surface mount package DO-214)
is chosen for these clamping diodes. Diodes D5 and D6 need
to conduct the freewheeling current and withstand the hard
commutating when S1 −S4 (or S2 and S3 ) are turned on. C3
D1 0060G (600 V, SiC diode), which has no reverse recovery
loss during C3D10060G switching, is chosen for D5 and D6 .
For all main devices, S1 −S6 , IPB60R099C6 is selected.
C. Power Loss Calculation
The losses in the power circuit can be divided into the conduc-
tion loss (power device conduction loss and inductor conduction
loss), switching loss, and inductor core loss.
1) Conduction Loss: The voltage drop of MOSFETs can be
simplified as a channel resistor, the voltage drop of diodes can
be simplified as a voltage source series with a channel resistor,
which are shown in (21) and (22), respectively
(21)
vak = Vf + i · Rak . (22)
For the positive half cycle, the duty cycle of S1 and S4 can
be expressed as (23). The duty cycle of the MOSFET S5 can be
expressed as (24). The power losses on S2 , S3 , and S6 in the
negative half cycle are the same due to the symmetric operation
modes
dS 1 S 4 = m · sin(ωt) (23)
dS 5 = 1 − m · sin(ωt). (24)
Assuming the output current is in phase with the duty cycle,
which means the pure active generation condition, the output
current can be expressed as
i(t) = Im · sin(ωt). (25)
The current in the power device is PWM current, whose con-
duction time depends on the duty cycle condition. All the power
devices will only work for half of the line cycle, the conduction
losses on high-frequency MOSFETs (S1 toS4 ), line frequency
MOSFETs (S5 , S6 ), and freewheeling Diodes (D5 , D6 ) are
given in (26), (27), and (28). The total conduction loss of all
devices is given in (29)
 π
1
PH ig h Fre q u e n c y M O SFET = i(t) · vd s (t) · da c tive (t) · d(ωt)
2π 0
2M
2
= Im · Rd s · (26)
3π
3618 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 7, JULY 2015

 π
1
PL ow Fre q u e n c y M O SFET = i(t) · vd s (t) · dz e ro (t) · d(ωt)
2π 0
 
2 1 2M
= Im · R d s · − (27)
4 3π
 π
1
PD io d e = i(t) · va k (t)
2π 0

× (1 − M sin(ωt)) · d(ωt)
 
1 M
= Im · V f · −
π 4
 
1 2M
2
+ Im · Ra k · − (28)
4 3π
Pc o n d = 4PH ig h Fre q u e n c y M O SFET + 2PD io d e
+ 2PL ow Fre q u e n c y M O SFET

2M Fig. 21. Calculated individual power loss under different power levels.
2
= 4Im · Rd s
3π
 
1 M
+ 2Im · Vf · − The second step is calculating the core loss density PL . The
π 4
  core loss density is a function of the ac flux swing and frequency.
1 2M It can be approximated from the core loss charts or the curve
2
+ 2Im · Ra k · −
4 3π fit loss (35) (a, b, and c are constants determined from curve
 
1 2M fitting)
2
+ 2Im · Rd s · − . (29)
4 3π PL = aΔB b f c . (35)
The conduction loss in the inductor can be divided in to the EPCOS’s N95 ferrite materials provides the chart of rela-
line frequency current conduction loss which is related to the tive core losses versus ac field flux density [43]. Then the core
dc resistance RL dc , and the switching frequency current ripple loss can be calculated though core cross section Ae and core
conduction loss which is related to the switching frequency ac magnetic path length Ie
resistance RL ac . The total conduction losses are
Pcore = PL · Ie · Ae . (36)
Pcon L = 0.5 · Im
2
· RL dc + If2 ac · RL ac . (30)
As the CEC efficiency is weighted efficiency calculated at
2) Switching Loss: The hard commutating device is the SiC 10%, 20%, 30%, 50%, 75%, and 100% of the full power level
diode when MOSFET is turned on, so there is no reverse recov- [25]. The power losses of the proposed inverter are calculated at
ery loss. The switching losses of the high-frequency MOSFETs 10%, 20%, 30%, 50%, 75%, and 100% of the full power level
(S1 toS4 ) only have the voltage and current overlap losses and at 250 W, and individual power losses under different power
the gating charge losses [44], which can be estimated through levels are shown in the Fig. 21. The calculated total loss under
(31) and (32) respectively different power levels and related system efficiency are shown
 ton+tr in Fig. 22.
PS W M OS = fsw · id (t) · vds (t) · dt
ton
 VI. EXPERIMENTAL RESULTS
toff +tf
+ fsw · id (t) · vds (t) · dt A 250 W microinverter hardware prototype with 380 V dc
toff input and 240 V ac output has been designed, fabricated and
tr + tf tested in the two stage nonisolated microinverter to verify the
= fsw · Ids · Vds · (31)
2 validity of the proposed high efficiency MOSFET transformer-
Pg = fsw · Qg · Vgate . (32) less inverter. The prototype of the two-stage nonisolated mi-
croinverter is shown in Fig. 23, which can be divided into the
The power losses of D5 and D6 only have capacitor charging high boost ratio nonisolated dc–dc converter and the proposed
and discharging losses [44], which can be estimated through transformerless inverter.
2 As shown in Fig. 17, Phase-leg splitting inductors only con-
PS W · fsw · Coss · Voff
Diode = 2
. (33) duct in positive half-line cycle and have 50% utilization, but
3
filter inductors have full utilization. Compared with filter in-
3) Core Loss: Due to the gap in the ferrite core, the first step
ductors, the phase-leg splitting inductors are much smaller. The
of the core loss calculation is calculating the ac flux swing
output filter inductor is 4.7 mH with the weight 90 g, the phase-
N · ΔI leg splitting inductor is 0.086 mH in total with the weight 4 g.
ΔB ∼
= . (34)
lgap /u0 Compared with transformerless MOSFET inverter topologies
CHEN et al.: HIGH-EFFICIENCY MOSFET TRANSFORMERLESS INVERTER FOR NONISOLATED MICROINVERTER APPLICATIONS 3619

Fig. 24. Output voltage and current waveforms.

Fig. 22. Calculated total loss and efficiency under different power levels.

Fig. 25. PWM gate signals waveforms.

Fig. 23. Two-hundred-fifty-watt two-stage nonisolated microinverter hard-

ware prototype.

in Figs. 8–10 [21], [22], [25], which only have 50% utilization
of magnetics, the proposed transformerless MOSFET inverter
has 98% utilization of inductance value and 96% utilization of
weight.
The output voltage and current waveforms of the proposed
inverter are shown in Fig. 24. As there is no dead-time require-
ment for each PWM switching cycle, the proposed inverter has
no duty cycle loss, which means 340 V dc bus can almost gen-
erate 240 V ac sinusoid voltage. Fig. 26. Inverter splitting inductor current waveform.
Fig. 25 shows the gating signals for all switches. In the posi-
tive half cycle, S1 and S4 are switched simultaneously in high-
frequency PWM and S5 is always on; other switches are always
off. In the negative half cycle S2 and S3 are switched simul- frequency voltage on the PV parasitic capacitor, which means
taneously in high-frequency PWM and S6 is always on; other minimized leakage current.
switches are always off. In the experiment, YOKOGAWA WT1600 digital power me-
As shown in Fig. 26, the splitting inductors L01 and L04 only ter is used to measure voltages, currents, and efficiency. The test
conduct current in the positive half cycle. The voltage between efficiency and the calculated efficiency of proposed inverter are
dc bus negative G and ac grid ground E (VE G ) is shown in shown in Fig. 28, which shows 99.01% peak efficiency at full
Fig. 27, which has a 60 Hz grid voltage component and a dc load 250 W. The CEC efficiency is a weighted efficiency calcu-
bias component. The waveform of VE G matches well with the lated at 10%, 20%, 30%, 50%, 75%, and 100% of the full power
calculation results in the (12). This indicates nearly zero high- level [25]. The overall CEC efficiency of proposed inverter is
3620
Fig. 27. Waveforms of voltage between grid ground and DC ground (V E G ).
Fig. 28. Efficiency test results of 250 W proposed inverter.
98.8%, which is calculated through
ηCEC = 0.04η10% + 0.05η20% + 0.12η30%
+ 0.21η50% + 0.53η75% + 0.05η100% (37)
VII. CONCLUSION
This paper proposes a MOSFET transformerless inverter with
a novel MOSFET-based phase leg, which achieves:
1) high efficiency by using super junction MOSFETs and
SiC diodes;
2) minimized risks from the MOSFET phase leg by split-
ting the MOSFET phase leg with optimized inductor and
minimizing the di/dt from MOSFET body diode reverse
recovery;
3) high magnetics utilization compared with previous high
efficiency MOSFET transformerless inverters in [21],
[22], [25], which only have 50% magnetics utilization.
The proposed transformerless inverter has no dead-time re-
quirement, simple PWM modulation for implementation, and
minimized high-frequency CM issue. A 250 W hardware proto-
type has been designed, fabricated, and tested in two-stage non-
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 7, JULY 2015
isolated microinverter application. Experimental results demon-
strate that the proposed MOSFET transformerless inverter
achieves 99.01% peak efficiency at full load condition and
98.8% CEC efficiency and also achieves around 98% magnetic
utilization. Due to the advantages of high efficiency, low CM
voltage, and improved magnetic utilization, the proposed topol-
ogy is attractive for two-stage nonisolated PV microinverter
applications and transformerless string inverter applications.
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Baifeng Chen(S’11) received the B.S. degree in hy-
dropower and digital engineering from Huazhong
University of Science and Technology, Wuhan,
China, in 2008, and the M.S. degree in electrical en-
gineering from Wuhan University, Wuhan, in 2010.
He is currently working toward the Ph.D. degree in
Future Energy Electronics Center (FEEC), Virginia
Tech, Blacksburg, USA.
Since 2010, he has been a Graduate Research
Assistant in FEEC. His current research interests in-
clude design high-efficiency inverters and converter
with wide bandgap power devices and their application in photovoltaic system,
battery charger, and motor driver.
Bin Gu (S’11–M’14) received the B.S. degree from
Northeast Dianli University, Jilin, China, in 2002,
the M.S. degree from Zhejiang University, Zhejiang,
China, in 2005, and the Ph.D. degree from Virginia
Polytechnic Institute and State University, Blacks-
burg, VA, USA, in 2013, all in electrical engineering.
He was with Shanghai Kinway Technologies, Inc.,
from 2005 to 2008, and ABB Robotics Research Cen-
ter, Shanghai, from 2008 to 2009, where he was in-
volved in developing HEV and industrial power elec-
tronics drives. He is currently with Texas Instruments,
Santa Clara, USA, as a System/Applications Engineer in GaN thrust group. He
is the author or coauthor of more than 30 technical articles published in various
IEEE journals and conferences. His current research interests include design
and control of high efficiency, high power density power converters using GaN
power devices for telecom infrastructure, photovoltaic, consumer, and electric
vehicle applications.
Lanhua Zhang (S’12) received the B.S. and the M.S.
degrees, both in electrical engineering, from Shan-
dong University, Jinan, China, in 2009 and 2012, re-
spectively. He is currently working toward the Ph.D.
degree in Future Energy Electronics Center (FEEC),
Virginia Tech, Blacksburg, VA, USA.
Since 2012, he has been a Graduate Research
Assistant with FEEC. His current research interests
include soft-switching inverter for renewable energy
application, high-efficient dc/dc converter, and non-
linear current control technology.
Zaka Ullah Zahid (S’13) received the B.S. degree
in electrical and electronics engineering from NWFP
University of Engineering and Technology (UET),
Peshawar, Pakistan, in 2007, and the M.S. degree in
electrical engineering from George Washington Uni-
versity (GWU), Washington DC, USA, in 2009. He is
currently working toward the Ph.D. degree in electri-
cal engineering at Virginia Polytechnic Institute and
State University, Blacksburg, VA, USA.
Since 2011, he has been a Graduate Research
Assistant at the Future Energy Electronics Center
(FEEC), Virginia Tech. His current research interests include design and control
of transformer isolated dc–dc converters for battery charging and vehicle-to-grid
applications.
3622
Jih-Sheng (Jason) Lai (S’85–M’89–SM’93–F’07)
received the M.S. and Ph.D. degrees in electrical engi-
neering from the University of Tennessee, Knoxville,
TN, USA, in 1985 and 1989, respectively.
From 1980 to 1983, he was the Head of the
Electrical Engineering Department of the Ming-Chi
Institute of Technology, New Taipei City, Taiwan,
where he initiated a power electronics program and
received a grant from his college and a fellowship
from the National Science Council to study abroad.
In 1986, he became a Staff Member at the University
of Tennessee, where he was involved in teaching control systems and energy
conversion courses. In 1989, he joined the Electric Power Research Institute
(EPRI) Power Electronics Applications Center (PEAC), where he managed
EPRI-sponsored power electronics research projects. From 1993, he was with
the Oak Ridge National Laboratory as the Power Electronics Lead Scientist,
where he initiated a high-power electronics program and developed several
novel high power converters, including multilevel converters and soft-switching
inverters. In 1996, he joined Virginia Polytechnic Institute and State University.
He is currently the James S. Tucker Professor and the Director of the Future
Energy Electronics Center (FEEC), Virginia Tech, Blacksburg, USA. His cur-
rent research interests include high-efficiency power electronics conversions for
high-power energy applications. He has authored or coauthored more than 265
technical papers and 2 books and received 20 U.S. patents.
Dr. Lai was the recipient of several distinctive awards, including a Technical
Achievement Award in Lockheed Martin Award Night, three IEEE IAS Confer-
ence Paper Awards, Best Paper Awards from IECON-97, IPEC-05, and PCC-07.
His student teams won three awards from future energy challenge competitions
and the first place award from TI Enginous Prize Analog Design Competi-
tion. He chaired the 2000 IEEE Workshop on Computers in Power Electronics
(COMPEL 2000), 2001 IEEE/DOE Future Energy Challenge, and 2005 IEEE
Applied Power Electronics Conference and Exposition (APEC 2005).
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 7, JULY 2015
Zhiling Liao received the B.S. and M.S. degrees
in electrical engineering from Jiangsu University,
Zhenjiang, China, in 1996 and 2003, respectively,
and the Ph.D. degree in electrical engineering from
Nanjing University of Aeronautics and Astronautics
(NUAA), Nanjing, China, in 2008.
He is currently a Professor in Jiangsu University.
His current research interests include high-efficiency
inverters for photovoltaic power systems and grid-
connected inverter control. He has authored or coau-
thored more than 40 technical papers in journals and
conferences.
Ruixiang Hao (M’14) received the B.S. and Ph. D.
degrees in electrical engineering from Hebei Univer-
sity of Technology, Tianjin, China, in 1999 and 2004,
respectively.
He is currently an Associate Professor in Bei-
jing Jiaotong University, Beijing, China. His current
research interests include high-efficiency dc/dc and
dc/ac converter control and design.