International Journal of Electronics

ISSN: 0020-7217 (Print) 1362-3060 (Online) Journal homepage: https://www.tandfonline.com/loi/tetn20

A Simple and Versatile Overcurrent Protection

Circuit for Power MOSFETs

Praveen V. Pol, Sanjaykumar L. Patil & Sanjeev Kumar Pandey

To cite this article: Praveen V. Pol, Sanjaykumar L. Patil & Sanjeev Kumar Pandey (2019): A
Simple and Versatile Overcurrent Protection Circuit for Power MOSFETs, International Journal of
Electronics, DOI: 10.1080/00207217.2019.1625973

To link to this article: https://doi.org/10.1080/00207217.2019.1625973

Accepted author version posted online: 31

May 2019.

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Publisher: Taylor & Francis

Journal: International Journal of Electronics

DOI: 10.1080/00207217.2019.1625973
A Simple and Versatile Overcurrent Protection Circuit for Power
MOSFETs

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Praveen V. Pola, Sanjaykumar L. Patilb and Sanjeev Kumar Pandeyb

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a
Vishwakarma Institute of Technology, Pune, India; b College of Engineering, Pune, India

ARTICLE HISTORY

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Compiled April 9, 2019

ABSTRACT

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This paper proposes an overcurrent protection (OCP) circuit for power MOSFETs
employed in low voltage power converters. The proposed configuration requires only
discrete components with a gate driver IC and uses the voltage drop across the device for
overcurrent detection. It can operate independently in cycle by cycle shutdown and
an
multiple cycle shutdown modes. In coordination with a micro-controller based driver IC
input signal generator and controller, the proposed OCP circuit can also operate in a
single cycle latch-up and hiccup overcurrent protection modes. The performance of the
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proposed scheme is evaluated experimentally at both, hard and soft fault conditions. By
experimentation it is shown that the proposed circuit can operate in various protection
modes and capable of protecting a MOSFET in both, hard and soft fault conditions.
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KEYWORDS
Fault; overcurrent protection circuit; response time; protection modes; MOSFET
protection.
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1. Introduction
Low voltage power converters up to few kilowatts power ratings, employ power MOSFETs for
minimizing conduction losses as low voltage power MOSFETs exhibit very low on-state
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resistance. Despite of low voltage operation, short circuits or severe faults subject those devices
to intolerable current levels, leading to degradation or catastrophic failure. This necessitates a
gate driver with overcurrent protection feature for reliability. Overcurrent protection (OCP)
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scheme is mainly characterized by the overcurrent detection technique, its response time and the
type of overcurrent protection mode. The common type of OCP actions or modes are:
(a) Cycle by cycle shutdown: also called as pulse by pulse shutdown. In this OCP mode,
the gate driver is shutdown at every switching cycle or PWM pulse when overcurrent is detected
and the process continues till the fault exist. Due to the repetitive overcurrent pulses, power
dissipation in a power device protected under this OCP mode is more and hence the power
device is likely to get over heated. Therefore this mode is suitable when peak fault currents are
limited.
(b) Multiple cycle shutdown: unlike cycle by cycle shutdown mode, in this mode, the
driver is shutdown for a time period corresponding to the multiple cycles after every overcurrent
pulse. Thus there exist a blanking time between two overcurrent pulses. Therefore the repetition
rate of over current pulses is much lesser. This generates lesser power dissipation in a power
device protected under this OCP mode and hence the power device can withstand higher peak
fault currents for longer duration.

CONTACT Praveen V. Pol. Email: pvpolnew@gmail.com

(c) Single cycle latch-up mode: also called as single cycle or latch-up mode. In this mode,
the driver IC is shutdown indefinitely or the PWM controller stops generation of PWM pulses
after the first overcurrent event itself. The switch remains in off state condition unless and until

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the system is not reset again. Hence in this protection mode, only single fault current pulse

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appears and hence least power is dissipated. A logic circuit or flip-flop is necessary in this OCP
circuit for latching action. The above action can also be executed by a programmable PWM
controller ( i.e. micro-controller) that discontinues the generation of PWM signal pulses going to

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the driver IC input. When the fault is acknowledged or the system is reset, normal switching
operation will begin. However if the fault persists, the above OCP action will be repeated.
(d) Hiccup mode: hiccup mode may be regarded as the blend of cycle by cycle and

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multiple cycle shutdown modes. In multiple cycle shutdown mode, there is a shutdown or sleep
time after every single overcurrent pulse, similarly in hiccup mode there is a shutdown or sleep
time but it is after a predetermined number of overcurrent pulses undergoing cycle by cycle
an
shutdown action. Hence under fault condition, the overcurrent protection system operates in a
cycle by cycle shutdown mode for a short duration and then the driver IC is shutdown for a
predetermined duration of time, called as a sleep time. The process is repeated till the fault exist.
The power dissipation in a power device is also less in this mode. (Hari, 2011; Liu & Lai, 2012;
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Sarles & DeGregorio, 2002; Shi, Mao, He, Liu & Lai, 2012).
Experimental evaluations show that, MOSFETs can tolerate overcurrent for few
microseconds, however repetitive overcurrent events degrade them (Abbate, Busatto &
Iannuzzo, 2011; Chen, Labrousse, Lefebvre, Petit, Buttay, & Morel, 2015; Kampitsis,
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Papathanassiou & Manias, 2016). Hence response time of overcurrent protection scheme should
be fast enough to prevent a power device current crossing its tolerable limit for reducing
localized heating, peak power dissipation and prevents the device going out of safe operating
area (SOA).
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Various OCP schemes for protection of voltage controlled devices such as IGBTs, silicon
and silicon carbide (SiC) MOSFETs are proposed in the literature. Those OCP schemes differ by
configuration, overcurrent detection technique and operating modes, however response time is a
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common consideration as these power devices can withstand overcurrent duration for a very
short duration. John et. al. (1999) proposed an OCP scheme for IGBT operating at high voltages.
A desaturation detection technique is used for sensing overcurrent. The reported response time is
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less than 1 μs. Similarly, Luo and Liang (2000) proposed an OCP circuit using a desaturation
detection technique for overcurrent protection of IGBTs operating in a medium voltage range.
The circuit is simple and only discrete components are employed. The reported response time is
2 μs. Desaturation detection is a lossless and sensorless overcurrent detection technique, but the
response time is comparatively more since it involves a blanking time for bypassing switching
oscillations (Josifovic, Popovic-Gerber & Ferreira, 2012; Liu, Ning, Wong & Shen, 2016) for
preventing spurious shutdown. Besides this, the voltage drop across the device under overcurrent
condition must also be sufficient to trigger the OCP circuit, as that in the case of IGBTs. Due to
very low on state resistances, especially in the case of low voltage MOSFETs, a very low voltage
drop across the MOSFET is generated and hence discrimination between normal and over
current values becomes difficult. Therefore use of overcurrent sensing element is preferred (Patel
& Ferdowsi, 2007). A resistor is a simple and accurate device for overcurrent detection that can
be employed as a current shunt in an OCP circuit (Bi, Jia & Li, 2017), however due to its
dissipative nature, many OCP schemes employ hall effect sensor (E-T-A Circuit Protection &
Control, n.d.; Zhang & Liang, 2014) or a stray inductance for sensing current. Wang et al. (2014)
proposed a high speed OCP scheme for protection of SiC MOSFETs that uses the stray
inductance between the Kelvin source and power source of the MOSFET for current sensing. It
has soft turn off feature and mode control input that can be controlled by a controller. The
reported response time is less than 200 ns. Awwad and Dieckerhoff (2015) and Sadik et al.

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(2016) evaluated OCP schemes with desaturation detection and stray inductance techniques for

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SiC MOSFETs. The former was slower than the later but both were effective in performance.
Unlike above techniques, Horiguchi et. al. (2015) proposed a novel technique for overcurrent
protection of SiC MOSFETs by using the gate charge characteristics for overcurrent detection. It

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is useful for overcurrent protection of SiC MOSFETs only from hard faults. Wittig, Boettcher &
Fuchs (2010) proposed an OCP circuit for low voltage power MOSFET using a desaturation

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detection technique which employ a comparator IC for overcurrent evaluation and a logic circuit
to shutdown the driver IC. Due to the requirement of many components for designing an OCP
scheme additional space and cost is required. Therefore some OCP schemes are integrated on a
single chip for cost reduction and miniaturization (Abbasi, Lee, Hean Pui, Raeisinafchi, Lee &
an
Saad, 2018; Chiu & Chou, 2011; Lee, Kim, Gendensuren, Choi & Choi, 2012; Rao, Deng &
Huang, 2015; Tao & Xu, 2008) but those are confined to low power or specific applications. In
many applications, switches operate below 55 volts, especially in low power converters
employed in renewable energy and fuel cell systems (Almasoudi, Alatawi & Matin, 2016;
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Andersen, Klumpner, Kjaer & Blaabjerg, 2003; Das & Agarwal, 2015; Li, Li, Xiang, Hu & He,
2014). When switches operate at low voltages, rate of rise of fault current is also low, therefore
OCP circuit response time is not a stringent requirement, rather a simple and effective OCP
technique is preferable for protection of switches. This will improve reliability of a power
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converter circuit with minimal effect on its cost. Considering the above facts, a simple circuit for
overcurrent protection of a power MOSFET is proposed in this paper. Simplicity is achieved by
the use of less number of components whereas the low cost by using discrete components along
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with a gate driver IC. The parameters of various existing OCP schemes along with the proposed
OCP circuit are tabulated in Table 1. Every OCP circuit has its own advantages and intended
application. Those can operate in one mode independently and some of them can also operate in
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other modes with the help of a programmable PWM signal controller or a micro-controller. The
proposed OCP circuit can operate in two modes independently and the required mode can be
selected simply by determining the values of passive components. With the help of a
programmable input PWM signal controller (i.e. micro-controller) it can also operate in single
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cycle latch-up and hiccup modes. The features of the proposed OCP circuit are: (a) simplest
configuration (b) least component count (c) only discrete components are employed (d) multiple
functions of components (e) does not require any additional power supply for its operation (f)
Fast response time of 230 ns (g) can operate in all OCP modes and (h) capability to protect a
MOSFET from both hard and soft fault conditions. Due to the above features, the proposed
circuit gives a novel, versatile and cost effective solution for overcurrent protection of power
MOSFETs.
The paper is composed of five sections: introduction in Section 1, the description of the
proposed OCP circuit with analysis is presented in Section 2, experimentation in Section 3, a
brief discussion in Section 4 and finally, conclusion in Section 5.

Table 1. Comparison of various overcurent protection (OCP) schemes

Reference Components OCP modes Response Application

Scheme involved time ( tvo )
Awwad & Passive Cycle by 200 ns SiC
Dieckerhoff components, cycle MOSFETs
(2015) transistors, operating at

t
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flip-flop, high
comparator, voltages
and logic

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gates
Bi, Jia, & Li Passive Multiple 10 μs MOSFETs
(2017) components, cycle operating at

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transistors, low voltages
and current
sensing
shunt
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E-T-A Ckt. Hall effect Cycle by 1 μs MOSFETs
Protection & sensor and cycle *Pulse operating at
Control flip-flop count low voltages
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shutdown
Horiguchi et. Passive Cycle by 1 μs MOSFETs
al. (2015) components, cycle operating at
comparators high
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and logic voltages

gates
John, Suh & Passive Cycle by 2 μs IGBTs
Lipo (1999) components, cycle operating at
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comparator, high
op-amp and voltages
transistors
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Luo & Liang Passive Cycle by 2 μs IGBTs

(2000) components cycle operating at
and medium
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transistors voltages
Sadik et.al. Passive Single cycle 180 ns SiC
(2016) components, *Cycle by MOSFETs
logic gates cycle operating at
and flip-flop *Multiple high
cycle voltages
*Hiccup
Sarles & Passive Hiccup - Switching
DeGregorio components, regulators
(2002) comparator
 and
transistors
Shi, Mao, Logic gates, Hiccup - DC - DC
He, Liu, & flip-flops switching
Lai (2012) and counters converters
Wang et. al. Passive Single cycle 140 ns SiC
(2014) components, *Cycle by MOSFETs
logic gates, cycle operating at
transistors *Multiple high

t
and cycle voltages

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comparator *Hiccup
Wittig et. al. Passive Cycle by 600 ns MOSFETs

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(2010) components, cycle operating at
comparator *Multiple low voltages
and flip-flop cycle

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*Single
cycle
*Hiccup
Proposed Passive Cycle by 230 ns MOSFETs
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scheme in components cycle operating at
this paper and Multiple low voltages
transistors cycle
*Single
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cycle
*Hiccup
*Indicates OCP mode possible with the help of input signal controller
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Table 2. Acronyms
Parameters Description
VBE Transistor base to emitter voltage drop
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Vb Transistor base voltage

Vf Feedback voltage
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VD Diode forward voltage drop

Vds Drain to source voltage
Vi Driver IC input voltage
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Vo Driver IC output voltage

+Vcc Driver IC supply voltage
+Vs Load supply voltage
id MOSFET drain curent
is MOSFET source curent
tb Blanking or detection delay time
 tvo Vo on-time period under fault condition
tsd Driver IC shutdown time after OCP action
t fc Fault clearance time
Rds ( on) Drain to source on state resistance
Lds Drain to source inductance
R ft Fault resistance

t
L ft Fault inductance

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FS Fault signal

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2. Proposed overcurrent protection circuit
The proposed overcurrent protection circuit is designed using discrete components and requires a
driver IC with enable input to shutdown the output when overcurrent event occurs. Thus the

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proposed configuration results into a gate driver with OCP circuit.

Figure 1. Proposed overcurrent protection circuit

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2.1. Description
The diagram of the proposed overcurrent protection circuit is shown in Figure 1. The technique
of overcurrent protection is to disable the driver IC by pulling the enable input (EN) voltage
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below its logic low threshold level by instantly discharging the timing capacitor Ct through the
switching transistor Q2 when Vb exceeds VBE drop of Q2 . This disables the driver IC and the
output Vo goes low. The MOSFET Q3 is then turned Off, V f goes low and Q2 is switched-off.
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The driver IC is enabled again when the capacitor charges above the logic high level threshold
voltage of the enable input. As shown in Figure 1, Rt and Ct are the timing components that
determine the shutdown period of the driver IC when overcurrent event occurs, whereas R1 , R2 ,
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R3 and Cd determine the blanking time, sufficient to bypass the time required to turn-on the
MOSFET Q3 and switching oscillations thereafter, for preventing spurious shutdown. Besides
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this, the function of R1 is to bias the feedback diode D f when Vo goes high and Q3 is turned-on.
Transistor Q2 controls the driver IC output Vo by enabling and disabling it, thus it acts as an
overcurrent evaluator as well. Though the driver IC enable input can tolerate voltage up to its
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supply voltage +Vcc , zener diode Dz with breakdown voltage Vz is selected to charge Ct to
maximum standard logic high level voltage of +5 V instead of +Vcc as it is much higher. This
limits the charge stored in Ct and helps it to discharge quickly through Q2 . This reduces the
response time of the OCP circuit. The fault is reported by the status of Q1 which is On under
normal operating condition and turns Off when OCP action initiates.

2.2. Analysis
The feedback diode D f gets biased through R1 when the driver IC output Vo goes high (
approximately to its supply voltage +Vcc ). The current iR1 splits into iR 2 and iDf . Due to iDf ,
voltage VD is generated across the diode D f whereas the generation of voltage Vds is mainly due
to id since id >> iDf . This generates the feedback voltage V f which is the sum of the feedback
diode voltage drop +VD and voltage Vds across the MOSFET Q3 , that can be expressed as
V f = VD + Vds (1)

did

t
V f = VD + Lds ( ) + (id ) Rds ( on ) (2)
dt

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Using the basic equation V = L(di / dt ) , and replacing V by the supply voltage +Vs and L by
fault inductance L f , Eq. 2 becomes

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+Vs
V f = [VD + Lds ( ) + (id ) Rds ( on ) ] (3)
Lf

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V f is divided by resistors R2 and R3 and voltage Vb is obtained at the base of transistor Q2
which is given by
R3
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Vb = V f [ ] (4)
R2 + R3
Substituting Eq. 3 in Eq. 4, the equation for Vb can be written as
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+Vs R3
Vb = [VD + Lds ( ) + (id ) Rds ( on ) ][ ] (5)
Lf R2 + R3
The OCP action initiates when the voltage Vb at the transistor base overcomes the base to
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emitter forward voltage drop VBE . The base current ib flows and Q2 switches on. Thus, for OCP
action
+V R3
Vb = [VD + Lds ( s ) + (id ) Rds (on ) ][ ] > VBE (6)
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Lf R2 + R3
Hence the OCP threshold voltage value of Vb = VBE . Considering the maximum drain current id
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limit and soft fault inductance value, the values of R2 and R3 are calculated using the above
equation. The current i3 through R3 and ib are calculated using the basic equations: i3 = VBE / R3
and ib = ic / β . As the capacitor Ct discharges through the collector of the transistor Q2 , higher
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collector current ic discharges Ct faster and the response time of the OCP circuit reduces.
Therefore the value of ib is calculated for higher ic (typically in the range of 100 to 500 mA).
When the driver IC output goes high, Vo is approximately equal to +Vcc . The total current ( ib +
i3 ) is drawn from +Vcc through R1 and hence to fulfill the requirement of the above current, the
value of R1 is then calculated by
+Vcc − V f
R1 = (7)
ib + i3
When the driver IC output is low, capacitor Cd is in discharged condition, Q3 is off and D f is
non conducting. When it goes high, then Vo is approximately equal to +Vcc , the capacitor Cd
starts charging through the thevenins equivalent resistance Rth and voltage Vth given by
Rth = ( R1 + R2 )  R3 (8)

R3
Vth = ( )Vo (9)
R1 + R2 + R3

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Assuming that D f is not conducting, the delay capacitor Cd will charges to VBE value of Q2 in

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a time tV and then the base current ib flows and Q2 switches On after its turn on delay time
BE

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td ( on ) . Therefore the OCP circuit remains inactive for total time period of [ tV + td ( on ) ] and
BE

hence the blanking time tb is

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Vth
tb = Cd Rth ln[ ] + td ( on ) (10)
Vth − VBE
Thus, the value of Cd can be determined for the required value of tb . When overcurrent event
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occurs, Q2 discharges Ct which disables the driver IC, Vo goes low and then Q2 is switched-off.
Ct is then released by Q2 and re-commence charging via Rt and also by the IC internal pull up
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resistor Ri , therefore the charging of Ct is from parallel combination of the above resistors.
Besides Ct the gate to source capacitance Cgs1 of Q1 is parallel with Ct and hence it also
charges simultaneously with Ct thereby reducing charging speed of Ct . Thus Ri and and Cgs1
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also play role in determination of shutdown time. The time required to charge the capacitor Ct to
the logic high threshold voltage level VHL of the driver IC, is the driver IC shutdown time tsd
which is given by
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+Vcc
tsd = (Ct + Cgs1 )( Rt  Ri ) ln[ ] (11)
+Vcc − VHL
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By using the above equation, values of Ct and Rt are calculated for the required shutdown time.

3. Experimentation
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The experimental schematic diagram is shown in Figure 2 and the corresponding setup is shown
in Figure 3. The design specifications for experimentation are given in Table 3. Referring to the
datasheets and specifications, the experimental parameters are determined by using the equations
given in the analysis section which are tabulated in Table 4. The driver IC input signal ( Vi )
generator and controller is designed using a PIC16F1939 micro-controller which responds to the
fault signal FS while operating in single cycle latch-up and hiccup OCP modes. As the drain
terminal of Q1 is open, it is connected to the micro-controller supply +Vdd through a pull up
resistor R pu for generating an active high fault signal (FS) pulse when Q1 switches-off due to the
OCP action. Under normal condition Q1 is On and FS output is low. The driver IC is given
separate supply +Vcc and the load supply is +Vs . A high value on-board electrolytic capacitor of
10,000 μ F with two parallel polyester capacitors of 10 μ F each are connected in parallel to
achieve extremely low equivalent series resistance (ESR) and equivalent series inductance
(ESL), due to this the peak current sourcing capacity of the supply +Vs becomes very high.
For experimentation, as observed in the experimental setup, hard fault is created by simply
shorting the MOSFET drain terminal to the power supply (i.e. by shorting the load terminals)
using a short wire (blue wire). The soft fault is created by the same way but instead of a wire it is

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shorted by an inductor of 1 μH. (yellow toroid core inductor visible at the right side).

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The experimental waveforms are observed on a 100 MHz DSO. For observation of the drain
current waveform a current sensing resistor Rcs is built using 10 SMD resistors (size code 1206)

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connected in parallel for achieving extremely low parasitic inductance for observation of true
nature of the drain current waveform. However, for the purpose of experimentation, Rcs is

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connected in series with the source of the MOSFET ( Q3 ) instead of connecting in series with the
drain terminal. Two separate grounds connections GND1 and GND2 are used instead of a single
ground. GND1 is common for input signal, driver IC and the OCP circuit whereas GND2 is for
the load supply +Vs . Due to the above connections, the gate capacitance charging and
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discharging currents are bypassed through GND1, and hence the source current is through Rcs
will be same as id and the voltage observed across Rcs will be as per the nature of id but
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inverted. This is correctly observed by inverting the DSO input channel displaying the id
waveform. Due to the above technique, the need of DSO with isolated input channels is
eliminated and both id and Vo waveforms can be observed with respect to the source terminal
simultaneously.
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Figure 2. Experimental schematic

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Figure 3. Experimental setup

The performance of the proposed overcurrent protection circuit is observed through the
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experimental waveforms in various OCP modes and its capability to operate under short circuit
and also in soft fault conditions, is presented in next subsections.

Table 3. Design Specifications

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Parameters Values Description

id ( max ) 50 A Maximum
drain current
limit
+Vcc +15 V Driver IC
supply
voltage
+Vs +30 V to Load supply
+50 V voltage
 range
tsd 4.5 μs For cycle by
cycle
shutdown
tsd 20 μs For multiple
cycle
shutdown
VD 0.6 V Datasheet
reference

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VBE 0.7 V Datasheet

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reference
Rds ( on) 4 mΩ Datasheet

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reference
Lds 10 nH Datasheet
reference

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Table 4. Experimental Parameters
Parameters Values
Vf 1.1 V
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R1 2.2 k Ω
R2 150 Ω
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R3 300 Ω
Cd 560 pf
Rt 33 k Ω (Cycle by cycle shutdown)
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Rt 150 k Ω (Multiple cycle shutdown)

Ct 1.5 nF
Rcs 0.1 Ω
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L ft 150 nH (For short circuit fault)

L ft 1 μH (For soft fault)
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Df ES1D
Q1 IRLML2803
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Q2 MMBT2222A
Q3 IPP051N15N5
DFW C3D10065A
Driver IC NCP81071B

Figure 4. Driver IC input Vi and output Vo waveforms under normal condition

3.1. Cycle by cycle shutdown mode

The values of timing components, Rt and Ct are selected to fix the driver IC shutdown time ( tsd
), slightly lesser than the time period of the input signal waveform. This enables the driver IC in
every off time period of the input signal Vi waveform, and prevents multiple shutdown in a
single pulse duration. Due to this, the driver IC gets enabled before the start of the subsequent
cycle pulse so that the OCP circuit responds in every successive cycle. In the experimentation tsd
is approximately 4.5 μs as the time period of the experimental waveform of 200 kHz is 5 μs.
Initially, a nominal load of 22 Ω is connected for observing the driver IC input Vi and output Vo
waveforms under normal operating condition. The waveforms are shown in Figure 4, which are

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similar in time scale since the OCP circuit is inactive in the normal condition. The load is then
replaced by a wire to create a short circuit or hard fault and then input signal Vi is applied. The
OCP circuits activates and protects the MOSFET in every cycle by disabling the driver IC which

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is observed in Figure 5.

Figure 5. Driver IC input Vi and output Vo waveforms in cycle by cycle shutdown mode

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Figure 6. Driver IC input Vi and output Vo waveforms in multiple cycle shutdown mode
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Figure 7. Driver IC input Vi and output Vo waveforms when Vi is continuously high in multiple
cycle shutdown mode
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3.2. Muliple cycle shutdown mode
For observation of waveforms in this OCP mode, same procedure as above is followed, except
that the value of Rt is changed for increasing the shutdown time. For experimentation the
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shutdown time tsd is taken as 20μs, corresponding to 4 cycles. The driver IC input Vi and output
Vo waveforms under this mode are observed in Figure 6. In Figure 7, it is shown that even if the
input is continuously high, the OCP circuit operates in this mode. The observed shutdown time is
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19 μs, differing slightly from the theoretical value of 20 μs due to tolerances in components and
determination of parametric values.
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3.3. Single cycle latch-up mode

In the above two modes the OCP circuit operates independently and the role of the fault signal
FS is simply to report the fault condition but it is not essential. In this type of mode the OCP
circuit protects the MOSFET from overcurrent, however the single cycle latch-up action is
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executed by the micro-controller on the reception of the fault signal FS from the OCP circuit.
The generation of the input signal or PWM pulses is discontinued indefinitely till the micro-
controller is not reset. Shutdown time is insignificant in this mode. By programming the micro-
controller and using the OCP FS output, the cycle by cycle shutdown or multiple cycle shutdown
mode is converted into a single cycle latch-up mode. The input Vi and output Vo waveforms in
this mode are shown in Figure 8. It is observed that the under the fault condition the driver IC
output Vo is shutdown and input signal Vi is discontinued. Hence both, Vi and Vo remains low.
Figure 8. Driver IC input Vi and output Vo waveforms in single cycle latch-up mode

Figure 9. Driver IC input Vi and output Vo waveforms in hiccup mode

3.4. Hiccup mode

The operation of the OCP circuit in cycle by cycle shutdown mode is converted in to the hiccup
mode, simply by monitoring the FS pulses. The controller counts the predetermined number of
FS pulses after which the input switching signal Vi is discontinued for a fixed duration which

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acts as the sleep time. The sequence of counting a fixed number of FS pulses followed by the

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sleep time is repeated till the fault exist. In this mode, the role of the micro-controller is simply to
count FS pulses and generate the sleep time. For experimental demonstration the driver IC is

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shutdown after 5 FS pulses and sleep time is taken as 50μs corresponding to 10 cycles. Vi and Vo
waveforms under the hiccup mode OCP action are shown in Figure 9.

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3.5. Hard and soft fault conditions
In context of power electronics switches, hard switch fault (HSF) or simply a hard fault is a
condition when the circuit loop impedance becomes very low. Due to this, fault current goes to a
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very high level with high di / dt (high fault current rising rate). This especially happens in the
case of short circuits. Soft fault also leads to a very high current level but with lower di / dt (low
fault current rising rate). It occurs when a load is shorted by a higher inductance (John, V., Suh,
B. S. & Lipo, T. A., 1999; Wang, Z. et al., 2014). Soft fault can also be caused due to
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degradation or failure of the circuit components (Sun, Q., Wang, Y. & Jiang, Y., 2018)

3.6. Response time and fault current

The response and fault clearance times are observed under both, short circuit (hard fault) and soft
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fault conditions. The approximate fault inductance values are shown in Table 4. The drain
current id waveform is observed across the Rcs = 0.1 Ω , therefore 2 V/div corresponds to 20
A/div. Figure 10 shows the response of the OCP circuit under hard fault condition at the load
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supply voltage +Vs = 30 V and time scale of 100 ns/div. The driver IC output Vo and the drain
current id waveforms are observed in Figure 10. Comparing both waveforms in time scale, id
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waveform is delayed as it starts rising after the turn-on delay time of the MOSFET Q3 and starts
falling after the turn-off delay time. When Q3 starts conducting the id increases rapidly and the
OCP action initiates instantly since di / dt is very high under short circuit condition, which
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generates V f , sufficient enough to switch-on the transistor Q2 . Due to the OCP action id goes
upto maximum 55 A and then falls to zero.

Figure 10. Driver IC output Vo and drain current id (2 V/div corresponds to 20 A/div)
waveforms under hard fault condition when +VS = 30 V

The fault clears within 300 ns as id persists up to 300 ns and hence, it is the fault clearance time
t fc . Similarly, Vo remains high for the time tvo which is about 225 ns and hence the response
time of the OCP circuit is approximately 225 ns. Figure 11 shows the response of the OCP
circuit under soft fault condition. Due to the higher value of fault inductance the rate of change
of drain current ( di / dt ) is less and hence the voltage generated due to the parasitic inductive
component Lds of the MOSFET is less. Thus V f is insufficient for initiating the OCP action
instantly. As id increases, the voltage drop across the MOSFET due to the resistive component
Rds (on ) increases to a value, sufficient to initiate the OCP action and then the driver IC is
shutdown. In this fault condition response and fault clearance times are insignificant as the OCP
circuit does not activate instantly but only when the id reaches to the value that could generate

t
ip
sufficient V f to trigger the OCP circuit. As observed in Figure 11, the drain current reaches upto
60 A within 2.2 μs and clears thereafter. The design specification is to limit the fault current i f

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(i.e. peak value if id under fault condition) up to 50 A whereas the experimental values obtained
are 55 A and 60 A for short circuit and soft fault conditions respectively.

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Figure 11. Driver IC output Vo and drain current id ( 2 V/div corresponds to 20 A/div)
waveforms under soft fault condition when +VS = 30 V
an
Figure 12 shows the performance of the OCP circuit at 40 V supply voltage under hard
fault condition, due to higher voltage, the rate of rise of id is more and hence the fault current
goes upto 72 A, Whereas under soft fault condition it goes upto to 68 A which is observed in
M
Figure 13.

Figure 12. Driver IC output Vo and drain current id ( 2 V/div corresponds to 20 A/div)
ed

waveforms under hard fault condition when +VS = 40 V

Figure 13. Driver IC output Vo and drain current id ( 2 V/div corresponds to 20 A/div)
waveforms under soft fault condition when +VS = 40 V
pt

Figure 14. Driver IC output Vo and drain current id ( 2 V/div corresponds to 20 A/div)
ce

waveforms under hard fault condition when +VS = 50 V

Figure 15. Driver IC output Vo and drain current id ( 2 V/div corresponds to 20 A/div)
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waveforms under soft fault condition when +VS = 50 V

At 50 V supply voltage the fault current under hard fault goes still higher upto 78 A as observed
in Figure 14. However, under soft fault condition it is around 62 A which is comparatively less
as there is reduction in the response time which is observed in Figure 15. The experimental
results are consolidated in Table 5. From this table it can be inferred that, under hard fault
condition the overcurrent peak value increases with the increase in the supply voltage since
response time is almost constant. However in the case of soft fault conditions the fault current
values does not increase remarkably as response time decreases at higher supply voltages hence
their values are closer to each other. Though the fault current peak values are higher than the
theoretical design limit of 50 A, they are not far away from it, hence they are acceptable. The
main purpose of MOSFET protection under various fault conditions is fulfilled by the proposed
OCP circuit.

Table 5. Experimental values of response time ( tvo ) and peak fault current ( i f ) at various test
conditions.

t
Supply Hard fault Hard fault Soft fault Soft fault

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voltage
+Vs tvo if tvo if
30 V 225 ns 55 A 2.2 μs 60 A

cr
40 V 230 ns 72 A 1.8 μs 68 A
50 V 220 ns 78 A 1.3 μs 62 A

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4. Discussion
Simplicity and capability to operate in various OCP modes and protection of MOSFETs in both,
hard and soft fault conditions are the strengths of the proposed OCP circuit whereas the novelty
an
lies in the multiple functions of the circuit components. The transistor Q2 acts as an overcurrent
evaluator, as a voltage reference ( VBE drop) and the timing capacitor discharging switch. The
driver IC besides driving the MOSFET gate, it is also involved in generation of the shutdown
M
time by using the internal logic threshold voltage levels of the enable input along with the timing
components Rt and Ct . Combination of R2 , R3 and Cd acts as a low pass filter, generates
blanking time and sets the overcurernt threshold level for OCP action. Due to the above multiple
ed

functions, the need of a comparator IC, voltage reference, timing and logic circuits are
eliminated.
In the proposed OCP circuit, there is no accurate current sensing element like resistor and
comparator IC for overcurrent evaluation, therefore the OCP accuracy depends on the value of
pt

the component parameters such as VBE , VD , Lds and Rds (on ) which are determined while
designing the OCP circuit. From the application point of view, the circuit is suitable for
overcurrent protection of low side power MOSFETs employed in boost, flyback, forward and
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push-pull converters where internal faults occur due to saturation of inductors, transformer cores,
shorting of rectifier or free wheeling diodes, short circuits in transformer windings or external
faults due to shorting of output cables or due to excessive loading.
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5. Conclusion
In this paper, a simple and versatile overcurrent protection circuit for power MOSFETs is
proposed. It is shown that the proposed overcurrent protection circuit can operate in a cycle by
cycle shutdown, multiple cycle shutdown, single cycle latch-up and hiccup overcurrent
protection modes. It is capable of protecting a MOSFET even if the driver IC input is
continuously high. The response time is less than 250 ns and clears fault within 300 ns under
short circuit fault. It can protect a power MOSFET form both, hard and soft faults by limiting the
fault current closer to the designed value.
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