Grid Connected Cascaded Multilevel Inverter with

Step Mode Space Vector Pulse Width Modulation

S.Naveeena1,M.Bhavani2,K.Asokan3
1
PG Student,Department of Electrical & Electronics Engineering,Government College of Engineering-Bargur
2
Professor,Department of Electrical & Electronics Engineering,Government College of Engineering-Bargur
3
Professor,Department of Electrical & Electronics Engineering,Government College of Engineering-Bargur

Abstract-The multilevel inverter is a I.INTRODUCTION

powerful electronic device widely used for
high power utility applications. The main Multilevel inverters have been under research
purpose of the multilevel inverter is to
and development for more than three decades
provide sinusoidal waveforms with low level
harmonic content to reduce distortion. and have found successful industrial
Multilevel inverters continue to receive applications. However, this is still a technology
more and more attention because of their under development, and many new
high voltage operation capability low
switching losses, high efficiency, reduced contributions and new commercial topologies
harmonic distortion and lower have been reported in the last few years.
electromagnetic interference ability to meet Multilevel inverters have been attracting
the increasing demand of power rating and
increasing interest recently the main reasons
power quality. This paper presents a
technique for harmonic reduction in a are increased power ratings, improved
twenty seven level cascaded H-Bridge harmonic performance. The present work
multilevel inverter. Here hybrid PWM is
provides a solution to design an efficient
used for reducing the harmonic content
present in the output waveform. Selective multilevel topology which is suited for medium
Harmonic Elimination PWM is used for and high power applications.
eliminate the 3rd and 5th order harmonics.
Space vector pulse width modulation A. Multilevel Inverter
technique is used for increasing the level of
output. Increasing the output levels will
There are different power converter
reduce the harmonics. The MATLAB-
SIMULINK is used to verify the simulation topologies and control strategies used in
results. inverter designs. Different design approaches

Keywords –Multilevel Inverter,Matlab address various issues that may be more or less
,Simulink. important depending on the way that the
converter is intended to be used.
 The issue of waveform quality is one the
important concern and it can be addressed in
many ways. In practice capacitors
inductors can be used to filter the waveform.
If the design includes a transformer, filtering
can be applied to the primary or the secondary
side of the transformer or to both sides.
clamp converter typically consists of m – 1
capacitors on the dc bus and produces m levels
and of the phase voltage. Fig 1. shows a single-
phase full bridge three level and five-level
diode-clamp converter in which the dc bus
consists of four capacitors, C1, C2, C3 and C4.

B. Challenging Aspects In Multi Inverters

The voltage source inverters produce

an A.C output voltage or a current from dc link
voltage. They are known as the two-level
inverter. To obtain a quality output voltage or a
current waveform with a minimum amount of Fig 1 Topology of the diode-clamped inverter
CMV and THD requires high-switching (a) three-level inverter, (b) five -level inverter.
frequency along with various PWM strategies.
TABLE 1

C.Multilevel Inverters Topology SWITCHING STATES OF 5-LEVEL DIODE

CLAMPED INVERTER
The general structure of the multilevel
inverter is to synthesize a near sinusoidal
voltage from several levels of dc voltages,
typically obtained from capacitor voltage
sources. As the number of levels increases, the
synthesized output waveform has more steps,
which produces a staircase wave that
approaches a desired waveform.

D. Diode-Clamped Multilevel Inverter

The most commonly used multilevel

topology is the diode clamped inverter, in
which the diode is used as the clamping device
to clamp the dc bus voltage so as to achieve
E. Flying Capacitor Multilevel Inverter
steps in the output voltage. An m-level diode-
 The structure of this inverter is similar A cascaded multilevel inverter consists
to that of the diode-clamped inverter except of a series of H-bridge (single-phase full-
that instead of using clamping diodes, the bridge) inverter units.
inverter uses capacitors in their place. The
flying capacitor involves series connection of
capacitor clamped switching cells.

This topology has a ladder structure of

dc side capacitors, where the voltage on each
capacitor differs from that of the next capacitor.
Figure 2. shows the five-level capacitor F

clamped inverter respectively. ig 3: Single phase structures of Cascaded

inverter (a) 3-level (b)5-level (c) 7-level

TABLE 3
COMPARISON OF TRADITIONAL MULTILEVEL
TOPOLOGIES

Fig 2: Topology for Capacitor-clamped 5-level

multi inverter

TABLE 2
SWITCHING STATES OF 5-LEVEL DIODE
CLAMPED INVERTER
In general inverters are compared in
terms of feasibility of their utilization and
applications. According to the MIL-HDBK-
217F standards, the reliability of a system is
indirectly proportional to number of its
components, consequently less the components
more reliable is the system.

F. Cascaded Multilevel Inverter

 The method involves simple
mathematical calculations to arrive at the
desired switching angles for harmonic
elimination.

B.Asymmetrical 27 Level Multiinverter

Figure 6 represents the Asymmetrical

Cascaded H-Bridge Inverter topology. In the
proposed work 27 level cascaded h bridge
inverter with hybrid PWM.

Fig 4: Different types of modulation

This hybrid PWM consist of selective
techniques
harmonic PWM and Space vector PWM. In
this system we are used 8 number of switches
II. PROJECT DESCRIPTION
for this level of multilevel inverter.
A.Existing System

This system presents a technique for

harmonic elimination in a five level cascaded
H-Bridge multilevel inverter. The technique is
based on computation of switching angles
using Chebyshev polynomials

Fig 6: Block diagram for 27 level multi

Fig 5 : Circuit diagram for existing inverter
system
 This 27 level of output is obtained with
reduced switches.In multilevel inverter
cascaded inverter configuration attracts
more research attention than flying-
capacitor and diode clamped due to their
circuit simplicity and modularity.

The number of levels in output voltage

can be increased either by increasing the
number of H-Bridges or by providing
Fig 7 : Vector diagram for three level
different sources (Asymmetrical
Space Vector Modulation
configuration) with particular voltage ratio
among bridges or combination of both.
D.Multilevel Selective Harmonics Elimination

Providing different voltage sources

The Selective Harmonic Elimination
with suitable number of bridges with
PWM (SHE PWM) technique is
particular voltage ratio provide required
currentlyapplied in conventional twenty seven
number of output voltage level with circuit
level inverter circuits.
modularity and easy.
It needed to be compared to the
C. Multilevel Svm
optimized harmonic stepped-waveform
technique in several aspects. Mainly, the
The space vector modulation (SVM)
harmonic components and the harmonic
algorithm is basically also a PWM strategy
characteristics will be focused.
with the difference that the switching times are
computed based on the three-phase space
SHE techniques can be applied to
vector representation of the reference and the
cascade multilevel inverters using two
inverter switching states rather than the per-
approaches. The first one is to consider one
phase in time representation of the reference
commutation angle per inverter; thus, the
and the output levels as in previous analyzed
number of harmonics that can be eliminated is
methods.
Ninv − 1.
E.Switching Mode Of Operation For 27 Level Fig 9 : Mode 2 for multilevel inverter
Inverter
MODE 3:
The switching mode of operation for
27 level multi inverter are shown below. It
contains 8 MOSFET switches. Here every
positive levels are shown seperately.

MODE 1:

Fig 10 : Mode 3 for multilevel inverter

MODE 4:

Fig 8: Mode 1 for Multilevel Inverter

Fig 11 : Mode 4 for multilevel inverter
MODE 2:
MODE 5:

Fig 12: Mode 5 for multilevel inverter

MODE 6: MODE 9:

Fig 13 : Mode 6 for multilevel inverter Fig 16: Mode 9 for multilevel inverter

MODE 7: MODE 10:

Fig 14 : Mode 7 for multilevel inverter Fig 17 :Mode 10 for multilevel inverter

MODE 8: MODE 11:

Fig 15: Mode 8 for multilevel inverter Fig 18 :Mode 11 for multilevel inverter

MODE 12:
 Fig 21 : Mode 14 for multilevel inverter
Fig 19 : Mode 12 for multilevel inverter
MODE 15:
MODE 13:

Fig 22: Mode 15 for multilevel inverter

These are the switching modes

operation for 27 level multi inverter. Here
every modes are shown separately and input
voltages are t started from 25V to 375V
Fig 20:Mode 13 for multilevel inverter
respectively.
MODE 14:
III. SIMULATION RESULT

A. Simulation Diagram
 Fig 23: Simulation of cascaded multilevel
inverter

B. Pulse Generation

Fig 25: Pulses for level creator

Fig 24: Pulse generation

C. Pulses For Level Creator

 D. Pulses For H-Bridge Inverter
Fig 26: Pulses to H bridge inverter
E. Output Voltage And Current Waveform
Fig 27: Output voltage and current waveform
In this proposed system of a simulation
result is the output voltage, output current and
step level will bedisplayed with respect to time.
The maximum step level of27-Level displayed.
And the voltage level for varioussteps
displayed. The output voltage per steps with
thetime will be displayed. The range of voltage
is up to 300V can be delivered.
The harmonic spectrum of output
voltage is shownabove. The reduction of THD
is used to evaluate theperformance of the
multilevel inverter.
IV.CONCLUSION
 In this work, 27 level asymmetric
cascaded multilevel inverter is presented. This
multilevel inverter produces high quality
output voltage close to sinusoidal Waves. It is
used to provide improved performance than the
conventional cascaded multilevel inverter. And
also this method is used to minimize the
switching losses.
The total harmonic distortion (THD) is
reduced to 0.2143. Thistechnique is used to
improve the level of the inverter andextends
the design flexibility and reduces
harmonics.When the number of level increase
total harmonicdistortion is decreased.
Thesimulation results give better quality of low
harmonic characteristics.
The 27-level Cascadedmultilevel
inverters with THD characteristics are verified
through simulation results by using MATLAB.
FUTURE SCOPE
In future, the simulated circuit will be
implemented over hardware and aim is to
achieve good correlation between the results of
computer simulation and experiments for 27
level multi inverter. And also levels will be
increased for decreasing the harmonics
further implementation.
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