(Logic Analyzer) Design Report

{Logic Analyzer}
Design Report
www.digilentdesigncontest.com
LOGIC ANALYZER
Submitted for the 2018 Digilent Design Contest Europe
GHEORGHE ASACHI TECHINCAL UNIVERSITY OF IASI

IASI, ROMANIA
Students:
Titirez Daniel
Mail:danieltitirez@yahoo,com
Adochitei Adrian
Mail:adochiteiadrian13@yahoo.com
Advisor: Zet Cristian
page 1 of 28
Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of
their respective owners.
{Logic Analyzer} Design Report
Date:07.05.2018
Contents
1. Introduction 3
2.Hardware Design 6
 FIFO Memory Block 7
 Transfer Rate Generation Block 9
 Data Receiving Register 13
 Logical block of reception 14
 The logical block of acquisition 15
 Transmission logic block 17
 The Register Block 18
 Block of the transmitted data register 21
3.Software design
 PC Application 23
4.Disscusion
 Problems Encountered 26
 Marketability 26
 Community Feedback 27
 References 27
page 2 of 28
Introduction
Abstract
The present project consists in a design of a logic analyzer, which can help students and
engineers to verify digital hardware, digital communication and software integration. The logic
analyzers are usually made with 34 to 136 channels, each channel being a single digital signal,
with sampling frequencies up 700 MHz and recording memories up to 64 MB. It does not
measure analog details like voltage values, but instead detects levels of logic thresholds. Our
design is a simple one allowing recording up to 8 channels, with sample frequency up 12 MHz
and recording memories up to 128 B. It fits a relative small and cheap FPGA and can be
implemented in house for developing digital and microcontroller application. Acquired date can
be transferred to a computer via a serial interface.
Objectives
Our objectives are to design a logic analyzer able to:
- Acquire logic signals to test and verify simple digital circuits studied didactic labs;
- Acquired logic signals to test and verify simple microcontroller applications;
- Studying and testing various communication interfaces like I2C, SPI, RS232, CAN;
Features-in-Brief
- Simultaneously acquire data from 8 channels;
- Programmable sampling frequency of 12, 6, 2, 1, 0.5, 0.1, 0.05, 0.01, 0.005, 0.001 MHz;
- Triggering the acquisition on one the input signals or using a separate signal on its rising or
falling edge;
- Locally store acquired data in a FIFO memory;
- Data transfer to a computer via a serial interface;
- Software for data analysis, storage and display;
page 3 of 28
Project Summary
PmodRS
ARTY7 232
Input signals
communication
with the
application
The general block diagram is described below:
The FIFO memory block has a primary element a 128 byte wide memory that temporarily sotes the acquired data from
the inputs. 8 AND gates let the input signals reach the FIFO memory. A 2:1 multiplexer select which data is sentto the
Transmission block, either from FIFO memory or from the State register.
The data receiving register is an 11 bit shift register used to store bit by bit the incoming words from the computer. It is
initialized to 0 and when clocked by the transmission clock it shifts data until all 11 RS232 incoming bits are stored.
The sampling rate generator allows 12 predefined sampling rates to be selected by software. They are obtained starting
from the 12MHz oscillator available on the ARTY board by dividing with different programmable factors (1, 2, 3, 4, 6, 12,
24, 120, 240, 1200, 2400, 12000). The sampling rate is programmed via the RS232 interface from the LabView application.
In this block it is included the frequency divider (625) for the baud rate clock, too.
The acquisition block counts the number of bytes that is acquired and stops the process when the preset number is
reached (16, 32, 64 or 128). It counts the acquisition clock pulses after the starting conditions is true: trigger event or soft
start.
The transmission blockis used to send data over RS232. It uses the same settings as for reception (11 bits with 8 data
bits and 2 stopping bits). The data byte is parallel loaded into the shift register and start bit and stop bits are added. Data is
shifted on each baud rate clock pulse. The process stops after 11 clocks.
The register blockincludes 5 registers: The address register (reg_adr), the acquisition register (regrk), the
Command register (reg_comanda), the Control register (reg_control) and the Status register (reg_stare). The Address
register is loaded with the address of the register being written or read. The Acquistion register starts the acquisition by
page 4 of 28
software or clear the data. The Command register programms the number of samples being acquired and the sampling rate.
The Control register
programs the trigger slope and mode. The Status register shows informations about the status of the analyser (end
of acquistion, reset device and FIFO empty)
Digilent Products Required
For this project, we used two hardware components:

-Pmod RS232: Serial Converter and Interface Standard;
-Cmod A7: Breadboardable Artix-7 FPGA Module;
Tools Required
The software we used to implement the project are:
-Labview;
- ISE Design Suite 14.7;
-Vivado;
Design Status
The project is done in proportion of 70%, with the software application in Labview and all the blocks necessary for
implementation of the project, which are realised and simulated in ISE Design Suite. Next step is to simulate the circuit
including all blocks, but also the import of the project on Vivado and programming the circuit in the A7 Cmod board.
Background
Why This Project?
For this project we chose the logical analyzer because this is useful to diagnose a problem with the logic of a circuit. This
type of device can reveal information about what really happens inside of a circuit, about signals interpretation and their
evolution on the entire process of data transmission or reception. It present an efficient method, which can be implemented
and personalized depending on your needs. The fact that can analyze in the same time a big number of signals, is a huge
advantage.
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Hardware Design
Block diagram
page 6 of 28
Top Level I/O pins
Pin Name Pin Direction Description

A(7:0) Input The Data Acquisition Input
Rx Input The line of reception for the serial interface
Clk Input Global clock line, from board oscillator. Frequency: 12MHz
Tx Output The line of transmission for serial interface
Trigger Input The acquisition selection with triggering
Modules on the top level schematic
Module Name Description

memorie FIFO Memory Block
genbr Transfer Rate Generation Block
logreceptie Logical block of reception
regdr Block of the received data log
registri Registers Block
log_transmisie Transmission logic block
logachizitie The logical block of aquisition
regdt Block of the transmitted data register
FIFO Memory Block
This block has as its main element a FIFO memory(first in first out).It memorize a data set received at the input
A(7:0), in this case,it can memorize maxim number of 128 octeți .Beside FIFO memory,this block contains two sub-
blocks:-a sub-block with ports and-optsi
-a sub-block with two multiplexors 8x1-multiplexor
The sub-block which contains 8 logical ports has the role to let the information pass, or to block its way into the
FIO memory, with the help of the input signal- Blocare
The block formed by multiplexors has the role to sort which information will get to the transmission block,the
octet set of FIFO memory, and if the memory is empty, a signal given by the registers block will start the data transmission
in the status register.
We can sendto the transmission register the contain of the memory or we can send received values from registers through
input B(7:0). This is done by the signal Reading_Status, received from the registers on the SEL input.
From the waveforms displayed by the test bench, we can observe that when the memory is empty, the EMPTY
input shows 1 logic and when the data stocks begin, this shows zero and in the final situation - when the memory is full, we
have FULL output in 1 logic.
page 7 of 28
Fig.1.a
Schematic diagram - top level design
Fig 1.b
Simulated waveforms
In the figure above, we can observe that the memory can be charged with a tact signal on the WRCLOCK input and on the
WREN input validation with 1 logic. This signals input are transmitted to the memory by the logic of acquisition. We
charge the memory with the values from A(7:0) input until we obtained on FULL output,1 logic. This output mark the
moment when the memory is full. In this point, the memory is full filled with those 128 octets received by the input.
page 8 of 28
Fig 1.c
Simulated waveforms
In 1.c figure, we activated the RDEN input and the tact signal RDCLOCK for writting on output,values previously saved
in the memory. It can be observed that in the moment when all values from the memory are written on the Y(7:0) output,
this gets empty, and the (EMPTY) signaling output reveals that the memory is empty and gets in 1 logic. In this moment
we transmit the data set from the memory to the transmission register.
Fig 1.d
Simulated waveforms
In this figure, it can be observed that we can select which data set can be sent to the transmission register, through the SEL
input. When this is in 1 logic at the output, we have the data set received from registers trough B(7:0) input, and when it is
in 0 logic at the output, we have the data set saved in memory. In this way we can select which data set will be transmitted
by transmission register and the by the RS-232 interface to the PC.
Genbr - Transfer Rate Generation Block
page 9 of 28
This block is composed by two divisors: (divizor 12) and (divisor625). The designed circuit
allows the selection of 12 predefined sampling rates. All these values are obtained by dividing the tact signal from the
oscillator on the board. In the circuit below, the frequency splitting of 12 MHz was performed in the following frequencies:
6, 2, 1, 0.5, 0.1, 0.05, 0.01, 0.005, 0.001 MHz to to get the desired sampling clock.
In this block is included the frequency divider (625) for the baud rate clock, which divides the 12 MHz frequency up to 625
Mhz ,necessary to get a baud rate clock (which represents the transfer rate of the input bits.)
Fig 2.a
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Fig 2.b
From the figure 2.b we can observe the baud rate clock signal that is made from the input signal,and it is repeated every
625 tact pulses. You can also see the sampling clock that can be selected depending on the RX input [3: 0]. Depending on
the value selected on the RX input [3: 0], we will have a certain sampling timing signal.
Fig 2.c
In Fig 2.c is represented the divider which divides the input frequency with various factors in order to obtain the sampling
clocks. These frequencies can be selected using a 12x1 multiplexer. This circuit is containing:
- four divisors dividing by 5;
- six divisors dividing by 2;
page 11 of 28
- a divisor dividing by 3;
Fig 2.d
Simulated waveforms
From the test bench above, you can see how the input frequency is gradually divided into several
frequencies that can be selected at the divider output.
Fig 2.e
page 12 of 28
In this logic scheme we have a divisor dividing the input frequency from 12 MHz to 625 Hz. This divisor consists of:
-a divisor dividing by 2;
- two splitters that divide by 8;
Fig. 2.f
Simulated waveforms
In this simulation we can see how the input frequency is gradually divided down to 625 Hz. The frequency we need for the
baud rate;
Regdr - Data Receiving Register
The 11 bit shift register is used to store bit by bit the incoming words from the computer. The reception
logic detects the falling edge of the incoming signal and clock the register with 11 clock pulses. Each
clock loads a bit from the incoming word into the register and shift the data to the right. The received
data is stored in one of the registers. The same design as the Transmission register has been used,
except the load capability that is not used.
Fig 3.a
page 13 of 28
Fig 3.b
Simulated waveforms
The waveforms are observed when we have the signal at the RX input at the same time and the clock signal takes place to
the right by 1 logic. When the two do not synchronize we have a right shift with 0. On the SEL entry we can select which
data set goes into the registers.
Log_receptie - Logical block of reception
The actual reception is done under the control of the logic block of the reception. It has the function of generating the
tact signal that will be used to drive the block of registers, signal that will be in compliance with defined communication
parameters.Besides these functions, due to the fact that the transfer is performed asynchronously, appears the problem of
detecting the moment of the appearance of a new data packet at the input. So you must first determine the number of bits of
the data sequence to receive, according to the defined communication parameters. This is done using a 4-bit counter
programmed to number up to 11 (because a complete sequence is made up of 11 bits). When the counter reaches 11, the
carry-out gives a reset signal to the flip-flop, and it goes to 0 (no longer letting it pass) until a new sequence is signaled. The
structure of logic reception consists of:
- an input signal representing the transmitted word (RX);

- a clock signal (BIS) representing the bit rate of the input bits;
- 3 D-type bistabs; - a 4-bit counter;
- a 3-state numerator;
- 3 outputs: BRR (bitrate transfer rate) and the other two to give clock signals to be used in the register block (MEMA and
MEMD)
page 14 of 28
Fig 4.a
From Fig. 4a it is noticeable that the MEMA and MEMB outputs are generated by the counter (num_2) together with the
output of the counter (num11), more precisely:
- the MEMA impulse is generated when the Q0 output of the 3-state counter is in the state 1 logc along with the carry
output from the counter (num11);
- the MEMB impulse is generated when the Q1 output of the 3-state counter is in the logical state 1 with the carry out of the
counter (num11);
Fig 4.b
Simulated waveforms
From the waveforms, it is noticed that after each sequence of data, a negative pulse is generated, meaning MEMA and
MEMD. After the first sequence appears MEMA (memory address) and after the second sequence appears MEMD.
The output of the BRR is transmitted by an AND gate between the baud rate clock and the Rx input (which is a written
word).
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Logachizitie-The logical block of acquisition
This block has the primary role of determining the number of bits of the received data sequence, according to the defined
communication parameters. This function is performed with the help of a numerator and a 2x4 multiplexer. According to
communication parameters we have 16, 32, 64 or 128 samples for input data. Depending on the number of samples
selected, the counter will count up to that value then using the multiplexer after the number of samples has been reached,
will display a signal that will indicate that a complete purchase has been made. Also within this block will be the trigger
mode (with or without triggering).
This is done with a 2x1 multiplexer depending on how the user wants to make the purchase.
The logic scheme is made from the following components:

-mux4x1 with validation entry;
-driving tip D-type dump;
-8-bit counter;
-two mux2x1;
Fig 5.a
The output Achizitie_Completa it goes to the registry, more precisely in the status register and the outputs Clk_Scriere
and st go into memory where it sets the tact signal and activates the validation input for writing the data sequence to the
memory.
page 16 of 28
Fig 5.b
Simulated waveforms
Fig 5.c
Simulated waveforms
From Fig. 5.b and 5.c it can be noticed that when I give an impulse on the entry Start_Achizitie ,the output st go in 1
logic ,and on output Clk_Writting we have the tact on the output Clk_Es. Depending on the selection we chose for the
multiplexer, the impulse that will indicate the complete acquisition could occur in the 256, 128, 64, 32 counts. Therefore we
can select the size of the data set stored in
memory.
log_transmisie - Transmission logic block
For proper transmission, the length of the transmitted sequence should be considered based on the information
provided by the communication parameters. It also takes into account the generation of the tact signal as well as the status
indicator. To fulfill these requirements correctly, the logic block uses the signals from the registers (CITIRE_STARE,
CITIRE_DATE) and from the FIFO (FIFO_GOL). Another important issue that it has to generate is to relay the bit rate
of the output bits. This rate is marked with BRT.
page 17 of 28
Fig 6.a
At output, we have Rst_Stare and Rst_Date that arrive at the registers to reset the data and registry status after the
registry data has been passed. Another output is the output BRT(the transfer rate of the output bits) which lasts for a period
of 11 pulses. The output bit transfer rate begins when logical 1 appears on the Writting_Status and ends when the impulse
on Cout output of the count (num_11) because the countdown is reset and an impulse is pulled on the output of Rst_Stare
goes to the registers.
On the same principle, it is also based when we have Citire_date in 1 logic only after the end of this exit time we
get an impulse on Rst_date output.
The MDT signal goes to memory representing the tact for writing .
Fig 6.b
Simulated waveforms
All of the above are illustrated in this bench test, for a better understanding of functionality.
page 18 of 28
Registry-Registers Block
The Registry Block consists of 5 sub-blocks:

- Registry address (regadrr);
- Command (reg_comand)
- control register (reg_control);
- Status register (reg_stare)
- Registry commanding acquisition logic (regrk);
- Address decoder (decra);
Registru de adresă (regadrr);
The address register consists of 8 D-type bistabs connected to a common clock signal, it must be analyzed along with the
address decoder (decra) because it is like a buffer register that has the role of sending the data to the address decoder for
the data to be interpreted. At the level of the decoder we have the MEMA output of the reception logic as the clock signal,
which when deciding the logic 0 begins to decode the received data. It works on 4 bits, the rest of the bits are not
interpreted at the level of this block.
Registru de comandă (reg_comandă);
This sub-block is activated when it receives a clock signal from the address decoder.
As input we have the 8 data bits, and the outputs of this register are used as follows:
- the first 4 bits of data represents the input of the genbr block, which has the role of setting the desired sampling
frequency;
- the next 2 bits of data represent input bits for the data acquisition logic.
It consists of 8 D-type bistabs, 8 bits of received data are used as the input signal.
Registru de control (reg_control);
The control register sets the trigger mode and type. As input to this register we have 8 data bits, of which the bit 0 and
the bit 1 are used, the first bit representing the analysis mode (if mod = 0 then the trigger analysis will be performed,
otherwise the analysis will also take account of the trigger condition).Front_trigg represents the date bit 1, and in the case of
simulation, it indicates whether the simulation will be done after a negative or positive trigger.
Registru de stare (reg_stare);
This register consists of two D-type bistabs and starts to work when it receives a clock signal from the acquisition logic
through the ACHIZITIECOMPLETA input.
In total it has 3 entries, the other two have the following meanings: the FIFO_GOL bit signals that the FIFO data
memory is empty, meaning that the data will be transmitted from the status register to the analyzer TX output. RSTSTARE
bit has the role of resetting this registry after a full purchase has been made. The value of this bit is given by the logic of the
transmission (if it has the value 0 then the DFF is reset). Since at the output we have to have an 8-bit signal (one byte), the
remainder of the output bit group (Q [7..2]) binds to the table (they will always have a value of 0).
page 19 of 28
Registru care comandă logica de achiziție(regrk);
This register has as inputs the 8 data bits and a clock signal (regrk) given by the address decoder shown above. The outputs
are two, the first bit of output Q0 is the bit called START_ACHIZ, and the bit Q1 is the bit called CITIRE_DATE. The
structure is made with DFF type bistabs.
Fig 7.a
Fig 7.b
Simulated waveforms
page 20 of 28
From the waveforms and the schematics it is observed that depending on the input D [7: 0] and the MEMA and MEMD
pulses received from the receive logic, it is selected in which register of the four goes the data sequence of the input
D [7: 0]. Depending on the register to which the output goes, it can command to start a new data acquisition, read the
desired sampling frequency data, or even select a trigger (positive or negative) front.
regdt-Block of the transmitted data register
This block is used to send data via RS232. It uses the same settings as for reception (11 bits with 8 data bits and 2
stopping bits). Its architecture is the same as the receiving register. This time, the loading input is used to load data to be
transmitted.
The size of the transmitted string, according to the parameters we have defined in this project, is 11 bits with the
following meanings:
- the first bit is the start bit;

- 8 bit bits are data bits;
- two bits are for stopping.
Due to the fact that the transfer starts with the start bit, it results that all bits will occupy the same position in the
transmission register. Also, regardless of the parameter values, the two stop bits in positions 10 and 11 will always be in the
1 logical state.
Fig 8.a
page 21 of 28
From the internal structure it is observed that the first transmitted bit will always be 0 (the value of the start bit)
because it is bound to GND, which is set to 0 by default. The last two stop bits will have a value of 1 (they are linked to
VCC, meaning they will have a value of 1) ,the rest of the bits representing the data byte. As with the received data logger,
it is also composed of D-type bistable cells together with 2x1 multiplexers.
Fig 8.b
Simulated waveforms
page 22 of 28
Software Design
PC visualization
Through the LabView design system, data was transmitted through the RS-232 serial interface to
the logic analyzer implemented on the FPGA.
It includes a front panel in which the 8 signals are displayed and where some commands can be
given to analyze the transmitted data.
page 23 of 28
The front panel of the application allows to configure the serial interface (COMM Settings), to setup
the acquisition parameters (ACQ Settings), to start the acquisition (RUN), to look for the status of the
analyzer (FIFO EMPTY and ACQ Complete) and to see for the the acquired data.
The transmission settings specify the Com port (Visa Resource name), the baud rate frequency,
the number of data bits (data bits), the parity and the number of Stop bits. The acquisition settings
specify the samples number (Nr esant), the sampling frequency (Frecv esant), the trigger mode
(Trigger) and the trigger edge (Trigg edge). There are predefined list controllers.
After the settings are filled in the button RUN can be pressed and the acquisition is started.
Immediately after the acquisition is completed (the application reads the Acq complete flag) graphs
are populated with data and the FIFO empty flag is lighted. The instrument can be stopped by
pressing the Stop button.
The instrument is running an While loop until the Stop button is pressed. Before entering into the loop
the serial settings are programmed
The programs is a sequence of write operations on the serial interface if the Run button is not
pressed. It only writes at the address 1 (the Command register) the acquisition parameters, at the
address 2 ( the Control register) the trigger parameters and the address 0 (the Acquisition register) it
starts the acquisition.
The last sequence changes the Run button state, so on the next loop the False sequence will be
executed.
page 24 of 28
The first sequence reads the State register (address 3) and if the acquisition is ready the next
sequence is executed. It writes into the Acquisition register to read the acquire data. In the last
sequence it reads the bytes at the serial port (DATA).
Acquired data is separated from received bytes and they are concatenated with shift registers in
vectors that rebuilds the signals on each channel (CH0 to CH7).
The user can change the acquisition parameters and restart the acquisition by pressing the RUN
button. The whole process will be resumed.
page 25 of 28
Discussion
Problems Encountered
The problems I've encountered are:

- vivado interface is to much complicated than ISE Design,and we have problem with that.
- we work in ise because it's more accessible
- we try to import all project in vivado but doesn't work
- i can't find a solution for that
Marketability
we have a page on facebook where we describe this project
page 26 of 28
Community Feedback
References
https://reference.digilentinc.com/_media/cmod_a7/cmod_a7_rm.pdf
https://www.xilinx.com/support/documentation-navigation/development-tools/hardware-development/ISE-design-
suite.html?resultsTablePreSelect=documenttype:SeeAll#documentation
http://www.fpga4fun.com
page 27 of 28
Appendix A: {Name of Source Code File}

Insert text here.
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{Logic Analyzer}

Submitted for the 2018 Digilent Design Contest Europe

GHEORGHE ASACHI TECHINCAL UNIVERSITY OF IASI

Advisor: Zet Cristian

The general block diagram is described below:

Digilent Products Required

For this project, we used two hardware components:

Top Level I/O pins

Pin Name Pin Direction Description

Modules on the top level schematic

Module Name Description

FIFO Memory Block

Genbr - Transfer Rate Generation Block

Regdr - Data Receiving Register

Log_receptie - Logical block of reception

- an input signal representing the transmitted word (RX);

Logachizitie-The logical block of acquisition

The logic scheme is made from the following components:

log_transmisie - Transmission logic block

The Registry Block consists of 5 sub-blocks:

Registru de adresă (regadrr);

Registru de comandă (reg_comandă);

Registru de control (reg_control);

Registru de stare (reg_stare);

Registru care comandă logica de achiziție(regrk);

regdt-Block of the transmitted data register

- the first bit is the start bit;

The problems I've encountered are:

Appendix A: {Name of Source Code File}

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