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SN7489

64-BIT RANDOM-ACCESS READ/WRITE M E M O R Y


D 1 4 1 6 , DECEMBER 1 9 7 2 - R E V 1 S E D FEBRUARY 1984

• For Application as a"Scratch Pad" Memory SN7489 . J OR N PACKAGE

with Nondestructive Read-Out (TOP VIEWI

• Fully Decoded Memory Organized as 16 AO C . U , 6 H VCC


Words of Four Bits Each ME C 2 15 3 A 1
WE C 3 14 D A 2
• Fast Access Time . . . 3 3 ns Typical
01 C 4 13 J A3
• Diode-Clamped, Buffered Inputs Q1 : 5 12 U D 4
D2 C 6 11 3 Q 4
• Open-Collector Outputs Provide Wire-AND Q2 C 7 10 H D 3
Capability GND C 8 9 ] Q3
• Typical Power Dissipation . . . 3 7 5 m W

• Compatible with Most TTL Circuits logic symbol

description RAM 16X4


111
AO
This 6 4 - b i t a c t i v e - e l e m e n t m e m o r y is a (15|
monolithic, high-speed, transistor-transistor logic A1
(14)
(TTL) array of 64 flip-flop memory cells organized A2
(13)
in a matrix to provide 16 words of four bits each. A3
Each of the 16 words is addressed in straight m e ^ L
binary w i t h full on-chip decoding. T77F (31 -Cs,

The buffered memory inputs consist of four (4) 1 >1


address lines, four data inputs, a write enable, ^ ^ (5)
and a memory enable for controlling the entry A, 2D A, 1. 3 | ~
(61 ^ (7)
and access of data. The memory has open- •2 - Q2
collector outputs w h i c h may be wired-AND (101 ^ (9)
03- • Q3
connected t o permit expansion up to 4 7 0 4 (12) ^ (111
D4 - • Q4
words of N-bit length w i t h o u t additional output
b u f f e r i n g . A c c e s s t i m e is t y p i c a l l y 3 3
nanoseconds; power dissipation is typically 3 7 5
milliwatts.

FUNCTION TABLE

ME WE OPERATION CONDITION OF OUTPUTS


L
L
L
H
Write
Read
Complement of Data Inputs
Complement of Selected Word
§
V)

H L Inhibit Storage Complement of Data inputs <


High
cc
H H Do Nothing

w r i t e operation
Information present at the data inputs is written into the memory by addressing the desired w o r d and holding
both the memory enable and write enable l o w . Since the internal output of the data input gate is common
to the input of the sense amplifier, the sense output will assume the opposite state of the information
at the data inputs w h e n the write enable is low.

read operation

The complement of the information which has been written into the memory is nondestructively read out
at the four sense outputs. This is accomplished by holding the memory enable l o w , the write enable high,
and selecting the desired address.

• . Copyright © 1 9 8 5 , Texas Instruments Incorporated

TEXAS ^
INSTRUMENTS
POST OFFICE BOX 225012 • D A L L A S , T E X A S 75265
SN7489
64-BIT RANDOM-ACCESS READ/WRITE M E M O R Y

logic diagram

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M E M O R Y CELLS
BIAS NETWORK

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5-4 TEXAS ^
INSTRUMENTS
POST O F F I C E B O X 2 2 5 0 1 2 • D A L L A S , T E X A S 75265
SN7489
64-BIT RANDOM-ACCESS READfWRITE MEMORY

s c h e m a t i c s of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF A L L OUTPUTS

• c

Data Inputs: R e q = 6 k n NOM


A l l others: R a a = 4 k l i NOM

absolute m a x i m u m ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V c c ( s e e N o t e 1) 7 V
I n p u t v o l t a g e ( s e e N o t e 1) 5.5 V
H i g h - l e v e l o u t p u t v o l t a g e , V o H < s e e N o t e s 1 a n d 2) 5.5 V
Operating free-air t e m p e r a t u r e range 0 ° C to 70 °C
Storage temperature range - 6 5 ° C to 150°C

NOTES: 1. Voltage values are with respect to network ground terminal.


2. This is the maximum voltage that should be applied to any output when it is in the off state.

recommended operating conditions

MIN NOM MAX UNIT


Supply voltage, V c c 4.75 5 5.25 V
Width of write-enable pulse, t w
Setup time, data input w i t h respect to write enable, t s u (see Figure 1)
40
40
ns
ns
5
(ft
Hold time, data input with respect to write enable, th (see Figure 1) 5 ns
Select input setup time with respect to write enable, t s u 0 ns
Select input hold time after writing, th (see Figure 1) 5 ns <
Operating free-air temperature, T ^ 0 70 °C
cc

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POST O F F I C E BOX 2 2 5 0 1 2 • D A L L A S , T E X A S 75265
SN7489
64-BIT R A N D O M ACCESS READfWRITE M E M O R Y

electrical characteristics over recommended operating free-air temperature range


(unless otherwise noted)
PARAMETER TEST CONDITIONS' MIN TYP* MAX UNIT
V|h High-level input voltage 2 V
V||_ Low-level input voltage 0.8 V
V|k Input clamp voltage Vcc = MIN- l| = - 1 2 mA -1.5 V
V c c = MIN. V|H = 2 V,
'OH High-level output current 20 mA
V|L = 0 . 8 V. VQH = 5-5 V
V C C = MIN. V | H = 2 V, lOL = 12 mA 0.4
N/ql Low-level output voltage V
V|L = 0.8 V |QL = 16 mA 0.45
Input current at maximum
V c c = MAX, v
l = 5.5 V 1 mA
'' input voltage
M A X v 2 4 v
l|H High-level input current Vcc = ' l = 40 tiA
l|l_ Low-level input current VCC = MAX, V| = 0 . 4 V -1.6 mA
'CC Supply current V c c = MAX, See Note 3 75 105 mA
V c c = 5 V, V o = 2.4 V,
C0 Off-state output capacitance 6.5 PF
f = 1 MHz

tpor conditions shown as MIN or M A X , use the appropriate value specified under recommended operating conditions.
* All typical values are at V c c = 5 V, T a = 25 °C.
NOTE 3: I c c ' s measured with the memory enable grounded, all other inputs at 4 . 5 V, and ail outputs open.

switching characteristics. V c c = 5 V, T a = 25 °C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Propagation delay time, low-to-high-level
26 50
output from memory enable
ns
Propagation delay time, high-to-low-level
33 50
^ ^ output f r o m memory enable C L = 30 pF,
Propagation delay time, low-to-high-level R L I = 300 a
tpi h 30 60
output from any address input R l 2 = 6 0 0 a,
ns
Propagation delay time, high-to-tow-level See Figure 1
35 60
output from any address input
Sense recovery time Output initially high 39 70
tCB ns
after writing Output initially low 48 70
SN7489
64-BIT RANDOM-ACCESS READ/WRITE M E M O R Y

PARAMETER MEASUREMENT INFORMATION

Vcc

^ R L 1 - 300 SI

From output
under test
_ L c L = 30pF L2 = 600 Ji
' T s (See Note B) ?

LOAD CIRCUIT

3V
MEMORY
\ J
ENABLE + 1.5V TTT-SV

IN 1-\ OV

DK
ANY
r~
IS V
ADDRESS

I
/|\
N—»{-<PLH
k—Ph'PHL
ANY
V VOH
f
OUTPUT 1.5 V
v \ L v o t
O L
Write enable is high.
READ CYCLE WRITE CYCLE FROM WRITE ENABLE

NOTES: A. The input pulse generators have the following characteristics: t r < 10 ns, tf s 10 ns, PRR = 1 MHz, Z o u t = 50 [2.
B. C[_ includes probe and jig capacitance.

FIGURE 1-SWITCHING CHARACTERISTICS

CO

<
CC

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POST O F F I C E BOX 225012 • D A L L A S , T E X A S 75265
SN7489
64-BIT RANDOM-ACCESS READ/WRITE M E M O R Y

TYPICAL CHARACTERISTICS

INPUT CURRENT PROPAGATION DELAY TIME


vs vs
INPUT VOLTAGE FREE-AIR TEMPERATURE

Vcc = 5 V
_ T A = 25°C.

DATA INPUTS-
<
E I
- A L L OTHER INPUTS. 01
E tPHL MEMORY ENABLE INPUT
K
3 —4 I I I I I
= tpLH SELECT INPUTS
I I I I I
- 6 rtpLH MEMORY ENABLE I N P U T _

- - 8

VCC - 5 V
-10 — C|_ = 3 0 p F -
RL = 3 0 0 n
-12 I
-1 0 1 2 3 4 10 20 30 40 50 60 70
V|—Input Voltage-V Ty\—Free-Air Temperature—°C

FIGURE 3

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POST O F F I C E BOX 2 2 5 0 1 2 • D A L L A S , T E X A S 75265

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