DESIGN AND IMPLEMENTATION OF FAULT

TOLERANT NETWORK ON-CHIP BRAIN MACHINE

INTERFACE

A PROJECT REPORT

Submitted by

K.BHARATHI

M.MADHUBALA

M.KEERTHIKA

in the partial fulfillment for the award of the degree

of

BACHELOR OF ENGINEERING

in

ELECTRONICS AND COMMUNICATION ENGINEERING

MEENAKSHI COLLEGE OF ENGINEERING

ANNA UNIVERSITY :: CHENNAI 600025

MARCH 2019
 ANNA UNIVERSITY : CHENNAI 600 025

BONAFIDE CERTIFICATE

Certified that this project report “DESIGN AND IMPLEMENTATION OF

FAULT TOLERANT NETWORK ON-CHIP BRAIN MACHINE
INTERFACE “is the bonafied work of “BHARATHI.K (311415106011) ,
KEERTHIKA.M (311415106029) and MADHUBALA.M (311415106032)”
who carried out the project work under my supervision.

SIGNATURE SIGNATURE

Mr. N. Prem Kumar,M.E,(Ph.D) Ms. N. Thendral, M.E,(Ph.D)

HEAD OF THE DEPARTMENT SUPERVISOR

Professor Assistant Professor

Department of ECE Department of ECE

Meenakshi College of Engineering Meenakshi College of Engineering

West K.K. Nagar, Chennai 78 West K.K. Nagar, Chennai 78

Submitted for the Anna University Project Viva Voice held on

Internal Examiner External Examiner

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 ACKNOWLEDGEMENTS

We express our sincere thanks and owe profound gratitude to our beloved
managing trustee Thiru.A.N.RADHAKRISHNAN, M.A., D.COM., our
honourable principal Dr. G. DEENADAYALAN., M.E.,Ph.D., Professor for
their permission to work on this project.

We take this opportunity to express our thanks to the Head of the Department,
Electronics and Communication Engineering Mr.K. PREM KUMAR, M.E.,
(Ph.D.), Professor for his consent to carry out this project , encouragement during
the course of the project and providing all the facilities to complete this project
suceesfully.

We extend our sincere thanks and deep sense of gratitude to our project guide
Ms.N.Thendral, M.E., Ph.D., Assistant Professor for providing us with the
necessary inputs and guidance to complete this project within the stipulated time.

We are indebted to the project co-ordinators Ms.D. Satheeshwari, M.E.,(Ph.D.),

Assistant professor and Mr.S.M. Sivaraman, M.Tech., (Ph.D.), Assistant
Professor who provide us with valuble suggestion during the review of our
project.

We wish to thank all the teaching and non-teaching staff of the Electronics and
Communication Engineering Department for their constant support throughout
the duration of this project.

Finally,we owe thanks to the almighty for his grace and our beloved parents for
their prayers in making this project a great success.

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 ABSTRACT

Scalable system on chip created a big impact in System On Chip ASIC

applications. We present a comprehensive analysis of on-chip traffic patterns

generated by the distributed computing-based STF model performing Brain

Machine Body Interface analysis. Network-on-chip (NoC) is one of the

possibilities to overcome some of the on-chip communication problems. In such

NoC-based systems, the communication is achieved by routing packets through

the network infrastructure rather than routing global wires. In the existing

system a machine learning-based algorithm to efficiently design large-scale on-

chip interconnection networks running BMBI models and algorithms. We

develop a traffic- pattern up-scaling algorithm that is able to scale a given

traffic pattern to any larger system size while keeping the key traits intact. In

the proposed system, a reliable fault tolerant network on chip architecture is

designed to ensure the fault free soc platform in VLSI chips. These architecture

enhance the Artificial intelligence applications such as traffic control, CNC

machine control, automation of robots . NoC platform provides also

additional flexibility to tolerate faults and guarantees system reliability.

Multiple SOC can be controlled through one Fault free network on chip.

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 LIST OF FIGURE

FIG NAME PAGE NO

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