90 (IJCNS) International Journal of Computer and Network Security,

Vol. 2, No. 8, August 2010

A Low Power High Gain Folded-Cascode CMOS

Op-Amp with Slew Rate Enhancement Circuit for
100mW 10-bit 50MS/s High Speed ADC Designed
in 0.18um CMOS Technology
Bhanu pratap singh dohare1, D.S.Ajnar2 and P.K.Jain3
1
Electronics & Instrumentation Engineering Department,
S.G.S.I.T.S. 23, Park Road, Indore, M.P. India-452003
bhanuecvlsi@gmail.com
2
Electronics & Instrumentation Engineering Department
S.G.S.I.T.S. 23, Park Road, Indore, M.P. India-452003
dajnar@sgsits.com
3
Electronics & Instrumentation Engineering Department
S.G.S.I.T.S. 23, Park Road, Indore, M.P. India-452003
pramod22_in@yahoo.com

Abstract: This work describes the design and Simulation of
high speed, high gain and low power fully differential op-amp
with specifications 110dB DC open loop Gain, Phase margin 72
deg and Unity Gain Bandwidth 822MHz .Input referred noise is
about 8nV/Hz@10MHz. Folded-cascode op-amp with positive
slew rate 35V/ns & negative slew rate 28V/ns .The settling time
is 3.5ns and the op-amp power consumption 2.8mW with
supply voltage +1.2/-1.2,This design has been implemented in
0.18um UMC mixed signal CMOS Technology using Cadence.
The op-amp is designed for sample-and-hold stage of 100mW
10-bit, 50MS/s high speed ADC. With speed optimization the
0.488% settling time is 3.5ns. This design utilizes Gain-Boosting
Technique, which is suitable for low supply voltage applications,
has been used to achieve high gain. Common mode feedback
(CMFB) is used to stable the designed op-amp against
temperature. Three fully differential folded cascode op-amps
have been used in this designing, one for main op-amp and
others for gain-boosting techniques. The two fully differential
folded-cascode. Op-Amp have continuous time with CMFB
which is used as Gain-Boosting techniques to increase the open
loop gain of the main Gain-Boosting. A slew rate enhancement
circuit is introduced for improving the non symmetric slew rate
of the output stages.
Keywords: Gain-Boosting, slew rate enhancement, CMFB.
1. Introduction
In high performance analog integrated circuits, such as
switch-capacitor filters, delta-sigma modulators and pipeline
A/D converters, op amps with very high dc gain and high
unity-gain frequency are needed to meet both accuracy and
fast settling requirements of the systems. In application of
pipelined analog-to-digital (A/D) converters, the
requirement for high speed and high accuracy operational
amplifiers (op-amps) are essential. The speed and accuracy
criteria are determined by the settling behavior of the op-
amps. Fast settling mainly depends on the unity gain
frequency while high settling accuracy is due to high DC
gain. The realization of high speed and high accuracy op-
amps has proven to be very challenging task. Optimizing
the circuit design for both requirements leads to conflicting
demands [1]. A single-stage folded cascode topology is a
popular approach in designing high speed op-amps. Besides
large unity gain frequency, it offers large output swing.
However, it has limitation to provide high DC gain which is
required for high settling accuracy. In 1990, Bult and
Geelen proposed the folded cascode op-amp with gain
boosting technique [3]. This technique help to increase the
op-amp DC gain without sacrificing the output swing of a
regular cascade structure [3]. The pushing up the doublet
can raise stability problem [5], [6]. Based on that, this paper
presents a simple but robust optimization design method; a
sample fully differential gain-boosted folded-cascode op
amp was also designed in 0.18um mix-signal CMOS
process with 1.2V power supply. Purpose of this paper is to
discuss design consideration when utilizing gain boost
cascade op-amp in the sample-and-hold (SHA) stage of
100mW 10-bit 50Ms/s Pipeline A/D converter. This paper is
divided into three additional sections. The gain boosting
technique is explained in section 4. And the circuit
frequency behavior is analyzed in section 5. In section 2, the
circuit implementation with 0.18um CMOS Process is
presented. The simulation results are given and discussed in
section 6. Finally, the conclusions are drawn in section 7.
2. Design of Gain Boosted Folded Cascode Op-
Amp
In this section, the implementations of the main op-amp and
the gain enhancement stages are discussed. A general
method of designing a pipeline A/D converter for minimum
power consumption was performed at the system level. This
results in a set of specifications for each stage in pipelined
A/D converter. The selected system architecture has a SHA
stage followed by eight 1.5bit residue gain stages and a 2-bit
flash stage. The op-amp has to meet the specifications for
 (IJCNS) International Journal of Computer and Network Security, 91
Vol. 2, No. 8, August 2010

the SHA as shown in Table 1. Since regular cascode device parameters related to channel length modulation
can not meet these specifications, gain boost cascode respectively for NMOS and PMOS devices. Taking the
topology has been chosen to meet both the high gain and complementarily between the transistors M4 and M6 into
high bandwidth requirements. Fully differential folded- account:
cascode op-amps have been adopted in this design, one for The gain expression becomes:
main op amp, and the others for auxiliary op amps. The
complete implementation is shown in Figure.2.Because the
gain-boosted op amp will be used in a closed-loop The unity gain frequency of the OTA is given by the
configuration, in order to minimize the virtual ground expression:
parasitic that reduces feedback factor, a NMOS differential Table 2: Design parameters and specifications
pair is chosen as input stage in the main op-amp. As for the Specifications Values
two auxiliary op amps, there is not any difference except f(MHz) 340
their input stages. The auxiliary op amp A2 is shown in ID(μA) 30
Figure.3 and Al is not shown again for its similarity to A2. Channel length(μm) 0.18
The ideal effect of the auxiliary op amp is to increase the AV(dB) 82
output impedance of the main op amp by auxiliary times so
CL(Pf) 0.1
as to improve the dc gain of the main op amp by the same
Vdd +1.2/-1.2
times. At the same time, the dominant pole of the main op
amp is pushed down by auxiliary times, where auxiliary is Parameters Values
the dc gain of the auxiliary op amp. As long as the unit-gain gm9,10/ID(V-1) 8
bandwidth of the auxiliary op amp is designed to be larger ID(W/L)9,10(μA) 0.86
than the -3dB bandwidth of the main op-amp the high- g,m4/ID(V-1) 6
frequency performance of the main op amp will be ID(W/L)4(μA) 1.65
unchanged, i.e. the gain-boosted op amp has the same high- W9,10(μm) 35
frequency performance as that of the main op amp. In fact, W1,2,3,4(μm) 18
the gain-boosting technique can potentially raise two W5,6,7,8,11,12(μm) 6
significant problems for the time-domain performance of the
gain-boosted op amp, i.e. doublet and instability.
4. Gain Boosting Technique
Table 1: Op-amp specification for SHA stage Figure 1 illustrates a gain boost cascade topology where
Parameters Specifications transistor MI is an input device, M2 a cascode device and
Stage capacitor(Cf) 1.2Pf
M3 a gain boost device. M3 drives the gates of M2 and
Load capacitor 1.9Pf forces the voltage at nodes X and Y to be equal. As a result,
Feedback factor 0.9 voltage variations at the drain of M2 will affect the voltage
Settling time 3.5ns at node X to a lesser extent because the gain boost device
DC gain 72dB regulates this voltage [3]. Figure. 1 Gain Boost cascode
Gain bandwidth(GBW) 326MHz topology The addition of gain boost device with open loop
Phase margin(PM) 70degree gain, Afb, provides a small signal output resistance
Input transistor current 0.72mA approximately Afb times larger than that of a regular
cascode [4]. Through this technique, the output resistance
3. Optimum Technology OTA Architecture and gain can be increased by the gain of the gain boost
Several fundamental issues exist when selecting an optimal device without adding more cascade devices. However,
architecture for the operational transconductance amplifier. transient response from such an op-amp is degraded by the
This choice aimed both at large gain and large bandwidth presence of pole-zero
performances. The folded cascode OTA is shown in Figure.
3 [2 - 4]. The name “folded cascode” comes from folding
down n-channel cascode active loads of a diff-pair and
changing the MOSFETS to p-channels. This OTA, like all
OTAs, has good PSRR compared to the operational
amplifier. To understand the operation of the folded cascode
OTA, this last has a differential stage consisting of PMOS
transistors M9 and M10 intend to charge Wilson mirror.
MOSFETS M11 and M12 Provide the DC bias voltages to
M5- M6-M7-M8 transistors. The open-loop voltage gain is
given by:
Figure 1. Gain boosting cascode topology
Where gm9, gm4 and gm6 are respectively the
transconductances of transistors M9, M4 and M6. ID is the doublet [5]. This doublet appears as a slow exponential term
bias current flowing in MOSFETS M4, M6, and M9. Like, in the step response of the op-amp, thus degrading the total
CL is the capacitance at the output node. λN and λP are the settling time drastically and will discussed further in the
analysis section.
92
Figure 2. Fully differential gain-boosted folded-cascode op
amp with CMFB
Figure 3. Fully differential folded-cascode amplifier A2 with
CMFB
5. Settling Response Analysis
To understand the effect of pole zero doublets on slow
settling behavior, the transfer function of the gain-boosting
technique is derived using small signal model as shown in
Figure 4.
Figure 4. Small signal model
Figure 4. Small signal model the capacitors C1 through C3
are the equivalent parasitic capacitance of the MOS
transistors at nodes X and Y. Meanwhile CL is the load
capacitance at output node. To simplify the analysis,
parasitic drain-to-gate capacitor C4 of M2 is broken into its
Miller equivalent at node X and at output node. This Miller
capacitance is included in the value of parasitic capacitor C2
at node X and value of capacitor CL at output node.
(IJCNS) International Journal of Computer and Network Security,
Vol. 2, No. 8, August 2010
Figure 5. Pole and zero locations
CMFB circuit is indispensable in fully differential
operational amplifier. Conventional dynamic SC-CMFB
circuit, which is shown in Figure. 2, is adopted in the main
op amp, for this CMFB circuit can save static power
consumption and the common mode voltage sense circuit
does not limit the output swing of the op amp. However, the
capacitors in SC-CMFB should be elaborately selected such
that these capacitors will not over-load the main op amp or
be affected by the charge injection of the switches. Although
the SC-CMFB circuit has many advantages described above,
it is not appropriate for the two auxiliary op amps. On the
one hand, the load capacitances of the two auxiliary op
amps are small, as a result, the capacitors in SC-CMFB will
smaller than them, and the charge injection of the switches
will decrease the accuracy of the circuit. One the other hand,
the output of each auxiliary op amp does not need high
swing. Therefore, two continuous-time CMFB circuits are
used. The CMFB circuit for A2 is shown in Figure. 3. The
CMFB circuit of Al is not shown, for it is similar to the one
of A2.
6. The Simulation Results
With the design process described above, a single stage fully
differential gain-boosted folded-cascode op amp was
designed and implemented in UMC 0.18um mix-signal
process with 1.2V power supply. The step response is
simulated by a closed-loop configuration Shown in Fig. 5.
Here, both input capacitor C1 and feedback capacitor Cf are
l pF, while load capacitor CL is 4pF. The Cp represents
parasitic capacitances at the input of the op amp, which is
0.185pF.
Figure 6. Frequency Response (bode plot)
Figure 7. Slew rate performance
 (IJCNS) International Journal of Computer and Network Security, 93
Vol. 2, No. 8, August 2010

[3] Mrinal Das, "Improved Design Criteria of Gain-

Figure 8. Relationship between settling time &Cc
Boosted CMOS OTA with High-Speed
Optimizations", IEEE Trans. on Circuits and Systems
II Vol. 49, No. 3, March 2002, p. 204-207.
[4] K. Bult and G Geelen, "The CMOS gain-boosting
technique", Analog Integrated Circuits and Signal
Processing, Vol. 1, No. 2, Oct. 1991, p. 119-135.
[5] European Industry Association (EICTA) MBRAI-02-
16 v1.0 (2004-01): “Mobile and Portable DVB –T
Radio Access Interface Specification”, 2004.
[6] P. Bogner, “A 28mW 10b 80MS/s pipelined ADC
in0.13μm CMOS”, Proc. ISCAS’04, vol. 1, pp. 17-
20,2004

Authors Profile

Bhanu Pratap Singh Dohare received the B.E.

degree in Electronics and Communication
Engineering from R.G.P.V. Bhopal in 2008 and
M.Tech in Microelectronics and VLSI Design
from S.G.S.I.T.S. Indore, India in 2010. Recently
he is working with a analog filter design and
analysis.
Figure 9. Differential output DC swing versus input voltage
(vin+ only) under different power supplies. D.S.Ajnar received the B.E. degree in Electronics
and Communication Engineering from D.A.V.V.
University, India in 1993 and M.E. Degree in
Table 3: Simulated Performance Digital Techniques & Instrumentation
Engineering from Rajiv Ghandhi Technical
Parameters Simulated results University Bhopal, India in 2000. He has been
DC gain 110 dB working in teaching and research profession since
1995. He is now working as Reader in Department of Electronics
Unity gain frequency 821 MHz & Instru. Engineering of S.G.S.I.T.S. Indore India. His interested
Phase margin 70 degree field of research is to Design the analog filter and Current-
Conveyor.
Power dissipation 7.8 mW
Settling time 3.7 ns P.K.Jain received the B.E. degree in Electronics
Slew rate 35V/ns,28V/ns and Communication Engineering from D.A.V.V.
University, India in 1987 and M.E. Degree in
Differential output swing 2 Vp-p
Digital Techniques & Instrumentation
Engineering from Rajiv Ghandhi Technical
7. Conclusions University Bhopal, India in 1993. He has been
A single-stage folded cascode gain-boosted CMOS OTA has working in teaching and research profession
been designed and simulated using 0.18um CMOS since 1988. He is now working as Reader in Department of
Electronics & Instru. Engineering of S.G.S.I.T.S. Indore India. His
technology. In this design, a single-transistor was applied as
interested field of research is analog cicuit design.
gain-boost device. Care has been taken in selection of the
current values in both the cascode device and the gain boost
device to ensure good settling time performance while
maintaining the gain and bandwidth of the op-amp. The
designed op-amp fulfills the stringent specifications of SHA
stage of pipelined A/D converter with minimal additional
power consumed.
References

[1] K. Bult and G Geelen, "A fast-settling CMOS op amps

for SC circuits with 90-dB DC gain", IEEE Joumal o
Solid-State Circuits, Vol. 25, No. 6, Dec. 1990,
p.1379-1384.
[2] B.Y. Kamath, R. G Meyer and P. R. Gray,
"Relationship Between Frequency Response and
Settling Time of Operational Amplifiers", IEEE
Journal of Solid-State Circuits, Vol. SC-9, No. 6,
Dec. 1974, p. 347-352..