N/P-Channel MOSFET

Fabrication
By
Assoc. Prof Dr. Uda Hashim
School of Microelectronic Enginnering
KUKUM
Test Insert
and
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Metal 2
Passivation

Planarisation
AlSiCu

BPSG
Spacer

FOX FOX

LDD
Arsenic Implant
BF2 S/D Implant
As+ S/D Implant
N-Well P-Well N-Well
Capacitor
PMOS NMOS
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P+ Substrate
 The making of transistor
• Circuit design
• Mask/layout design
• Mask making and artwork
• Fabrication process
• Device testing – for parametric and
functional test
• Packaging and Reliability Test
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Mask Design

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 MOSFET Masking Step
• Mask 1: Source Drain Mask
• Mask 2: Gate Mask
• Mask 3: Contact mask
• Mask 4: Metallization Mask

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 Introduction
• Mask design is very important before fabrication
process can be done.
• Design rules must be followed to prevent defect in
the process.
• In this design, gate length is varied from 30um,
50um, 100um, 150um, 200um and 300um.
• Different gate length will have different gate mask
and different distance from source to drain.
• The smaller the gate size, the better the transistor in
speed.

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Circuit, layout and cross section of NMOS
transistor
• In NMOS design, NMOS
circuit is transferred to
layout design.
• Then, mask can be design to
fabricate NMOS transistor.

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 MASK 1: Source Drain Mask
• Mask 1 is used to control
the heavily phosphorus
doped and create the
source and drain region of
the n_channel device.
Layout 1: Source and Drain

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 Mask 2: Gate Mask
• Mask 2 is used to remove
the thick oxide layer and
grow a very high quality
of thin oxide.
Layout 2: Layout 1 and gate

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 Mask 3: Contact mask
• Mask 3 is used to pattern
the contact holes.
• Etching will open the
holes.
Layout 3: Layout 2 and contact

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 Mask 4: Metallization Mask
• Mask 4 is used to pattern the
connection.
• The uncovered Aluminum
film will be removed during
etching process.

Layout 4: Layout 3 and metallization

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Mask Design using AutoCAD

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 Mask Design Step
• Step 1: Set frame and wafer size dimension
• Step 2: Design alignment mark
• Step 3: Design source and drain mask
(Mask 1) block and duplicate to the
whole wafer.
• Step 4: Design gate mask (Mask 2) block
and duplicate to the whole wafer.
Then, inverse the alignment mark to
change the polarity.
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• Step 5: Design contact mask (Mask 3) block
and duplicate to the whole wafer.
• Step 6: Design Metallization mask (Mask 4)
block and duplicate to the whole
mask.
• Step 7: Print on transparency film using high
resolution printer.

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 Step 1: Set frame and wafer size dimension

• The frame size is set to 20” x

12” (A4 paper size).
• The wafer diameter is set to
4” and the wafer block is set
to 6” x 6”.
• Then the design unit is set to
millimeter or micron depend
on the designer’s
convenience.

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 Step 2: Alignment Mark design
• Alignment mark is used to
align wafer between layer
to layer during the
fabrication process.
• First, design the alignment
block.
• Then, design the cross an
insert it inside the block.

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 Step 3: Design source and drain mask
• First, design the mask block.
• Then, design the source and
drain region which is
uncovered and designed
with desired dimension.
• At this mask, the polarity of
the alignment block is
reversed. The cross is open
and the block is opaque.

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 Step 4: Design gate mask
• The red block is the gate
mask, it is drawn before the
white area.
• The white area on the red
layer is the gate region.
• Maintain the mask design

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 Step 5: Design contact mask
• The brown block is the gate
mask.
• The white rectangle is the
contact region.
• Maintain the mask design

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 Step 6: Design metallization mask
• The Metallization mask is
used for routing purposes.
• The unprotected region will
be etched away whereby the
exposed Aluminum area
will be removed.
• Maintain the mask design

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Q&A

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Transistor Fabrication
(Step by Step Process)

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 n-channel MOSFET Fabrication

The device fabrication steps are shown for n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistor
(FET). All photolithography processes are shown by means of animation. The steps shown here are the most detailed
and serve as basis for the next few applets showing the device fabrication. A lightly doped p-type Si wafer

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 Oxide Grown

For NMOS process, the starting material is a P-type lightly doped, <100>-oriented, polished silicon wafer. The first step is
to form the SiO2 layer(0.5 - 1um thick) by thermal oxidation. The oxidation temperature is generally in the range of 900 -
1200 degree C, and the typical gas flow rate is about 1cm/s.

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 Photoresist Applied

Following oxidation, several drops of positive Photoresist(e.g. Shipley S1818) are dropped on the wafer. The wafer
is spun at about 3000rpm to be uniformly spread out.After the spinning step, the wafer is given a pre-exposure
baking (80 - 100 degree C) to remove the solvent from the PR film and improve adhesion to the substrate.

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 PR Developed

Third step is to define the active area (Drain and Source regions) by photolithography.The PR layer not covered by the
mask undergoes a chemical change by UV light and is removed by the spraying the wafer with the developing
solution(e.g. Shipley MF319). The final remaining PR is a copy of the pattern on the mask. Finally,the wafer is rinsed and
spin-dried, and then baked again so that the PR can resist the strong acid used to etch the exposed oxide layer.

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 Oxdie Etched

For SiO2 etching, HydroFluoric(HF) acid is usually used because it attacks oxide, but not silicon
or PR. Therefore, the HydroFluoric(HF) acid etches away the oxide in the openings in the PR, and
stops at the silicon surface.

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 PR Removed

After SiO2 etching, PR is stripped by using either a solvent (Aceton) or a plasma oxidation,
leaving behind an insulator pattern that is the same as the opaque image on the mask.

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 Phosphorus Diffused

After stripping the PR,a two-step diffusion process is used to form drain and source regions, in which Phosphorus
predeposition is first formed under a Constant-Surface-Concentration Condition(CSCC) and then is followed by a
drive-in diffusion under a Constant-Total-Dopant Condition(CTDC). Finally, a thin layer of Phosphosilicate Glass
on the wafer is removed by HF

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 Field Oxide Grown

After the forming the drain and source regions, additional oxide layer is grown from thermal oxidation as before.
The Phosphorus spreads out by diffusion during this furnace operation, but the concentration are still much
higher than that of the substrate doping.

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 PR Applied

The second photolithography process is done to remove the oxide, defining a gate region. The same
procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing -
> Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

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 PR Developed

The second photolithography process is done to remove the oxide, defining a gate region. The same
procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing -
> Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

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 Oxide Etched

The second photolithography process is done to remove the oxide, defining a gate region. The same
procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing -
> Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

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 PR Stripped

The second photolithography process is done to remove the oxide, defining a gate region. The same
procedure (PR Drop ->Spinning ->Pre-Baking ->Mask Alignment->UV Exposure -> PR Developing -
> Rinsing and Drying -> Post-Baking -> Oxide Etching) as in Lithography #1 is used.

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 Gate Oxide Grown

After the second photolithography, a very thin gate oxide layer(a few hundred angstroms) is grown by
thermal oxidation.

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 PR Applied

The third photolithography process is done to remove the oxide, defining contact holes. The same
procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing
-> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

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 PR Developed

The third photolithography process is done to remove the oxide, defining contact holes. The same
procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing
-> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

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 Oxide Etched

The third photolithography process is done to remove the oxide, defining contact holes. The same
procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing
-> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

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 PR Removed

The third photolithography process is done to remove the oxide, defining contact holes. The same
procedure(PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure -> PR Developing
-> Rinsing and Drying -> Post-Baking -> Oxide etching) as in lithography #1 is used.

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 Aluminium Film Deposited

A metal such as Aluminum is then evaporated on the whole substrate surface(a few thousand
angstrom thick) under high-vacuum condition.This method is attractive because it is simple and
inexpensive and produces no ionizing radiation.The Al layer will form electrical contacts later.

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 PR Applied

The final lithography process is done to remove the Al-layer, defining a contact pattern. The same
procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR
Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

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 PR Developed
The final lithography process is done to remove the Al-layer, defining a contact pattern. The same
procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR
Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

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 Aluminium Interconnect Etched
The final lithography process is done to remove the Al-layer, defining a contact pattern. The same
procedure( PR Drop -> Spinning -> Pre-Baking ->Mask Alignment ->UV Exposure ->PR
Developing->Rinsing and Drying->Post-Baking ->Aluminum Etching) as in lithography #1 is used.

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 Completion of NMOS Fabrication
After the final PR stripping, all the NMOS fabrication steps are completed.

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Thanks

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