MINI PROJECT

CLOCK DIVIDER

EXP NO: 15 DATE:

BATCH MEMBERS

G.AJAY 211016106002
P.ABISHEIK 211016106001
M.AJAY KUMAR 211016106003
M.BLESSON SAVIOUR 211016106008
INTRODUCTION

Clock Divider is also known as frequency divider, which divides the input clock
frequency and produce ouput clock. In our case let us take input frequency as
50MHz and divide the clock frequency to generate 1KHz ouput signal.

In the block diagram, the counter increases by 1 whenever the rising edge of clk
arrives. It also resets its output to '0' when it reaches the constant number defined
in the constant block. The comparator compares the output of the counter with the
pre-defined constant and asserts EQ if the output of counter is equal to the pre-
defined constant. When EQ is asserted, the output of the clock divider flips.
Let's assume that the pre-defined number is 3, and the output of clock divider
(clk_div) is initialized to 0. It takes three clock cycles before the output of the
counter equals the pre-defined constant, 3. When it reaches 3, the output of clock
divider (clk_div) turns to 1, and the counter resets itself. It takes another three
cycles before the output of the counter equals the pre-defined constant, 3. When it
reaches 3 again, clk_div turns back to 0. So it takes 6 clock cycles before clk_div
goes to 1 and returns to 0 again. As a result, the frequency of clk_div is one sixth
of the frequency of original clk.
In this example, we are going to use this clock divider to implement a signal of
exactly 1 Hz frequency. First, we will need to calculate the constant. As an
example, the input clock frequency of the Nexys3 is 100 MHz. We want our
clk_div to be 1 Hz. So it should take 100000000 clock cycles before clk_div goes
to '1' and returns to '0'. In another words, it takes 50000000 clock cycles for
clk_div to flip its value. So the constant we need to choose here is 50000000. Now
we will start to describe the circuit:
SCHEMATIC DIAGRAM

SOFTWARE REQUIRED

 Xilinx ISE
 VERILOG CODE

1. module frequency_divider_by2 ( clk ,rst,out_clk );

2. output reg out_clk;
3. input clk ;
4. input rst;
5. always @(posedge clk)
6. begin
7. if (~rst)
8. out_clk <= 1'b0;
9. Else
10. out_clk <= ~out_clk;
11. end
12. endmodule

TEST BENCH

1. `timescale 1ns/100ps
2. module frequencydiv;
3. output reg clk;
4. output reg rst;
5. input wire out_clk;
6. frequency_divider_by2 freq1(clk,rst,out_clk);
7. initial
8. clk = 1'b0;
9. always
10. #10 clk = ~clk;
11. initial
12. begin
13. $monitor($time,"clk = %b,rst = %b,out_clk = %b",clk,rst,out_clk);
14. rst =0;
15. #20 rst =1;
16. #100 $finish;
17. end
18. initial
19. begin
20. $dumpfile ("frequencydiv.vcd");
21. $dumpvars (0,frequencydiv);
22. end
23. endmodule
And the result of the simulation.
0 clk = 0,rst = 0,out_clk = x
10 clk = 1,rst = 0,out_clk = 0
20 clk = 0,rst = 1,out_clk = 0
30 clk = 1,rst = 1,out_clk = 1
40 clk = 0,rst = 1,out_clk = 1
50 clk = 1,rst = 1,out_clk = 0
60 clk = 0,rst = 1,out_clk = 0
70 clk = 1,rst = 1,out_clk = 1
80 clk = 0,rst = 1,out_clk = 1
90 clk = 1,rst = 1,out_clk = 0
100 clk = 0,rst = 1,out_clk = 0
110 clk = 1,rst = 1,out_clk = 1
120 clk = 0,rst = 1,out_clk = 1

The waveform is here

CONCLUSION
This information is useful to invert the output clock at each of its rising edge. This module is
meant to be a complement of step sequencers or to be used to trigger events at regular beats. It
provides a way of clocking up to three step sequencers at various rates from a single external
master clock, the master clock rate can be divided by 1 (unchanged rate),2,3,4,5,6,7 or 8
independently on the three dividers.