M.Tech.

VLSI Design, Test and Manufacturing

Curriculum and Syllabus R2015

KALASALINGAM UNIVERSITY
Kalasalingam Academy of research and Education
Anand Nagar, Krishnankoil – 626 126.
Srivilliputtur (Via), Virudhunagar (Dt), Tamil Nadu.
M.Tech. Semiconductor Testing and Packaging Regulation R2015

M.Tech-VLSI Design, Test and Manufacturing

Curriculum and Syllabus
R2015

ECE Department Kalasalingam University Page 1

M.Tech. Semiconductor Testing and Packaging Regulation R2015

KALASALINGAM UNIVERSITY
Anand Nagar, Krishnankoil – 626 126.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

M.Tech – VLSI DESIGN, TEST AND MANUFACTURING

Curriculum
Semester I (17th August, 2015 to 30th Nov, 2015)

Subject
Subject L T P C
Code
ECE5301 Essentials of Circuit theory 2 0 1 3
ECE5302 Essentials of VLSI design 2 0 1 3
ECE5303 Semiconductor Physics and Device Modelling 2 0 1 3
ECE5304 Scripting Languages for VLSI Design
3 0 0 3
Automation
ECE5305 Digital Design 2 0 1 3
ECE53xx Elective I – System Architecture Design 3 0 0 3
ECE5381 CMOS Digital Design Laboratory 0 0 3 1
ECE5382 CMOS Analog and Mixed Signal Design
0 0 3 1
Laboratory
ECE5383 Seminar I 1 0 0 1
Total 15 0 10 21

Semester II (15th Dec 2015 to 15th May, 2016)

Subject
Subject L T P C
Code
ECE5306 Microsystems and Microengineering 3 0 0 3
ECE5307 Testing and Testability 2 0 1 3

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ECE5308 System and Device Packaging 3 0 0 3

ECE5309 SOC Design and Verification 2 0 1 3
ECE5310 Test Engineering – I 2 0 1 3
ECE53xx Elective II - VLSI Fabrication Technology ( 3 0 0 3
Industry Visit to Fab - SCL)
ECE5384 IC Test Laboratory 0 0 3 1
ECE5385 SOC Verification Laboratory 0 0 3 1
ECE5386 Seminar II 1 0 0 1
Total 16 0 9 21

Semester III (1st July, 2016 to 30th Nov, 2016)

Subject
Subject L T P C
Code
ECE63xx Elective-III – 3 0 0 3
ECE63xx Elective-IV – Test Engineering – II 3 0 0 3
ECE63xx Elective-V- Reliability Engineering 3 0 0 3
ECE6396 Project Work Phase –I - - 18 6
Total 9 0 18 15

Semester IV (15th Dec, 2016 to 15th May 2017)

Subject Subject L T P C
Code
ECE6397 Project Work Phase – II - - 36 10
Total - - 36 10

LIST OF ELECTIVES

Subject
Subject L T P C
Code
ECE5311 Systems Architecture Design 3 0 0 3
ECE5312 Low Power VLSI Design 3 0 0 3

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ECE5313 VLSI Fabrication Technology 3 0 0 3

( Industry Visit to Fab - SCL)
ECE5314 Hardware-Software Co-Design 3 0 0 3
ECE5315 Formal Verification 3 0 0 3
ECE5316 High level synthesis 3 0 0 3
ECE5317 CMOS RF Design 3 0 0 3
ECE5318 Three Dimensional Network-on-Chip 3 0 0 3
ECE5319 Electronic Product Design 3 0 0 3
ECE6311 Mixed signal IC Design 3 0 0 3
ECE6312 Three Dimensional IC Design 3 0 0 3
ECE6313 Reliability Engineering 3 0 0 3
ECE6314 Test Engineering – II 3 0 0 3
ECE6315 RTL to GDSII 3 0 0 3
ECE6316 Full Custom Design 3 0 0 3
ECE6317 Logic analysis and synthesis 3 0 0 3

L T P C
ECE5301-ESSENTIAL OF CIRCUIT THEORY
2 0 1 3
Regulation R2015
Description: To be able to analyse a circuit using both manual and computer based
methods.
To be able to specify and design an appropriate analogue filter for a given
application
Unit I Introduction 9
The s-plane and the Laplace domain The s-plane, the general complex exponential excitation
function, two-port networks, positive reak functions, positive semi-definite functions,
properties of RC networks, properties of LC networks.
Unit II State Variables 9
State variables and state space representation State-space, obtaining state variables and state
equations from transfer function, resistors, inductors and capacitors, formulation of state
equations by nodal and mesh analysis, energy functions, formulation of state equations using
energy functions.
Unit III Transformations 9
Transformations, canonical forms - eigen values Eigen values and eigen vectors, diagonal
matrices, the Jordan canonical form., Solution of network equations Solution of linear state
equations through Laplace transformation, solution of transient equations, networks with
sparse matrices.

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Unit IV Synthesis 9
Synthesis of analogue circuits Realisation of LC driving point functions, RC driving point
functions, RL driving point functions, synthesis of RLC circuits. Insertion power function
and reflection coefficient, Butterworth filters, Chebyschev filters, transformation to obtain
high-pass characteristics, band-pass and band-stop filters.
Active Filters Active filters using gyrators, active filters using NICs, the state variable filter,
switched capacitor filters.
Unit V Recent Trends in Circuit Theory 9
Modern trends in circuit analysis and design Automatic equation formulation - modified
nodal analysis, modelling of non-linear circuits - diodes and transistors, Spice, Tellegan's
theorem, sensitivity and robust design, automatic design and use of Artificial Intelligence.
Reference Books
1. John Bird, Electrical Circuit Theory and Technology, Routledge, Fifth Edition, 2013
2. I. D. Mayergoyz, Wes Lawson,Basic Electric Circuit Theory, Gulf Professional
Publishing, 1997
3. .Charles A. Desoer, Ernest S. Kuh, Basic Circuit Theory, Tata McGraw-Hill
Education, 2009

L T P C
ECE5302-ESSENTIALS OF VLSI DESIGN
2 0 1 3
Regulation R2015
Description: This course describes about the present and possible near future
processing technologies, delays, power and interconnects engineering of
CMOS, combinational and sequential circuit design, array sub systems
and special purpose systems
Unit I MOS transistor theory 9
CMOS logic, CMOS fabrication layout, Design partitioning, Logic design , circuit design,
physical design, MOS transistor theory, CV characteristics, Non ideal IV effects, DC transfer
characteristics, pitfalls and fallacies
Unit II CMOS processing technology and delay 9
CMOS design rules, CMOS process enhancement, and technology related CAD issues,
manufacturing issues. Delay –Transient response, RC delay model and linear delay model,
logical efforts of path, Timing analysis and delay fault models.
Unit III Power and Interconnect 9
Dynamic power, static power , energy delay optimization, Low power optimization ,
Interconnect – Wire geometry, Interconnect modelling, Interconnect Engineering, Logical
effort with wires, Robustness – variability, Reliability, Scaling, statistical Analysis of
variability, variation in tolerant design
Unit IV Circuit design using CMOS 9
Combinational circuit design – circuit families, circuit pitfalls, SOI circuit design, threshold

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circuit design, Sequential circuit design- sequential static circuits, circuit design of latches
and flip flops, static sequential element methodology, sequencing dynamic circuits.
Unit V System design using CMOS 9
Array sub systems – SRAM , DRAM, Read only memory, Serial access memory, CAM,
PLA, Robust memory design, Special purpose systems- Overview, packages and cooling,
Power distribution, clocks, PLLs and DLLs, I/Os, High speed links, random circuits
Reference Books
1. Neil H.E. Weste and David Mani Harris CMOS VLSI Design, A circuit and system
perceptive, PEARSON publication, 2011.
2. Douglas A. Pucknell and Kamran Eshraghian, BASIC VLSI Design., PHI publication,
2012.
3. Kiran V. G.and Nagesh H.R. Fundamentals of CMOS VLSI Design., Pearson, 2011.

ECE5303-SEMICONDUCTOR PHYSICS AND L T P C

DEVICE MODELLING 2 0 1 3
Regulation R2015
Description: This course describes behaviour & modelling of MOS transistors. In
addition to that it describes the MOSFET modelling and optimization.
Unit I Fundamentals of basic semiconductor theory 9
Energy band model, intrinsic semiconductor, extrinsic or doped semiconductor, electrical
conduction, PN junction at equilibrium, diode current-voltage characteristics, diode dynamic
behavior, real PN junction, diode circuit model, temperature dependent diode model
parameters, MOSFET structure, MOSFET characteristics, MOSFET scaling, hot-carrier
effects, VLSI device structures, MOSFET parasitic elements, MOSFET length and width
definitions, MOSFET .
Unit II MOSFET Capacitor and threshold voltage 9
Circuit models MOSFET capacitor with no applied voltage, MOS capacitor at non- zero bias,
capacitance of MOS structures, deviation from ideal C-V curves, anomalous C-V curve,
MOS capacitor applications, non uniformly doped substrate and flat band voltage, MOSFET
with uniformly doped substrate, non uniformly doped substrate, threshold voltage variations
with device length and width , temperature dependence of threshold voltage.
Unit III MOSFET model 9
Drain current calculations, Pao- Sah model, charges-sheet model, Piece-wise drain current
model for enhancement devices, drain current model for depletion devices, effective
mobility, short geometry models, impact of source –drain resistance on drain current,
temperature dependence of the drain current. Intrinsic charges and capacitances, charge-
based capacitance model, long channel charge model, short channel charge model,
limitations of the quasi-static model, small-signal model parameters
Unit IV Model parameter measurements 9
Substrate current model, gate current model, correlation of gate and substrate current,

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mechanism of MOSFET degradation, measure of degradation –device lifetime, impact of

degradation on circuit performance, temperature dependence of device degradation ,Data
acquisition , gate-oxide capacitance measurement, measurement of doping profile in silicon,
measurement of threshold voltage, determination of body factor, flat band voltage , drain
induced barrier lowering parameter, determination of sub threshold slope, carrier inversion
layer mobility measurement, determination of effective channel length and width,
determination of drain saturation voltage, measurement of MOSFET intrinsic capacitances,
measurement of gate overlap capacitance, measurement of MOSFET source/drain diode
junction parameter
Unit V Model parameter extraction using optimization method 9
Model parameter extraction, basics definitions in optimization, optimization methods, some
remarks on parameter extraction using optimization techniques, confidence limits on
estimated model parameter, parameter extraction using optimizer diode model, MOSFET
level1 model, MOSFET level2 model, MOSFET level 3 model, MOSFET level 4 model,
comparison of four MOSFET models, Statistical modeling and worst-case design parameters
Reference Books
1. Arora, N., “MOSFET Models for VLSI Circuit Simulation”, World scientific,2007.
2. Grasser, T., “Advanced Device Modeling and Simulation”, World Scientific Publishing
Company., 2003.
3. Fjeldly, T., Yetterdal, T. and Shur, M., “Introduction to Device Modeling and Circuit
Simulation”, Wiley-Interscience., 1997.
4. Selberherr, S., “Analysis and Simulation of Semiconductor Devices”, Springer-Verlag.,
1984.

ECE5304-SCRIPTING LANGUAGES FOR VLSI L T P C

DESIGN AUTOMATION 3 0 0 3
Regulation R2015
Description: Scripting languages are used for automating tasks of different EDA tools.
This course deals with programming with Scripting languages such as
PERL,CGI, JAVA script, TCL and other languages such as python, ruby
etc
Unit I Scripting Languages 9
Definition of script, Scripting Context, Shell scripts Overview of Scripting Languages –
PERL, CGI, VB Script, Java Script, Python, Ruby, and TCL
Unit II PERL, Interfacing 9
Operators, Statements Pattern Matching etc. Data Structures, Modules, Objects, Tied
Variables, Inter process Communication Threads, Compilation and Line Interfacing
Unit III Programming In PERL, TCL Basics 9
Debugger Internal and Externals Portable Functions, Extensive Exercises for Programming
in PERL, TcL language basics

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Unit IV Programming In TCL 9

Basic commands, Control constructs, Advanced constructs, File I/O, TcL application in
EDA tools, tk and wish, Example: Back-Annotating a Verilog module
Unit V Other Languages 9
Broad Details of CGI, VB Script, Java Script, Python, Ruby with Programming Examples
Reference Books
1.Randal L, Schwartz Tom Phoenix, ―Learning PERL, Oreilly Publications, 2011.
2. Tom Christiansen, Nathan Torkington, ―PERL Cookbook, Oreilly Publications, 2004.
3. Larry Wall, et.al., ―Programming PERL, Oreilly Publications, 2000.

L T P C
ECE5305- DIGITAL DESIGN
2 0 1 3
Regulation R2015
Description: The course covers the topics related to digital design for VLSI Engineer.
ANALYSIS OF CLOCKED SYNCHRONOUS
Unit I 9
SEQUENTIAL NETWORKS (CSSN)
Modelling of CSSN State Stable Assignment and Reduction, Design of CSSN, Design of
Iterative Circuits, ASM Chart, and ASM Realization.
Unit II STATIC AND DYNAMIC CMOS DESIGN, 9
OPTIMIZATION TECHNIQUES
Combinational circuit design, circuit families, static CMOS, ratioed circuits, Cascade voltage
switch logic, Dynamic circuits. Pass transistor circuits, Differential circuits. Combinational
network delay. Power and energy optimization sequential machine design styles. Rules for
clocking. Performance analysis
Unit III ANALYSIS OF ASYNCHRONOUS SEQUENTIAL 9
CIRCUIT (ASC)
Flow Table Reduction, Races in ASC, State Assignment, Problem and the Transition Table ,
Design of ASC, Static and Dynamic Hazards, Essential Hazards, Designing Vending
Machine Controller. Mixed Operating Mode Asynchronous Circuits, Sequencing static
circuits, Circuit design of latches and flip-flops, Static sequencing element methodology,
Sequencing dynamic circuits, Synchronizers.
Unit IV PROGRAMMABLE LOGIC DEVICES (PLDS) 9
Programmable gate arrays, Realization State machine using PLD, EPROM to Realize a
Sequential Circuit, Designing a Synchronous Sequential Circuit using a GAL, EPROM.
Xilinx series FPGAs, Altera complex PLDs, Altera Flex 10K series CPLDs, FPGA based
system design, FPGA fabrics.
Unit V DATAPATH AND ARRAY SUBSYSTEMS 9
Addition / Subtraction, Comparators, counters, coding, multiplication and division. SRAM,
DRAM, ROM, serial access memory, context-addressable memory.
Reference Books

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1. Donald G. Givone, Digital principles and Design, Tata McGraw Hill, 2002.
2. John M. Yarbrough, Digital Logic applications and Design, Thomson Learning,
3. Nripendra N. Biswas, Logic Design Theory, Prentice Hall of India, 2001.
4. Charles H. Roth Jr., Fundamentals of Logic design, Thomson Learning, 2004.
5. Weste etal. N.H.E., CMOS VLSI Design, Pearson Education, 3 rd Edition 2005.
6. Wolf. W., FPGA- based System Design, Pearson Education, 2004

ECE5381-CMOS DIGITAL DESIGN L T P C

LABORATORY 0 0 3 1
Regulation R2015
(Cadence/Synopsis/Mentor Graphics tools must be used.)
(Ability to understand and comprehend Datasheet, implement common devices in both
ASIC (simulation, synthesis, STA), FPGA implementation)
1. Write Verilog Code for the following circuits and their Test Bench for verification,
observe the waveform and synthesize the code with technological library with given
Constraints*. Do the initial timing verification with gate level simulation.
An inverter
Successive Approximation Register [SAR]
*An appropriate constraint should be given
2. The chip for this lab consists of an 8-bit multiplier that computes the result in four
pipeline stages. Signals A and B are the 8-bit inputs and result is the 16-bit product.
CLK and RESET are the clock and active-high synchronous reset, respectively. You
are expected to write a Verilog description of the design, verify its functionality and
synthesize it in for the highest frequency possible.
3. Create schematics, symbols, and layouts for an inverter and a 2-input NAND gate.
Using these symbols and layouts, create a schematic, symbol, and layout for a 2:1
MUX using 3 2-input NAND gates and 1 inverter. Perform design-rule-checks (DRC)
and a layout-vs.-schematic (LVS) check on the layouts of the inverter, 2-input
NAND, and 2:1 MUX. Then, get accurate propagation delays for the 2:1 MUX by
extracting parasitic capacitances from the layout and simulating the circuit
4. Bipolar gate Design - BiCMOS logic

SUGGESTED DESIGN PROJECTS FOR VLSI LAB

Arithmetic and Logic Subsystems:
A-1. Bit Slice ALU.
A-2. 6*6 Booth Multiplier
A-3. Incrementer/Decrementer
A-4. Comparator: of two n-bit numbers. (i.e. expandable architecture)
A-5. 4-bit Baugh-Wooley Multiplier
A-6. 8-bit Logarithmic Multiplier

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A-7. 4-bit Braun Multiplier

A-8. 4-bit Parallel Full Adder: with carry-look-ahead.
A-9. 8-bit Transmission-Gate Adder
A-10. 4-bit CLA Adder Using Cross-Coupled Domino Logic
A-11. 8-bit Carry Skip Adder
A-12. 8-bit Carry-Select Adder
A-13. 8-bit Brent and Kung Adder
A-14. CRC (cyclic redundancy checker)
A-15. 16-bit Fast 2’s Complement Converter
A-16. Fast 32-bit Parallel Comparator
A-17. 16-bit Serial-Parallel multiplier
Memory Subsystems:
M-1. Dual-Port Static Register
M-2. Static Random Access Memory: with cross-coupled inverters
M-3. Dynamic Random Access Memory: 3- or 4- transistor cells
M-4. Content Addressable Memory
M-5. Stack: Last-in, First-out Memory
M-6. Queue: First-in, First-out Memory
Control Subsystems:
C-1. Serial-to-Parallel or Parallel-to-Serial Converter
C-2. BCD-to-Binary or Binary-to-BCD Converter: for bit serial applications
C-3. 8-bit Barrel Shifter.
C-4. Pseudo-Random Sequence Generator: for Built-in self test.
C-5. 4-phase Clock Generator
Any other Innovative Idea/ Any Journal Paper Implementation

ECE5382-CMOS ANALOG AND MIXED L T P C

SIGNAL DESIGN LABORATORY 0 0 3 1
Regulation R2015
ANALOG DESIGN
1. Lambda calculation for PMOS and NMOS, FT calculation, Trans-conductance plots,
Single transistor amplifier
2. Design the following circuits: A single stage differential amplifier, Common Source
and Common Drain Amplifier with given specifications*, completing the design flow
mentioned below:
a. Draw the schematic and verify the following
i. DC Analysis
ii. AC Analysis
iii. Transient Analysis
b. Draw the Layout and verify the DRC, ERC

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c. Check for LVS

d. Extract RC and back annotate the same and verify the Design.
3. Design an op-amp with given specification* using given differential amplifier
Common source and Common Drain amplifier in library** and completing the design
flow mentioned below:
a. Draw the schematic and verify the following
i. DC Analysis
ii. AC Analysis
iii. Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
4. Design a 4 bit R-2R based DAC for the given specification and completing the design
flow mentioned using given op-amp in the library**.
a. Draw the schematic and verify the following
i. DC Analysis
ii. AC Analysis
iii. Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
MIXED SIGNAL DESIGN
5. For the SAR based ADC mentioned in the figure below draw the mixed signal
schematic and you verify the functionality by completing ASIC Design FLOW.
[Specifications to GDS-II]

6. Design and Implementation of any one of the following project using the backend
tool.

*Appropriate specification should be given.

**Applicable Library should be added and information should be given to the Designer.

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***An appropriate constraint should be given

References:
1. David A johns, Ken Martin, Analog Integrated Circuit Design, Wiley, 2008.
2. R. Gregorian and G.C Temes, Analog MOS Integrated Circuits for Signal Processing,
Wiley, 1986.
3. Roubik Gregorian, Introduction to CMOS OpAmp and Comparators, Wiley, 1999.
4. Alan Hastlings, The art of Analog Layout, Wiley, 2005.
5. Pr Gray and Rg Meyer, Analysis and Design of Analog Integrated Circuits, 5 th
Edition, Wiley, 2009.
6. Mohammed Ismail and Terri Fiez, Analog VLSI: Signal and Information Processing,
McGraw-Hill, 1994.
7. Geiger, Allen and Stradder, VLSI Design Techniques for Analog and Digital Circuits,
Tata McGraw-Hill Education, 2010.
8. Jan M Rabaey, Digital Integrated Circuits, 2nd Edition, Pearson Education, 2003.
9. Sung-Mo Kang, CMOS Digital Integrated Circuits, 3rd Edition, McGraw-Hill, 2003.

ECE5306-MICROSYSTEMS AND L T P C
MICROENGINEERING 3 0 0 3
Regulation R2015
Description: This course describes about the concepts of quantum mechanics, micro
electromechanical devices, fabrication process of Microsystems. In
addition it also deals with micro machine, transducers and case studies.
Unit I Fundamentals of MEMS fabrication 9
Overview of design of MEMS and NEMS, Biological and bio systems analogies, overview
of nano and microelectromechanical systems, application of micro and
nanoelectromechanical systems, micro and nanoelectromechanical systems, synergetic
paradigms in MEMS, MEMS and NEMS architectures, overview of basic processes,
microfabrication and micromachining of ICs, microstructures, and micro devices, MEMS
fabrication Technologies.
Unit II Devising and Synthesis 9
MEMS motion micro devices classifier and synthesis, nanoelectromechanical systems, to
modeling, analysis, and simulation, electromagnetic and its application for MEMS and
NEMS.
Unit III Micro Machines and transducers 9
Micromachines, synchronous Microtransducers, microscale permanent – magnet stepper
micro motors, piezo transducer, fundamentals of modeling of electromagnetic radiating
energy micro devices, classical mechanics and its application, thermos analysis and heat
equation
Unit IV Quantum Mechanics 9

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Atomic structures and quantum mechanics, molecular and nanostructure dynamics,

molecular wires and molecular circuits, Overview of microelectromechanical systems control
, lyapunov stability theory, control of microelectromechanical systems, intelligent control of
MEMS, Hamilton – Jacobi theory and quantum mechanic’s
Unit V Case studies 9
Design and fabrication , analysis of translation micro transducers, single, phase reluctance
micro motors : modeling , analysis and control, three – phase synchronous reluctance micro
motors, microfabrication, magnetization dynamics of thin films, microstructures and
microtransducers with permanent magnets: micro mirror actuators, reluctance
electromagnetic micro motors, micro machined polycrystalline silicon carbide micro motors,
axial electromagnetic micro motors, synergetic computer – aided design of MEMS.
Reference Books
1. Sergey Edward Lyshevski, “MEMS and NEMS: Systems, Devices, and Structures” CRC
Press, 2002.
2. Stephen D. Senturia,” Micro system Design”, Kluwer Academic Publishers,2001
3. Tai Ran Hsu ,”MEMS and Microsystems Design and Manufacture” ,Tata McGraw Hill,
2002.

L T P C
ECE5307-TESTING AND TESTABILITY
2 0 1 3
Regulation R2015
Description: This course describes about the various types of faults, study about fault
detection, fault modelling, fault simulation, test generation methods and
fault diagnosis methods.
Unit I Fault Modelling and Fault Simulation 9
Overview to testing , Faults in Digital Circuits , Modelling of faults: , Functional modelling
at logical, register and structural levels , Logic simulation , Types of simulation , Event
Driven simulation , Delay models , Fault Modelling , Logical Fault Models , Fault detection ,
Fault Equivalence and Fault Location ,Fault dominance , Fault simulation Technique , Fault
simulation for combinational circuits , Fault sampling
Unit II Test Generation for Circuits 9
Overview , Composite circuit representation and value systems , Test generation basics
,Implication , Structural test generation: preliminaries , Specific structural test generation
paradigms, Non-structural test generation techniques ,Test generation systems ,Test
generation for reduced heat and noise during test ,Classification of sequential ATPG methods
and faults , Fault collapsing , Fault simulation , Test generation for synchronous circuits ,
Test generation for asynchronous circuits , Test compaction , IDDQ testing
Unit III Design for Testability 9
Testability , Ad Hoc Design for Testability Techniques , Controllability and Observability by
means of scan registers, Generic scan path designs , Board level and system level DFT

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approaches , Advanced Scan concepts , Boundary scan standards , Compression Techniques

Unit IV Self, Test and Memory Testing 9
Built In Self Test concepts , BIST Design Rules , Test pattern generation for BIST,
Exhaustive Testing, Pseudorandom Testing, Pseudo exhaustive Testing, Logic Segmentation
and Constant weight patterns ,Generic offline BIST architecture – Specific BIST architecture
– CSBL, BEST, RTS, LOCST,STUMPS,CBIST, CEBS, RTD, SST, CATS, CSTP and
BILBO – Advanced BIST Concepts – Memory testing , Traditional tests , March tests ,
Pseudorandom memory tests
Unit V Fault Diagnosis, Self, Checking Design and PLA Testing 9
Logical Level Diagnosis , Diagnosis by UUT reduction ,Fault Diagnosis for Combinational
Circuits , Self-checking design, System Level Diagnosis , PLA testing , PLA testing
problems ,Test generation algorithms for PLAs , Testable PLA design , Analog and mixed
signals circuit testing.
Reference Books
1.Nirajjha, S. Gupta, ―Testing of Digital systems, Cambridge Press, 2003.
2.M.Abramovici, et.al., ―Digital systems and Testable Design, Jaico IEEE Publishers, 2002.
3. M.L.Bushnell, V.D.Agrawal, ―Essentials of Electronic Testing for Digital, Memory and
Mixed-Signal LSI Circuits, Kluwer Academic, 2002.
4. Laung-T Wang, et.al (Editors), ―VLSI Test principles and architectures: Design for
Testability, Kaufmann Publishers, 2006.

L T P C
ECE5308-SYSTEM AND DEVICE PACKAGING
3 0 0 3
Regulation R2015
Description: The objective of this course is to sensitize the undergraduate students and
graduate students to the all-important multidisciplinary area of electronics
systems packaging. The course will discuss all the important facets of
packaging at three major levels, namely, chip level, board level and
system level. The entire spectrum of microelectronic systems packaging
from design to fabrication; assembly and test will be covered. Current
trends in packaging of electronic systems will be covered.
Unit I Overview of electronic systems packaging 9
Products and levels of packaging, Packaging aspects of handheld products; Case studies in
applications, Case Study (continued); Definition of PWB, Basics of Semiconductor and
Process flowchart; Wafer fabrication, inspection and testing, Wafer packaging; Packaging
evolution; Chip connection choices, Wire bonding, TAB and flipchip-1, Wire bonding, TAB
and flipchip-2.
Unit II Semiconductor Packages 9
Why packaging & Single chip packages or modules (SCM), Commonly used packages and
advanced packages; Materials in packages, Advances packages (continued); Thermal

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mismatch in packages; Current trends in packaging, Multichip modules (MCM)-types;

System-in- package (SIP); Packaging roadmaps; Hybrid circuits.
Unit III Electrical Design considerations in systems packaging 9
Electrical Issues -Resistive Parasitic, Capacitive and Inductive, Parasitic, Electrical Issues on
Layout guidelines and the Reflection problem, Interconnection, Quick Tutorial on packages;
Benefits from CAD; Introduction to DFM, DFA & DFT, Components of a CAD package and
its highlights, Design Flow considerations; Beginning a circuit design with schematic work
and component layout, Demo and examples of layout and routing; Technology file
generation from CAD; DFM check list and design rules; Design for Reliability
Unit IV Printed Wiring Board Technologies: Board- level 9
packaging aspects
Review of CAD output files for PCB fabrication; Manufacturing process flow, Vias; PWB
substrates, Substrates continued; Video highlights; Surface finishes, Photoresist and
application methods; UV exposure and developing; Printing technologies for PWBs, PWB
etching; Resist stripping; Screen-printing technology, Through-hole manufacture process
steps; Panel and pattern plating methods, Video highlights on manufacturing; Solder mask
for PWBs; Multilayer PWBs; Introduction to microvias, Microvia technology and Sequential
build-up technology process flow for high-density interconnects, Conventional Vs HDI
technologies; Flexible circuits; Tutorial session
Unit V Surface Mount Technology 9
SMD benefits; Design issues; Introduction to soldering, Reflow and Wave Soldering
methods to attach SMDs, Solders; Wetting of solders; Flux and its properties; Defects in
wave soldering, Vapour phase soldering, BGA soldering and Desoldering/Repair; SMT
failures, SMT failure library and Tin Whiskers, Tin-lead and lead-free solders; Phase
diagrams; Thermal profiles for reflow soldering; Lead-free alloys, Lead-free solder
considerations; Green electronics; RoHS compliance and e-waste recycling issues, Thermal
Design considerations in systems packaging, Embedded Passives Technology- Introduction
to embedded passives; Need for embedded passives; Design Library; Embedded resistor
processes, Embedded capacitors; Processes for embedding capacitors; Case study examples;
Summary of materials in packaging
Reference Books
1. Rao R. Tummala, Fundamentals of Microsystems Packaging, McGraw Hill, NY, 2001.
2. William D. Brown, Advanced Electronic Packaging, IEEE Press, 1999.

L T P C
ECE5309-SOC DESIGN AND VERIFICATION
2 0 1 3
Regulation R2015
Description: This course describes about the various types of verification techniques,
analog/mixed signal simulation, hardware-software co-verification and
design sign-off.

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Unit I Overview and System-Level Verification 9

Technology Challenges, Verification Technology Options-( Simulation Technologies, Static
Technologies, Formal Technologies, Physical Verification and Analysis, Comparing
Verification Options), Verification Methodology, Testbench Creation, Testbench Migration ,
Verification Languages, Verification IP Reuse, Verification Approaches, Verification and
Device Test, Verification Plans, Bluetooth SOC: A Reference Design.
Unit II Block-Level Verification 9
IP Blocks, Block Level Verification, Block Details of the Bluetooth SOC , Lint Checking,
Formal Model Checking, Functional Verification/Simulation, Protocol Checking, Directed
Random Testing , Code Coverage Analysis.
Unit III Analog/Mixed Signal Simulation 9
Mixed-Signal Simulation, Design Abstraction Levels, Simulation Environment, Using
SPICE, Simulation Methodology, Bluetooth SOC Digital-to-Analog Converter, Chip-Level
Verification with an AMS Block. Functional Simulation, Testbench Wrappers, Event-based
Simulation, Cycle-based Simulation, Simulating the ASB/APB Bridge, Mixed-Event/Cycle-
based Simulation, Transaction-based Verification, Simulation Acceleration.
Unit IV Hardware/Software Co-verification 9
HW/SW Co-verification Environment, Emulation, Soft or Virtual Prototypes, , Co-
verification, Rapid Prototype Systems, Comparing HW/SW Verification Methods, FPGA-
based Design, Developing Printed Circuit Boards, Software Testing
Unit V Static Netlist and Physical Verification 9
Netlist Verification, Bluetooth SOC Arbiter, Equivalence Checking, Static Timing
Verification. Design Checks, Physical Effects Analysis, Design sign-off
Reference Books
1.Prakash Rashinkar, Peter Paterson, Leena Singh “System-on-a-chip verification
Methodology and techniques “ Kluwer Academic Publishers , 2002.
2.Ricardo Reis, Vincent Mooney, Paul Hasler, VLSI-SoC: Advanced Topics on Systems on a
Chip, Springer Science and Business Media, 2009.
3.Wael Badawy, Graham A. Julien, System-on-Chip for Real-Time Applications, Springer
Science and Business Media, 2003.

L T P C
ECE5310- TEST ENGINEERING – I
2 0 1 3
Regulation R2015
Description: The basic course for testing. The testing of IC is a key process. The topics
covered include digital, analog and mixed signal circuits testing.
Unit I Fundamentals of Digital testing 9
Essentials: Scientific/Engineering Notation, Voltage, Current, Resistance, Using ohms law,
Digital numbers, Digital Logic, Testing Philosophy, Role of Testing, VLSI Technology
Trends Affecting Testing

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Introduction to Test: Basic Terms, Correct way to Test, The Test System, The PMU, The
Pin Electronics, Basic rules of test engineering
Unit II Mixed Signal Circuits 9
Analog, Digital, Mixed signal circuits, common types of Analog and Mixed signal circuits,
application of mixed signal circuit.
Unit III Test and Diagnostic equipment 9
ATE, Wafer Prober, Handler, E – beam prober, Focused Ion beam, Forced Temperature
system. Signal generator, spectrum analyzer, oscilloscope, pattern generator, logic analyzer.
Measurement accuracies, calibration, focused calibration.
Unit IV Test Planning 9
Device data sheet, generating test plan, components of test program, test economics, yield,
correlation, Time to market.
Unit V DC parameters testing 9
Open Shorts PMU methods, VOH/IOH, VOL/IOL, IIH/IIL, IDD Gross current, IDD static
Current, IDDQ, IDD Dynamic Current, Resistive Inputs- Pull ups, Pull downs, Output
Fanout, IOZL/IOZH, Input clamp, output short circuit current, Line regulation, load
regulation, ref voltage.
Reference Books
1. Mark Burns, Gordon W Roberts, An Introduction to Mixed-Signal IC Test and
Measurement, Oxford Univ Pr (Sd); 2 edition (14 October 2011)
2. Michael L. Bushnell, Vishwani D. Agrawal, Essentials of Electronic Testing for
Digital, Memory & mixed Signal Testing VLSI Circuits, Springer; 1st Corrected ed.
2002. Corr. 2nd printing 2004 edition (12 January 2005).

L T P C
ECE5384-IC TEST LABORATORY
0 0 3 1
Regulation R2015
1 analog device and 1 digital device will be tested in the lab. The circuit will be built on a
bread board/general purpose board
ATE Simulator, The same will be verified on the tester.

L T P C
ECE5385- SOC VERIFICATION LABORATORY
0 0 3 1
Regulation R2015
Module 1
1. Verilog Simulation and RTL Verification
a) Memory
b) Clock Divider and Address Counter
c) n-Bit Binary Counter and RTL Verification

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2. Finite State Machines Implement and Verify Using Verilog File I/O
3. Different types of TBs for memory and adder/subtractor

Module 2
1. Basic Verification environment for FIFO/UART
2. Verification Planning for FIFO/UART
a) Development of the test cases as per the verification plan b) Generation and Analysis
of Code coverage Reports
3. Writing assertions for FIFO

REFERENCE BOOKS:
1. Samir Palnitkar ,Verilog HDL.
2. T. Kropf, "Introduction to Formal Hardware Verification", Springer Verlag, 2000.
3. P. Rashinkar, Paterson and L. Singh,"System-on-a-Chip Verification-Methodology and
Techniques", Kluwer Academic Publishers, 2001

ELECTIVES- SEMESTER I
L T P C
ECE5311-SYSTEM-on-CHIP ARCHITECTURE
3 0 0 3

Regulation R2015

Description: This course describes the SOC creation from market and product
requirement specification to complete implementation with focus on h/w
implementation.

Unit I Market and Product Requirement Specification 9

Digital logic, HW/SW/FW allocation, SOC Organization and architecture, memory

requirements, Interconnect, I/F requirements, System model, performance analysis, golden
models and inputs for implementation.

Unit II CPU and Memory System 9

Computer arithmetic, ISA: functions, addressing modes and formats, comparisons, Role of
compiler, MIPS, Processor structure and function, RISC, CISC architectures, RISC vs.
CISC architectures comparison, RISC, CISC Processor s and overview Memory
management and hierarchy, Caches: associativity, allocation and replacement policies,
sub-block placement. Multilevel caches, Cache performance issues, Uniprocessor cache
coherency issues: self- modifying code, peripherals, address translation, Six basic
cache optimizations, Eleven Advanced optimizations of Cache performance, Virtual
memory, Virtual memory protection and examples, Virtual memory and virtual

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machines, Cross cutting issues, AMD Opteron memory hierarchy

Unit III Interconnect - Network on a chip 9

Interconnect- performance,re-use and ease of physical implementation

Unit IV I/F 9

Interface implementation. Throughput analysis. Study different I/F IP - PCIe, SATA, DDR,
JTAG, SPI, I2C, UART, IJTAG

Unit V SOC Implementation and Synthesis 9

Select RTL components, RTL refinements/enhancements, verification

Reference Books:
1. William Stallings, Digital Computer Organization and Architecture: Designing for
Performance,8th Edition, Pearson, 2010.
2. John. L. Hennessy, David. A. Patterson, Computer Architecture: A Quantitative
Approach,4th Edition, Elsevier (Morgan Kufmann Series), 2010.
3. Kai Hwang, Naresh Jotwani, ―Advanced Computer Architecture: Parallelism,
Scalability and Programmability, Tata McGraw Hill, 2010.
4. John Hayes, ―Computer Architecture and Organization, Tata McGraw Hill, 2010.
5. David Culler, J.P. Singh, Anoop Gupta,Parallel Computer Architecture: A
Hardware/Software Approach, Elsevier (Morgan Kufmann Series), 2005.
6. Nicholas Carter, Raj Kamal, ―Computer Architecture and Organization, Tata McGraw
Hill (Schaum's Outline Series), 2009.

L T P C
ECE5312-LOW POWER VLSI DESIGN
3 0 0 3
Regulation R2015
Description: This course describes about sources of power consumption, various power
reduction and power estimation techniques of CMOS circuits in addition to
that it also deals with the hardware, synthesis and design concepts of low
power circuits
Unit I Power Dissipation 9

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M.Tech. Semiconductor Testing and Packaging Regulation R2015

Sources of power dissipation, designing for low power ,physics of power devices in
MOSFET devices ,power dissipation in CMOS, low power VLSI design
Unit II Power Estimation 9
Modeling of signals, signal probability calculation, probabilistic techniques for signal activity
estimation, statistical techniques, estimation of glitching power, sensitivity analysis, power
estimation using input vector compaction, power dissipation in domino CMOS, circuit
reliability, power estimation at the circuit level, high- level power estimation, information-
theory based approaches, estimation of maximum power
Unit III Synthesis for Low Power and test flow low voltage CMOS 9
circuits
Behavioral level transforms logic level optimization for low power, circuit level, summary
and future directions, Circuits design style, leakage current in deep sub micrometer
transistors, deep sub micrometer device design issues, low voltage circuits design techniques,
testing deep sub micrometer ICs with elevated intrinsic leakage, multiple supply voltages.
Unit IV Energy Recovery techniques 9
Energy dissipation in transistor channel using an RC model, energy recovery circuits design,
design with partially reversible logic , supply clock generation, summary and conclusion
sources of software power dissipation, software power estimation , software power
optimizations, automated low power code generation, co design for low power
Unit V Low Power System Design 9
Standard adder cells, CMOS Adder’s Architecture, B ICMOS Adder, Low-Voltage Low-
Power Design techniques, Current-Mode Adders, Over view of multiplication, Types of
multiplier architecture, Braun multiplier, Baugh-Woolley multiplier, Wallace tree multiplier,
Types of ROM, ASIC physics of floating gate non volatile devices, floating gate memories,
Basics of ROM, Low –power ROM technology
Reference Books
1.Kaushik Roy, Sharat Prasad, ―Low-Power CMOS VLSI Circuit Design, Wiley, 2009.
2. K. Seng Yeo, Kaushik Roy, ―Low Voltage, Low Power VLSI Subsystems, Tata
McGraw Hill, 2009.
3.Gary K. Yeap, ―Practical low power digital VLSI design", Springer, 2002.

ECE5313-VLSI FABRICATION L T P C
TECHNOLOGY 3 0 0 3
Regulation R2015
Description: This course familiarizes the students with rapid progresses of the
fabrication technology in recent years, VLSI fabrication processes (such
as crystal growth, wafer preparation, epitaxy, oxidation, lithography,
etching, deposition, diffusion, ion implantation and metallization), the
integration process and packaging techniques in VLSI
Unit I Quantum Mechanics 9

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Overview- material conductivity - Quantum mechanics - energy bands - crystalline structures

- Density of states - band structures - Fermi - Dirac function - material classification - Band
structure - electrons and holes - doping - Scattering - mobility - Diffusion transport - Einstein
relation - Carrier generation and recombination- continuity equation.
Unit II Wafer Preparation and Oxidation 9
Review of Semiconductor theory - Electronic Grade Silicon - Czochralski Crystal Growing -
Silicon Shaping Processing consideration - Vapor Phase Epitaxy - Molecular Beam Epitaxy
- Silicon on Insulators – Epitaxial Evaluation – Growth Mechanism and Kinetics – Thin
Oxides – Oxidation Techniques and Systems – Oxide Properties.
Unit III Lithography and Relative Plasma Etching 9
Optical Lithography – Electron Lithography – X-Ray Lithography - Ion Lithography Plasma
- Properties – Feature Size - Control and Anisotropic Etch Mechanism – Relative Plasma
Etching Techniques and Equipments.
Unit IV Deposition , Diffusion, Lon Implementation 9
Deposition Processes – Polysilicon – Plasma Assisted Deposition – Models of Diffusion in
Solids – Fick’s One Dimensional Diffusion Equation – Atomic Diffusion Mechanism –
Measurement Techniques – Range Theory – Implantation Equipment. Annealing Shallow
Junction – High Energy Implantation – Physical Vapour Deposition – Patterning.
Unit V Process Integration and Packaging 9
NMOS IC Technology – CMOS IC Technology – MOS Memory IC Technology – Bipolar
IC Technology – IC Fabrication. Analytical Beams – Beams Specimen Interaction –
Chemical Methods – Package Types baking Design Considerations – VLSI Assembly
Technology – Package Fabrication Technology., Overview of ULSI Technology
Reference Books
1. S.M.Sze, ―VLSI Technology, McGraw Hill, 2003.
2. Douglas A. Pucknell, Kamran Eshraghian, ―BASIC VLSI Design, Pearson, 2003.
3. R.S. Muller and T.I. Kamins, ―Device Electronics for Integrated Circuits, Wiley 3rd
Edition 2003.
4. Simon M. Sze, ―Semiconductor Devices Physics and Technology, 2nd Edition, Wiley,
2001.

ECE5314-HARDWARE SOFTWARE CO- L T P C

DESIGN 3 0 0 3
Regulation R2015
Description: This course describes about the quest for energy efficiency in hardware-
software co-design, control and data flow analysis. In addition to that it
also describes about embedded cores, SOC and various types of co-
processors
Unit I Data Flow Modeling Implementation 9
Introducing Hardware/Software Co-design, The Quest for Energy Efficiency, The Driving

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Factors in Hardware/Software Co-design, The Hardware-Software Co-design Space, The

Dualism of Hardware Design and Software Design, Modeling Abstraction Level,
Concurrency and Parallelism. Introducing Data Flow Graphs, Analyzing Synchronous Data
Flow Graphs, Control Flow Modeling and the Limitations of Data Flow Models, Adding
Time and Resources, Transformations. Software Implementation of Data Flow, Hardware
Implementation of Data Flow, Hardware/Software Implementation of Data Flow.
Unit II Control Flow and Data Flow analysis, FSM and 9
architectures
Data and Control Edges of a C Program, Implementing Data and Control Edges,
Construction of the Control Flow Graph, Construction of the Data Flow Graph, Application:
Translating C to Hardware, Single-Assignment Programs. Cycle-Based Bit-Parallel
Hardware, Hardware Modules, Finite State Machines, Finite State Machines with Data path,
FSMD Design Example: A Median Processor, Proper FSMD, Language Mapping for FSMD
by Example. Limitations of Finite State Machines, Microprogrammed Control, Micro-
instruction Encoding, The Micro-programmed Datapath, Implementing a Micro-programmed
Machine, Micro-program Interpreters, Micro-program Pipelining, Microprogramming with
Microcontrollers.
Unit III System on Chip 9
Processors, The RISC Pipeline, Program Organization, Compiler Tools, Low-Level Program
Analysis, Processor Simulation. The System-on-Chip Concept, Four Design Principles in
SoC Architecture, Example: Portable Multimedia System, SoC Modeling in GEZEL.
Connecting Hardware and Software, Synchronization Schemes, Communication-Constrained
Versus Computation-Constrained, Tight and Loose Coupling.
Unit IV Buses and Interfaces 9
On-Chip Bus Systems, Bus Transfers, Multi-master Bus Systems, Bus Topologies. Memory-
Mapped Interfaces, Coprocessor Interfaces, Custom-Instruction Interfaces. The Coprocessor
Hardware Interface, Data Design, Control Design, Programmer’s Model Control Design Data
Design.
Unit V Co-processors 9
The Trivium Stream Cipher Algorithm, Trivium for 8-bit Platforms, Trivium for 32-bit
Platforms.AES Encryption and Decryption, Memory-Mapped AES Encryption Coprocessor,
AES Encryption/Decryption with Custom Instructions.Coordinate Rotation Digital Computer
Algorithm, A Hardware Coprocessor for CORDIC, An FPGA Prototype of the CORDIC
Coprocessor, Handling Large Amounts of Rotations.
Reference Books
1.Patrick Schaumont, A Practical Overview to Hardware/Software Co-design, Springer,
2010.
2. Jorgen Staunstrup, Wayne Wolf, Hardware/Software Co-Design, Springer Science and
Business Media, 1997.
3. Ralf Niemann,Hardware/Software Co-Design for Data Flow Dominated Embedded

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M.Tech. Semiconductor Testing and Packaging Regulation R2015

Systems, Springer Science and Business Media, 1998.

4. Ivan Hom A Methodology for the Hardware/software Co-design of Embedded Systems,
ProQuest, 2007.

SEMESTER II
L T P C
ECE5315-FORMAL VERIFICATION
3 0 0 3
Regulation R2015
Description: In the context of hardware and software systems, formal verification is
the act of proving or disproving the correctness of intended algorithms
underlying a system with respect to a certain formal specification or
property, using formal methods of mathematics This course deals with
an Overview to verification, current formal verification techniques,
property specifications of verification. It also deals with formal test plan
procedure and final system simulation.
Unit I Verification Process 9
Verification, Market Window. Verification Plan, Debug Cycle, Simulation, Output Data,
Test Bench Development. HDL Software Simulators, Accelerated Simulation, Process-
based accelerator Techniques, Hardware Emulation, FPGA Prototyping.
Unit II Formal Techniques 9
Formal verification concepts, -what is formal verification, Formal Boolean verification,
formal sequential verification. Formal Basics, Reachability Analysis, Definitions
Unit III Property Specification 9
Reasoning about Correct Behavior, Elements of Property Languages, Property Language
Layers, Property Classification, PSL Basics, System Verilog Assertion Basics, Fair Arbiter
Example.
Unit IV The Formal Test Plan Process 9
Developing a Formal Test Plan, Rules for Writing a Requirements Model, AMBA AHB
example. Cone-of Influence Reduction, Abstraction Reduction, Compositional Reasoning,
Symmetry, Counter Abstraction, Non determinism, Gradual Exhaustive Formal Verification.
Unit V Final system simulation 9
Test Plan Revisited, Module Verification, Full Simulation from a Simulation Flow, Full
Simulation from a Formal Verification Flow., IEEE 1850 PSL property specification
language, IEEE 1800 System Verilog assertions.
Reference Books
1. Douglas L. Perry, Harry D. Foster “Applied Formal Verification: For Digital Circuit
Design” , Mc Graw-Hill Professional Engineering, 2005.
2.Luca De Alfaro, Stanford University. Computer Science Dept,” Formal verification of
probabilistic systems “, Issue 1601, Stanford University, 1997.
3. William K Lam, “Hardware Design Verification: Simulation and Formal Method-based

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M.Tech. Semiconductor Testing and Packaging Regulation R2015

Approaches” , Prentice Hall, 2005.

L T P C
ECE5316-HIGH LEVEL SYNTHESIS
3 0 0 3
Regulation R2015
Description: This course presents a structured design concepts, algorithmic and register
level design, gate level and ASIC library modeling, synthesis and
synthesis algorithms for design automation.
Unit I Structured Design Concepts 9
The Abstraction Hierarchy, Textual vs. Pictorial Representations, Types of Behavioral
Descriptions, Design Process, Structural Design Decomposition, The Digital Design Space,
CAD Tool Taxonomy, Schematic Editors, Simulators, The Simulation System, Simulation
Aids, Applications of Simulation, Synthesis Tools, Major Language Constructs, Lexical
Description, VHDL Source File, Data Types, Data Objects, Language Statements, Advanced
Features of VHDL, The Formal Nature of VHDL, VHDL 93, Modeling Delay in VHDL, The
VHDL Scheduling Algorithm, Modeling Combinational and Sequential Logic, Logic
Primitives
Unit II Algorithmic and Register Level Design: 9
General Algorithmic Model Development in the Behavioral Domain, Representation of
System Interconnections, Algorithmic Modeling of Systems , Transition from Algorithmic to
Data Flow Descriptions, Timing Analysis, Control Unit Design, Ultimate RISC Machine
Unit III Gate Level; and ASIC Library Modeling: 9
Accurate Gate Level Modeling, Error Checking, Multivalued Logic for Gate Level
Modeling,
Configuration Declarations for Gate Level Models, Modeling Races and Hazards,
Approaches to Delay Control, Design of Combinational Logic Circuits, Design of Sequential
Logic Circuits
Unit IV Synthesis 9
Behavioral Model Development, The Semantics of Simulation and Synthesis, Modeling
Sequential Behavior, Modeling Combinational Circuits for Synthesis, Inferred Latches and
Don’t Cares, Tristate Circuits, Shared Resources, Flattening and Structuring, Effect of
Modeling Style on Circuit Complexity, Top-Down Design Methodology, Sobel Edge
Detection Algorithm, System Requirements Level, System Definition Level, Architecture
Design, Detailed Design at the RTL Level, Detailed Design at the Gate Level
Unit V Synthesis Algorithms for Design Automation 9
Benefits of Algorithmic Synthesis, Algorithmic Synthesis Tasks, Scheduling Techniques,
Allocation Techniques, State of the Art in High-Level Synthesis, Automated Synthesis of
VHDL Constructs
Reference Books
1. James R. Armstrong and F. Gail Gray, VHDL Design Representation and Synthesis,

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M.Tech. Semiconductor Testing and Packaging Regulation R2015

Prentice Hall, 2000.

2. A.M. Dewey, Analysis and Design of Digital Systems with VHDL, PWS Kent, 1996.
3. A.A. Jerraya, H. Ding and P. Kission, Behavioral Synthesis and Component Reuse with
VHDL, Kluwer, 1996.
4. K.C. Chang, Digital System Design with VHDL and Synthesis: An Integrated Approach,
Wiley India Pvt. Ltd., New Delhi

L T P C
ECE5317-CMOS RF DESIGN
3 0 0 3
Regulation R2015
Description: This course describes about process design of CMOS RF devices such as
RF mixers, RF CMOS oscillators; RF CMOS phase locked loops, RF
CMOS pre-scalers and their architectures because RF IC design
particularly in CMOS is a different activity altogether from traditional or
discrete RF design.
Unit I RF CMOS Devices 9
Modern RF Mobile Technologies, The RF Transceiver, Modulation and Demodulation
Techniques, Multiple Access Techniques, Receiver Sensitivity and Linearity, On- chip
Power Amplifier, The Cellular Phone Concept, The CMOS RF Technology, Overview, RF
Transistor, On- Chip Inductors, Baluns/Transformers, RF Interconnects, Varactors, RF
Capacitors.
Unit II Low Noise Amplifiers 9
Process Design Kits, Basic Concepts of LNAs, Input Architecture of LNAs, Input Matching
Analysis, Design of a single – band LNA(LNA1)
Unit III RF Mixers and RF CMOS Oscillators 9
Overview, Common Configurations of Active Mixers, Active Mixer with Current Booster,
Passive Mixers, Port Isolation and DC Offset in Direct Conversion Mixers, Image Reject
Mixers for low IF Architectures, Various LC VCO Topologies LC VCO Design
Methodology
Unit IV RF CMOS Phase – Locked Loops 9
Fundamental Principles of a Phase – Locked Loop, Transient Characteristics – Tracking,
Loop Bandwidth – Second Order PLL, Acquisition, Phase Detector and Loop Filter , Charge
Pump PLL Filter, Noise Characteristics of PLL Building Blocks
Unit V RF CMOS Prescalers and Architecture 9
Prescalers , DFFs for Prescaler , Design and Optimization of CMOS Dynamic circuits, Phase
noise and architectures
Reference Books
1.Kiat Seng YEO , Manh Anh Do, Chirn Chye BOON “ Design of CMOS RF Integrated
circuits and systems”, World Scientific Publishing Co. Pte.Ltd, 2010.
2. Robert Caverly ,”CMOS RFIC Design Principles”, Artech House Press, 2007.

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M.Tech. Semiconductor Testing and Packaging Regulation R2015

3. Thomas H.Lee “ The design of CMOS Radio – Frequency Integrated circuits “,

Cambridge University, 2004.

ECE5318-THREE DIMENSIONAL NETWORK- L T P C

ON-CHIP 3 0 0 3
Regulation R2015
Description: Noc have been proposed as a promising solution for future SoC Design
since it offers more scalability, allows more processors to operate
concurrently and allows performance prediction. This course deals with
overview to network on chip communication architecture, system
integration, verification and testing of NOC in 3D .
Unit I NOC , A Paradigm Shift, NoC Modelling and Topology
9
Exploration
SoC Integration and its Challenges , SoC to NoC: A Paradigm Shift , Research Issues in NoC
Development ,Existing NoC Examples , OSI Layer Roles in NoC , Benefits and Challenges
in Adoption of NoCs ,Topology Exploration , Traffic Modelling , Topology Modelling ,
Topology Synthesis , Application Mapping: Mapping Problem, ILP Formulation,
Constructive Heuristics, Mapping using Discrete PSO
Unit II Communication Architecture, NOC Based System 9
Integration
Switching Technique , Packet Routing , QoS, Congestion Control and Flow Control , Router
Design , Network Link Design , NoC Interface Design , Clock Distribution , NoC Based
System Floor Planning
Unit III Power and Thermal Effects and Management, NOC 9
Verification and Testing
Models, Wear-out Mechanisms , Faults Classification , Fault Tolerance Metrics , Error
Control Coding for On-Chip signalling , Power and Energy Savings in NoCs , On Designing
Reliable NoCs , NoC Verification , Testing Fundamentals, NoC Testing
Unit IV NOC Design and Prototyping Framework 9
The Spidergon STNoC , Middleware Memory Management in NoC , The SYSMANTIC
Framework , Application Specific NoC Synthesis , Reconfigurable NoC Design
Unit V Design of 3-D NOCs, Future Trends in NOC 9
3-D Integration , Design and Evaluation of 3-D NoC Architectures , Case Studies:
Implementation of a 3-D Instance for LEON3 Processor, Implementation of a 3-D NoC ,
Future Trends: Photonic NoC, Wireless NoCs
Reference Books
1. Konstantinos Tatas (Author), Kostas Siozios (Author), Dimitrios Soudris (Author), Axel
Jantsch (Author),---.Designing 2D and 3D Network-on-Chip Architectures, Publisher:
Springer, 2014.
2. Santanu Kundu (Author), Santanu Chattopadhyay (Author)---Network-on-Chip: The Next

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M.Tech. Semiconductor Testing and Packaging Regulation R2015

Generation of System-on-Chip Integration, 1 edition, Publisher: CRC Press, 2014.

3. Abbas Sheibanyrad, Frédéric Pétrot, Axel Jantsch,--- 3D Integration for NoC-based SoC
Architectures”, Springer Science and Business Media, 2010.

L T P C
ECE5319-ELECTRONIC PRODUCT DESIGN
3 0 0 3
Regulation R2015
Description: This course gives an introduction of electronic product development
process, system design, IC packaging and their metrics, mechanical
design, quality in the design process and portable electronics.
Unit I INTRODUCTION 9
The basic product development process-product planning-design and engineering-
procurement-manufacturing -functionality-performance-user interface-form factor- battery
life- cost- time to market (TTM)- reliability-marketing and distribution-service and support.
Unit II SYSTEM DESIGN 9
Top down design-product concept-innovation-creativity- validation -communication-product
requirements-system architecture development-trade-off analysis-cost modelling-circuit
design-physical and mechanical design-Tolerance and reliability.
Unit III ELECTRONIC PACKAGING 9
IC packaging: Leaded package, TABITCP package-COB, flip-chip, BGA, CSP-Discrete
components-Board to board connectors-substrates-Escape routing-PCA/module design
metrics-Electronic packaging metrics-I/O hardware : buttons, switches, dials and touch
screens, speakers , microphones, antennas, and external connectors
MECHANICAL DESIGN, QUALITY IN THE DESIGN 9
Unit IV
PROCESS
Housings-EMI shielding-Thermal management: High level thermal analysis, thermal issues
in notebook computers-mechanical integration-DFMA analysis, Quality control -quality
assurance-quality functional deployment-assignment matrices-checklist-quality in the design
process-concurrent design-risk analysis-quality in production.
Unit V PORTABLE ELECTRONICS 9
Digital and analog processing: microprocessor, logic devices, microcontrollers, DSP, analog
devices, sensors, wireless communication, system memory and mass storage-Displays:
Display technologies-LCD-micro display-pen input-power sources- Battery technologies: Ni-
Cd, alkaline,Ni-MH,lithium ion, lithium polymer, photovoltaic cells, fuel cells-product
implementation-high level power analysis-Case study: Cellular phones-portable PCs-
Personal digital assistants-digital imaging products.
Reference Books
1. Tony Ward and James Angus, ”Electronic product design”, Chapman and Hall
publications,1996.
2. Bert Haskell, “ Portable Electronics product design and development: For cellular

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M.Tech. Semiconductor Testing and Packaging Regulation R2015

phones, PDAs, Digital cameras, personal electronics and more”, McGraw-HILL, 2004.

SEMESTER III
L T P C
ECE6311-MIXED SIGNAL IC DESIGN
3 0 0 3
Regulation R2015
Description: This course describes about the concepts of various current mirror
configurations, various amplifier configurations, design of op-amp and
comparators. In addition to that it also discusses about various data
conversion architectures, Nyquist rate data converters and oversampling
converters
Unit I Current Mirror, Amplifiers 9
Simple current mirror, Common source amplifiers, Source follower, common gate amplifier,
Common gate amplifier, cascade current mirror, MOS differential pair gain stage, Frequency
response of linear systems, frequency response of elementary transistor circuits, Ideal model
of negative feedback, dynamic response of feedback amplifiers, First and second order
feedback systems.
Unit II Op amp Analysis 9
Two stage CMOS op amp, OP amp compensation, Advanced current mirrors, Folded cascade
op amp, current mirror op amp, differential op amp, Analog integrated circuit biasing,
voltage regulation , Time domain analysis , frequency domain analysis, Noise model for
circuit elements and analysis, Comparator specification, using an op amp for comparator,
Charge injection errors and latched comparators.
Unit III Signals and filters 9
Performance of sample and hold circuits, MOS sample hold basics, example of CMOS
sample hold and circuits, Overview continuous time filter , Overview to GM-c filters , trans
conductors using fixed resistors, CMOS trans conductors using Triode and active transistors,
Active RC MOSFETS, discrete time signal overview , Laplace, z transform, down sampling
and up sampling.
Unit IV Switched capacitors, D/A converters 9
Switched capacitor – basic building blocks , basic operation and analysis, Noise switched
capacitor circuits, first order filters, bi quad filters, charge injection, Ideal D/A,, A/D
converters, quantization noise, signed code, performance limitation, Nyquist rate D/A
converters- decode based converters, binary scale converters, thermometer code converter,
hybrid converter.
Unit V A/D converters 9
Integrating convertors, successive approximation converters, cyclic converters ,pipelined
A/D converters, flash converters, two step A/D converters , Interpolating converters,
Oversampling with and without noise converters, system architectures, multi bit over
sampling converters , Phase locked loops, linearized small signal analysis, Jitter phase noise,

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electronic oscillators, Jitter phase noise in PLLs.

Reference Books
1. Tony Chan Carusone ,David A. Johns ,Kenneth W. Martin “Analog Integrated
Circuit design”, John Wiley and Sons, Inc, 2nd edition, 2012.
2. Tajalli, Armin, Leblebici, Yusuf, Extreme Low-Power Mixed Signal IC Design, Springer,
2010.
3. R. Jacob Baker, CMOS Mixed- Signal Circuit Design, Wiley –IEEE Press, 2nd Edition
2009.

ECE6312-THREE DIMENSIONAL L T P C
INTEGRATED CIRCUIT DESIGN 3 0 0 3
Regulation R2015
Description: 3D integration or vertical integration is an exciting path to boost the
performance and extend the capabilities of modern integrated circuits.
This course deals with manufacturing of 3D systems, interconnection
prediction models, physical design techniques, thermal management
techniques, timing optimization for 3D architectures.
Unit I Manufacturing of 3-D Packaged Systems, 3-D IC
9
Fabrication Techniques
Overview to Interconnects , Three- Dimensional or vertical integration Overview , System-
in-Package , Three-Dimensional Integrated Circuits , System-on-Package ,Technologies for
System-in-Package , Cost issues for 3-D Integrated Systems , Monolithic 3-D ICs , 3-D ICs
with TSVs or Interplane Vias , Contactless 3-D ICs , Vertical Interconnects for 3-D ICs
Unit II Interconnect Prediction Models, Physical Design 9
Techniques for 3-D ICs
Interconnect Prediction Models: for 2-D ICs and 3-D ICs , Projections for 3-D ICs , Floor
Planning Techniques for 3-D ICs , Placement Techniques for 3-D ICs , Routing Techniques
for 3-D ICs , Layout Tools for 3-D ICs
Unit III Thermal Management Techniques 9
Thermal Analysis of 3-D ICs , Thermal Management without Thermal Vias , Thermal
Management with Thermal Vias
Unit IV Timing Optimization for Interconnects 9
Interplane Interconnect Models , Two-Terminal Nets with a Single-Interplane Via , Two-
Terminal Nets with a Multiple-Interplane Via ,Timing-Driven Placement Via for Interplane
Interconnect Trees , Multi-terminal Interconnect Via Placement Heuristics , Via Placement
Algorithms for Interconnect Trees
Unit V 3-D Circuit Architectures 9
Classification of Wire-Limited 3-D Circuits , Three-Dimensional Microprocessors and
Memories , Three-Dimensional Networks-on-Chip , Three-Dimensional FPGA , Case Study:
Clock Distribution Network for 3-D ICs

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Reference Books:
1. Visileios F. Pavlidis (Author), Eby G. Friedman (Author)--Three-dimensional Integrated
Circuit Design (Systems on Silicon) Morgan Kaufmann / Kindle Edition: Amazon, 2010.
2. Antonis Papanikolaou (Editor), Dimitrios Soudris (Editor), Riko Radojcic (Editor)--Three
Dimensional System Integration: IC Stacking Process and Design, Publisher: Springer; 2011.
3. Yuan Xie (Editor), Jingsheng Jason Cong (Editor), Sachin Sapatnekar (Editor)--Three-
Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures (Integrated
Circuits and Systems),Publisher: Springer, 2010 .

ECE6313-RELIABILITY & TESTING OF IC AND L T P C

MICROSYSTEMS 3 0 0 3
Regulation R2015
Description: This course presents EMI environment, EMI control techniques, EMC
design of PCBs, signal integrity, Reliability of IC Design.
Unit I EMI Environment 9
Definition of EMI and EMC with examples, Classification of EMI/EMC - CE, RE, CS, RS,
Sources of EMI, EMI coupling modes - CM and DM, ESD Phenomena and effects,
conducted and radiated EMI, Conducted, Radiated and Transient Coupling, EMI/EMC
standards and measurements- Civilian standards, Military standards, EMI Test Instruments
/Systems, Test beds for ESD and EFT, Military Test Method and Procedures (462), Basic
principles of RE, CE, RS and CS measurements, EMI measuring instruments
Unit II EMI control techniques 9
Shielding, Filtering, Grounding, Bonding, EMI gasket, Isolation transformer, opto-isolator,
Transient suppressors, Cable routing and connection, Signal Control, Component selection
and mounting
Unit III EMC design of PCBs 9
PCB Trace routing, Cross talk, Impedance control, Power distribution decoupling, Zoning,
Motherboard designs and Propagation delay performance models
Unit IV Signal Integrity 9
The Importance of Signal Integrity, Electromagnetic Fundamentals for Signal Integrity, Ideal
Transmission-Line Fundamentals, Crosstalk, Differential Signaling, High-Speed Channel
Modeling, Equalization
Unit V Reliability of IC Design 9
Basic Concepts, Quality and Reliability Assurance of Complex Equipment’s and Systems,
Probability Theory, Stochastic Process and Mathematical Statistics for , Qualification Tests
for Components and Assemblies Reliability Analysis, Reliability Analysis During the Design
and Development Phases, Maintainability Analysis, Design Guidelines for Reliability,
Maintainability and Software Quality, Statistical Quality Control and Reliability Tests,
Quality and Reliability Assurance During the Production Phase
Reference Books:

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1. Clayton. R.Paul, ―Introduction to Electromagnetic Compatibility , Wiley, 2006.

2.W.Prasad Kodali―Engineering Electromagnetic Compatibility: Principles, Measurements,
Technologies, and Computer Models, Wiley - IEEE Press, 2001.
3. Henry W.Ott, Electromagnetic Compatibility Engineering, Wiley , 2009.
4. Bernhard Keiser, ―Principles of Electromagnetic Compatibility, Artech House, 1987.
5. Alessandro Birolini, Reliability Engineering Theory and Practice, 4th Edn., Springer
(India) Pvt. Ltd., 2006, ISBN: 8181284518
6. Howard Johnson and Martin Graham, "High Speed Digital Design: A Handbook of Black
Magic”,3rd Edition, (Prentice Hall Modern Semiconductor Design Series' Sub Series: PH
Signal Integrity Library), 2006
7. Stephen H. Hall, Garrett W. Hall, and James A. McCall " High-Speed Digital System
Design: A Handbook of Interconnect Theory and Design Practices", Wiley , 2007

L T P C
ECE6314- TEST ENGINEERING – II
3 0 0 3
Regulation R2015
Description: The course continues the testing of the previous semester.
Unit I ATE Architecture 9
DC resources, Digital sub system, AC Source and Measurement, Timing measurement unit,
Computing Hardware.
Unit II Digital Testing 9
Verification of functional parameters, IDDQ, ATPG, Functional test and AT speed testing,
AC parameters. Test mode, High Speed Loop Back testing, propagation delay, rise time and
fall time measurement, jitter measurement, Memory Testing. BIST
Unit III Sampling theory 9
Analog measurements Using DSP, Sampling and reconstruction, repetitive sample sets,
synchronization of sampling system DSP based testing: Advantage of DSP based testing,
Digital signal Processing, discrete Time Transforms, The inverse FFT.
Unit IV Analog and Mixed signal testing 9
Analog channel testing: Overview, Gain and Level Tests, Phase Test, Distortion Tests, Signal
Rejection Tests, Noise Tests.
Sampled Channel Testing: Overview, sampling considerations, Encoding and Decoding,
Sampled channel Tests
DAC testing: Basics of converter testing, DC Tests, Transfer curve Tests, Dynamic DAC
Tests, Tests For Common DAC Applications
ADC testing : ADC Testing versus DAC Testing, ADC code edge measurement, DC TESTS
and Transfer Curve Tests., Dynamic ADC Tests, Tests for common ADC Application
Unit V DIB Design 9
DIB Basics, PCB, DIB TRACES, Shields and guards, Transmission Lines, Grounding and
Power distribution, Dib components, common dib circuits, common dib mistakes

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Characterization program: Objectives, Test Vector and Characterization, Binary Search,

Linear search, Common Characterization Parameters, Test System Data logger, use of Test
system tools, Shmoo Plots, Threshold/Level Search, Go no go testing
Test data analysis: Introduction to data analysis, data visualization tools, statistical Analysis,
statistical Process control
Reference Books:
1. Mark Burns, Gordon W Roberts, An Introduction to Mixed-Signal IC Test and
Measurement, Oxford Univ Pr (Sd); 2 edition (14 October 2011)
2. Michael L. Bushnell, Vishwani D. Agrawal, Essentials of Electronic Testing for
Digital, Memory & mixed Signal Testing VLSI Circuits, Springer; 1st Corrected ed.
2002. Corr. 2nd printing 2004 edition (12 January 2005)

L T P C
ECE6315 – RTL to GDS-II
3 0 0 3
Regulation R2015
Description: The course deals with topics related to back-end design of ICs.
Unit I Design flows, Logic synthesis 9
Invention, Implementation Integration Future Scaling Challenges, Behavioral and Register
Transfer-Level Synthesis Two-Level Minimization, Multilevel Logic Minimization
,Enabling Technologies for Logic Synthesis, Sequential Optimization, Physical Synthesis,
Multivalued Logic Synthesis.
Unit II Power Analysis and Optimization from Circuit to 9
Register-Transfer Levels, Equivalence Checking
Introduction ,Power Analysis , Circuit-Level Power Optimization , Logic Synthesis for Low
Power, Equivalence Checking , Boolean Reasoning Combinational Equivalence Checking,
Sequential Equivalence Checking
Unit III Digital Layout — Placement, Static Timing Analysis 9
Introduction: Placement Problem and Contexts, Global Placement , Detailed Placement and
Legalizers ,Placement Trends ,Academic and Industrial Placers, Representation of
Combinational and Sequential Circuits ,Gate Delay Models , Timing Analysis for
Combinational Circuits ,Timing Analysis for Sequential Circuits , Clocking Disciplines:
Edge-Triggered Circuits , Clocking and Clock-Skew Optimization , Statistical Static Timing
Analysis
Unit IV Structured Digital Design, Routing and Exploring 9
Challenges of Libraries for Electronic Design
Introduction ,Datapaths ,Programmable Logic Arrays Memory and Register Files ,Structured
Chip Design, types of Routers , A Brief History of Routing ,Common Routing Algorithms,
Additional Router Considerations , What Does It Mean to Design Libraries, How Did We
Get Here, Anyway,Commercial Efforts , What Makes the Effort Easier? ,The Enemies of
Progress Environments That Drive Progress ,Libraries and What They Contain.

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Unit V Design Closure, Tools for Chip-Package Codesign, 9

Design Databases, FPGA Synthesis and Physical Design
Introduction , Current Practice , The Future of Design Closure, Drivers for Chip-Package
Codesign Digital System Codesign Issues , Mixed-Signal Codesign Issues , I/O Buffer
Interface Standard and Other Macromodels, Modern Database ,Fundamental , Advanced
Features,Technology, Library Data and Structures: Design-Data Management,
Interoperability Models , System-Level Tools ,Logic Synthesis ,Physical Design Looking
Forward .
Reference Books
1. Dan Clein “CMOS IC Layout: Concepts, Methodologies, and Tools” Newnes, 2000.
2. Ray Alan Hastings, The Art of Analog Layout, Prentice Hall, 2006.
3. Hurst ,”Custom-Specific Integrated Circuits: Design and Fabrication”, CRC Press, 1985.
4. Louis Scheffer, Luciano Lavagno, and Grant Martin, EDA for IC Implementation,Circuit
Design, and Process Technology,CRC press, 2006

L T P C
ECE6316-FULL CUSTOM DESIGN
3 0 0 3
Regulation R2015
Description: Full-custom design is a methodology for designing integrated circuits by
specifying the layout of each individual transistor and the
interconnections between them .This course deals with different types of
layouts, advanced techniques for building block interconnect layout,
layout electrical characteristics, layout considerations and computer aided
design of layouts.
Unit I Schematic Fundamentals, Layout Designs 9
Layout design overview, ic design flow, The MOS transistor- the basic circuit structure, logic
gates, transmission gates, understanding the schematic connectivity, review of fundamental
laws, Overview of CMOS VLSI manufacturing.
Unit II Block Interconnect Layout Design 9
Flow, microprocessor design flow, ASSPs, Memories, System on chip, or SOC,CAD tools as
part of a flow Standard cell libraries, special logic cells, pad cells, memory design leaf cells,
laser fuse cells, chip finishing cells
Unit III Layout Design Techniques To Address Electrical 9
Characteristics
Power grid, clock signals, interconnect routing, Resistance, capacitance, symmetry, special
electrical requirements Wide metal slits, large metal via implementations, step coverage
rules, multiple rule sets, antenna rules, special design rules, latch-up
Unit IV Layout Considerations 9
Layout of circuits designed for change, planning for unknown changes, engineering change

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orders, guidelines for proper layout

Unit V Computer –Aided Design(CAD) Tools For Layout 9
Overview, planning tools, layout generation tools, support tools
Reference Books
1. Dan Clein “CMOS IC Layout: Concepts, Methodologies, and Tools” Newnes, 2000.
2. Ray Alan Hastings, The Art of Analog Layout, Prentice Hall, 2006.
3. Hurst ,”Custom-Specific Integrated Circuits: Design and Fabrication”, CRC Press, 1985.

ECE6317-LOGIC ANALYSIS AND L T P C

SYNTHESIS 3 0 0 3
Regulation R2015
Description: This course covers the basics of digital logic circuits and design. Through
the basic understanding of Boolean algebra and number systems it
introduces the student to the fundamentals of combinational logic design
and then to sequential circuits (both synchronous and asynchronous).
Memory systems are also covered. Finally, the student is introduced to
Register Transfer Logic design and the structured implementation of
controllers and microprogrammed computers, RISC CPU case study and
Hw/Sw Co-Design
Unit I High-level synthesis 9
Introduction to Synthesis and optimization: High-level synthesis: Motivation and
organization Scheduling Resource sharing, Data path and control synthesis
Unit II Logic synthesis 9
Logic synthesis: Algorithms and rule-based systems, Algebraic and Boolean methods,
Unit III Timing issues 9
Timing issues: Sequential synthesis and retiming, Semicustom libraries & library mapping
Algorithms and rule-based systems Structural and Boolean matching
Unit IV Optimization of digital circuits 9
Optimization of digital circuits: Area, Timing and power optimization. RTL Coding for
area, timing and power optimization. Synthesis and Generation of area, timing and power
reports: RISC CPU a case study.
Unit V Hw/Sw Co-Design 9
Introduction to Hw/Sw Codesign, Problem taxonomy Embedded system design Software
optimization Perspectives

Reference Books
1. Giovanni De Micheli, “Synthesis and Optimization of Digital Circuits”, McGraw-Hill,
1994, 5th print.
2. “Logic Synthesis”, S. Devadas, A. Ghosh and K. Keutzer, McGraw Hill, 1994.
3. R. Gupta, “Co-synthesis of Hardware and Software for Embedded Systems”, Kluwer

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M.Tech. Semiconductor Testing and Packaging Regulation R2015

1995.
4. Edwars M.D., Automatic Logic synthesis Techniques for Digital Systems, Macmillan
New Electronic Series, 1992
5. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson
Education, 2005.

SEMINAR TOPICS
1. Discrete to VLSI - history and current trends
2. Architecture definition challenge
3. SOC - verification
4. Sytem Verilog and UVM
5. SOC - DFT Architecures
6. SOC - DFT - At=Speed testing
7. SOC - DFT - Compression
8. SOC- DFT- design2silicon - stimulus - simulation to silicon challenges
9. Need for automation in VLSI
10.SOC implementation challenges
11.Low power Design
12.Simulation vs Silicon
13.Process technology trends
14.Choosing right process technology
15.Why Test? Need for and current trends
16. ATE Digital test
17.ATE - Analog and Mixed-Signal Test
18. Test Economics
19. Protocol Test
20.ATE h/w design challenges
21.High Speed I/F Test
22.Wafer Probe Challenges
23.Yield Analysis
24. Test Economics
25 Volume Debug

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